CXG1158K Power Amplifier Module for JCDMA Description The CXG1158K is the power amplifier module which operates at a single power supply. This IC is designed using the Sony's original p-Gate HFET process. 10 pin LCC (Ceramic) Features • Single power supply operation: VDD1 = VDD2 = 3.5V (High Power Mode), 1.3V (Low Power Mode 1), 1.0V (Low Power Mode 2), VGG = 2.7V • Ultrasmall package: 0.06cc (6.2mm × 6.2mm × 1.55mm) • High efficiency: ηadd = 41%@POUT = 27.5dBm (High Power Mode), ηadd = 23%@POUT = 15dBm (Low Power Mode 1) • Output power (high/low mode switching supported): POUT = 18 to 27.5dBm: High Power Mode, POUT = 15 to 18dBm: Low Power Mode 1, POUT ≤ 15dBm: Low Power Mode 2 • Gain: Gp = 29dB (@900MHz) Applications Power amplifier for JCDMA system cellular phones Structure p-Gate HFET module Absolute Maximum Ratings • Operating ambient temperature • Operating case temperature • Storage temperature • Bias voltage • Bias voltage • Input power Ta –30 to +60 °C Tcase –30 to +90 °C Tstg –30 to +125 °C VDD1, VDD2 6 V VGG 3.3 V (@VDD1 = VDD2 ≤ 3.5V) PIN 8 dBm Recommended Bias Voltage Conditions • VDD1 = VDD2 = 1.0 to 4.2V • VGG = 2.7V ± 1% GaAs module is ESD sensitive devices. Special handling precautions are required. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E03511-PS CXG1158K Package Outline/Pin Configuration Front GND GND 10 9 PIN 1 8 VGG VDD1 2 7 GND VDD2 3 6 POUT 6 POUT 7 GND 8 VGG 4 5 GND GND GND GND 4 5 Back VDD2 3 VDD1 2 PIN 1 11 GND 10 9 GND GND Note) GND (Pin 11) should be soldered on the land of the board. For the land to which GND (Pin 11) area is connected, make the through holes in the land and form the GND pattern. –2– CXG1158K Electrical Characteristics Item (ZS = ZL = 50Ω, IS-95 Modulation, Ta = 25°C) Conditions Min. Typ. 887 Frequency Max. Unit 925 MHz Current consumption 1 POUT = 27.5dBm, VDD = 3.5V, VGG = 2.7V 395 410 mA Current consumption 2 POUT = 15dBm, VDD = 1.3V, VGG = 2.7V 103 110 mA Current consumption 3 POUT = 12dBm, VDD = 1.0V, VGG = 2.7V 76 90 mA Gain 1 POUT = 27.5dBm, VDD = 3.5V, VGG = 2.7V 25 29 dB Gain 2 POUT = 18dBm, VDD = 1.3V, VGG = 2.7V 22 23.5 dB Gain 3 POUT = 15dBm, VDD = 1.0V, VGG = 2.7V 20 22 dB ACPR1 (High Power Mode) POUT = 27.5dBm, VDD = 3.5V, VGG = 2.7V, ±900kHz offset, 30kHz band width –54 –47 dBc ACPR2 (High Power Mode) POUT = 27.5dBm, VDD = 3.5V, VGG = 2.7V, ±1.98MHz offset, 30kHz band width –63 –58 dBc ACPR1 (Low Power Mode 1) POUT = 18dBm, VDD = 1.3V, VGG = 2.7V, ±900kHz offset, 30kHz band width –55 –50 dBc ACPR2 (Low Power Mode 1) POUT = 18dBm, VDD = 1.3V, VGG = 2.7V, ±1.98MHz offset, 30kHz band width –62 –57 dBc ACPR1 (Low Power Mode 2) POUT = 15dBm, VDD = 1.0V, VGG = 2.7V, ±900kHz offset, 30kHz band width –55 –50 dBc ACPR2 (Low Power Mode 2) POUT = 15dBm, VDD = 1.0V, VGG = 2.7V, ±1.98MHz offset, 30kHz band width –62 –57 dBc 2nd, 3rd harmonics POUT = 27.5dBm, VDD = 3.5V, VGG = 2.7V –30 –23 dBc Input VSWR VDD = 3.5V, VGG = 2.7V 1.2 2 Gate current VGG = 2.7V, POUT ≤ 27.5dBm 1.7 2.5 –3– mA CXG1158K Recommended External Circuit GND C1: 1µF C2: 10µF GND PIN VGG C1 C2 VDD1 C2 C1 C2 C1 GND GND VDD2 POUT GND GND Recommended Evaluation Board Board material: Glass fabric-base epoxy Size: 40mm × 50mm × 0.6mm Relative dielectric constant: 4.6 Front Back VGG GND C2 GND C1 PIN POUT VDD1 C1 C1 C2 C2 GND GND VDD2 –4– CXG1158K Example of Representative Characteristics Conditions: f = 900MHz VDD1 = VDD2 = 3.5V, VGG = 2.7V (High Power Mode) VDD1 = VDD2 = 1.3V, VGG = 2.7V (Low Power Mode 1) Ta = 25°C IDD vs. POUT 600 550 500 400 350 300 250 200 150 100 50 0 ACPR1 vs. POUT ACPR2 vs. POUT VDD = 3.5V VDD = 1.3V ACPR2 [dBc] ACPR1 [dBc] 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 POUT [dBm] PIN [dBm] –34 –36 –38 –40 –42 –44 –46 –48 –50 –52 –54 –56 –58 –60 –62 –64 –66 –68 –70 –72 –74 VDD = 3.5V VDD = 1.3V 450 IDD [mA] POUT [dBm] POUT vs. PIN 32 30 VDD = 3.5V 28 VDD = 1.3V 26 24 22 20 18 16 14 12 10 8 6 4 2 –26 –24 –22 –20 –18 –16 –14 –12 –10 –8 –6 –4 –2 0 2 4 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 POUT [dBm] –48 –50 –52 –54 –56 –58 –60 –62 –64 –66 –68 –70 –72 –74 –76 –78 VDD = 3.5V VDD = 1.3V 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 POUT [dBm] –5– CXG1158K Package Outline Unit: mm 10PIN LCC(CERAMIC) SOLDERING POINT X 6.0 6.0 + 0.5 ∗6.2 - 0.3 + 0.15 1.55 - 0.17 0.1Max 0.2 S PIN 1 INDEX 0.1 S ∗6.2 ± 0.3 S SOLDERING POINT DETAILX 3.8 Y 1.6 5 2 7 1 8 1.1 ± 0.15 6 4.9 3 3.4 ± 0.15 TERMINAL 1.7 ± 0.1 4 0.15 1.4 0.9 COAT SUBSTRATE COAT 10 2 0.15 0.15 C0.1 9 2-R0.2 2-R0.2 R0.2 0.15 4-R0.2 0.6 ± 0.2 DETAILY TERMINAL PACKAGE STRUCTURE NOTE: Dimension "∗" does not include cutting burr. SONY CODE LCC-10C-361 PACKAGE MATERIAL CERAMIC SUBSTRATE TERMINAL TREATMENT GOLD PLATING JEITA CODE TERMINAL MATERIAL NICKEL PLATING JEDEC CODE PACKAGE MASS 0.2g –6– Sony Corporation