CXK58512TM/M -55LL/70LL/10LL ∗ 65536-word × 8-bit High Speed CMOS Static RAM ∗Under For the availability of this product, please contact the sales office. development Description The CXK58512TM/M is a high speed CMOS static RAM organized as 65536-words by 8 bits. A polysilicon TFT cell technology realized extremely low stand-by current and higher data retention stability. Special feature are low power consumption, high speed. The CXK58512TM/M is a suitable RAM for portable equipment with battery back up. Features • Fast access time (Access time) -55LL 55ns (Max.) -70LL 70ns (Max.) -10LL 100ns (Max.) • Low standby current 10µA (Max.) • Low data retention current 6µA (Max.) • Single +5V supply: +5V ± 10% • Low voltage data retention: 2.0V (Min.) • Broad package line-up CXK58512TM 8mm × 20mm 32 pin TSOP package CXK58512M 525mil 32 pin SOP Package CXK58512TM 32 pin TSOP (Plastic) Block Diagram A15 A13 A8 A11 A9 A7 A6 A5 A14 A12 Buffer A4 A3 A10 A0 A2 A1 Buffer Row Decoder Memory Matrix 1024 × 512 VCC GND I/O Gate Column Decoder OE Function 65536-word × 8 bit static RAM Structure Silicon gate CMOS IC CXK58512M 32 pin SOP (Plastic) Buffer WE CE1 CE2 I/O Buffer I/O1 I/O8 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E94915A58-PK CXK58512TM/M Pin Configuration (Top View) A11 A9 A8 A13 WE CE2 A15 Vcc NC NC A14 A12 A7 A6 A5 A4 Pin Description 32 OE 31 A10 1 2 30 CE1 29 I/O8 3 4 5 7 8 9 30 CE2 A12 4 29 WE 26 I/O5 A7 5 A6 6 28 A13 24 GN D 10 31 A15 A14 3 25 I/O4 CXK58512TM 32 Vcc NC 2 27 I/O6 28 I/O7 6 NC 1 A5 25 9 24 A1 0 A0 1 1 23 CE1 I/O2 1 20 I/O6 12 21 I/O1 A3 13 20 A0 A2 14 19 A1 18 A2 A3 17 16 A9 26 8 23 I/O3 22 I/O2 A4 A0 to A15 Address input I/O1 to I/O8 Data input output CE1, CE2 Chip enable 1, 2 input WE Write enable input OE Output enable input VCC Power supply GND Ground NC No connection A11 OE A10 22 I/O8 1 I/O1 12 21 I/O7 3 I/O3 1 4 GND 15 19 16 17 18 I/O5 I/O4 CXK58512M Absolute Maximum Ratings Item (Ta = 25°C, GND = 0V) Symbol Rating Unit V Supply voltage VCC Input voltage VIN –0.5 to +7.0 –0.5∗ to VCC + 0.5 Input and output voltage VI/O –0.5∗ to VCC + 0.5 V Allowable power dissipation PD 0.7 W Operating temperature Topr 0 to +70 °C Storage temperature Tstg –55 to +150 °C Soldering temperature • time Tsolder 235 • 10 °C • s V ∗ VIN, VI/O = –3.0V Min. for pulse width less than 50ns. Truth Table CE1 CE2 OE WE Mode I/O pin VCC Current H × × × Not selected High Z ISB1, ISB2 × L × × Not selected High Z ISB1, ISB2 L H H H Output disable High Z ICC1, ICC2, ICC3 L H L H Read Data out ICC1, ICC2, ICC3 L H × L Write Data in ICC1, ICC2, ICC3 ×: "H" or "L" DC Recommended Operating Conditions Item Description A8 7 11 15 27 Symbol (Ta = 0 to +70°C, GND = 0V) Symbol Min. Typ. Max. Unit Supply voltage VCC 4.5 5.0 5.5 V Input high voltage VIH 2.2 — VCC + 0.3 V Input low voltage VIL –0.3∗ — 0.8 V ∗ VIL = –3.0V Min. for pulse width less than 50ns. –2– CXK58512TM/M Electrical Characteristics • DC Characteristics Item (VCC = 5V ± 10%, GND = 0V, Ta = 0 to +70°C) Symbol Test conditions Min. Typ.∗ Max. Unit Input leakage current ILI VIN = GND to VCC –1 — +1 µA Output leakage current ILO CE1 = VIH or CE2 = VIL or OE = VIH or WE = VIL VI/O = GND to VCC –1 — +1 µA Operating power supply current ICC1 CE1 = VIL, CE2 = VIH VIN = VIH or VIL IOUT = 0mA — 7 15 mA -55LL — 45 90 ICC2 Min. cycle duty = 100% IOUT = 0mA -70LL — 40 70 -10LL — 35 60 — 10 20 — — 10 — — 2 — 0.4 1 Average operating current ICC3 Cycle time 1µs duty = 100% IOUT = 0mA CE1 ≤ 0.2V CE2 ≥ Vcc – 0.2V VIL ≤ 0.2V VIH ≥ Vcc – 0.2V CE2 ISB1 Standby current o orr 0 to +70°C 0.2V CE1 ≥ Vcc – 0.2V 0 to +40°C CE2 ≥ Vcc – 0.2V +25°C mA mA µA ISB2 CE1 = VIH or CE2 = VIL — 0.6 3 mA Output high voltage VOH IOH = –1.0mA 2.4 — — V Output low voltage VOL IOL = 2.1mA — — 0.4 V ∗ VCC = 5V, Ta = 25°C –3– CXK58512TM/M I/O capacitance (Ta = 25°C, f = 1MHz) Item Symbol Test conditons Min. Typ. Max. Unit Input capacitance CIN VIN = 0V — — 7 pF I/O capacitance CI/O VI/O = 0V — — 8 pF Note) This parameter is sampled and is not 100% tested. AC Characteristics • AC test conditions (VCC = 5V ± 10%, Ta = 0 to +70°C) Item Conditions Input pulse high level VIH = 2.2V Input pulse low level VIL = 0.8V Input rise time tr = 5ns Input fall time tf = 5ns Input and output reference level -55LL 1.5V CL∗ = 30pF, 1TTL -70LL/10LL CL∗ = 100pF, 1TTL Output load conditions • Test circuit TTL CL ∗ CL includes scope and jig capacitances. –4– CXK58512TM/M (Vcc = 5V ± 10%, GND = 0V, Ta = 0 to +70°C) • Read cycle (WE = "H") Item tRC Read cycle time -55LL Symbol tAA tCO1 Chip enable access time (CE1) tCO2 Chip enable access time (CE2) tOE Output enable to output valid tOH Output hold from address change Chip enable to output in low Z (CE1, CE2) tLZ1, tLZ2 tOLZ Output enable to output in low Z (OE) Chip disable to output in high Z (CE1, CE2) tHZ1∗, tHZ2∗ tOHZ∗ Output disable to output in high Z (OE) Address access time -70LL -10LL Unit Min. Max. Min. Max. Min. Max. 55 — 70 — 100 — ns — 55 — 70 — 100 ns — 55 — 70 — 100 ns — 55 — 70 — 100 ns — 30 — 40 — 50 ns 15 — 15 — 15 — ns 10 — 10 — 10 — ns 5 — 5 — 5 — ns — 25 — 25 — 35 ns — 25 — 25 — 35 ns ∗ tHZ1, tHZ2 and tOHZ are defined as the time required for outputs to turn to high impedance state and are not referred to as output voltage levels. (Vcc = 5V ± 10%, GND = 0V, Ta = 0 to +70°C) • Write cycle Item Write cycle time Address valid to end of write Chip enable to end of write Data to write time overlap Data hold from write time Write pulse width Address setup time Write recovery time (WE) Write recovery time (CE1, CE2) Output active from end of write Write to output in high Z -55LL Symbol -70LL -10LL Unit Min. Max. Min. Max. Min. Max. tWC tAW tCW tDW tDH tWP tAS tWR tWR1 55 — 70 — 100 — ns 50 — 60 — 70 — ns 50 — 60 — 70 — ns 25 — 30 — 40 — ns 0 — 0 — 0 — ns 40 — 50 — 70 — ns 0 — 0 — 0 — ns 0 — 0 — 0 — ns 0 — 0 — 0 — ns tOW tWHZ∗ 10 — 10 — 10 — ns — 25 — 25 — 30 ns ∗ tWHZ is defined as the time required for outputs to turn to high impedance state and is not referred to as output voltage level. –5– CXK58512TM/M Timing Waveform • Read cycle (1) : CE1 = OE = VIL, CE2 = VIH, WE = VIH tRC Address tAA tOH Data out Previous data valid Data valid • Read cycle (2) : WE = VIH tRC Address tAA CE1 tCO ttHZ1 HZ 1 tLZ 1 CE2 tCO 2 tLZ tHZ 2 2 OE tOE tOHZ tOLZ Data out Data valid High impedance –6– CXK58512TM/M • Write cycle (1) : WE control tWC Address tWR tAW OE tCW CE1 tCW CE2 *1 tWP tAS WE tDW tDH Data valid Data in tWHZ tOW Data out High impedance *2 *2 • Write cycle (2) : CE1 control tWC Address tAW OE tAS tCW tWR1 *3 CE1 tCW CE2 tWP WE tDH tDW Data valid Data in Data out High impedance –7– CXK58512TM/M • Write cycle (3) : CE2 control tWC Address tAW OE tCW CE1 tCW tAS tWR1 *3 CE2 tWP WE tDH tDW Data valid Data in Data out High impedance ∗1 Write is executed when both CE1 and WE are at low and CE2 is at high simultaneously. ∗2 Do not apply the data input voltage of the opposite phase to the output while I/O pin is in output condition. ∗3 tWR1 is tested from either the rising edge of CE1 or the falling edge of CE2, whichever comes earlier, until the end of the write cycle. –8– CXK58512TM/M Data retention waveform • Low supply voltage data retention waveform (1) (CE1 control) tCDRS Data retention mode tR VCC 4.5V 2.2V VDR CE1 CE1 VCC| 0.2V GND • Low supply voltage data retention waveform (2) (CE2 control) Data retention mode VCC 4.5V tCDRS tR CE2 VDR 0.4V CE2 0.2V GND Data Retention Characteristics Item Data retention voltage Data retention current Symbol Test conditions Min. Typ. Max. Unit 2.0 — 5.5 V 0 to +70°C — — 6 0 to +40°C — — 1.2 +25°C VDR ∗ ICCDR1 VCC = 3.0V∗ — 0.2 0.6 ICCDR2 VCC = 2.0 to 5.5V∗ — 0.4 10 µA Chip disable to data retention mode 0 — — ns 5 — — ms Data retention setup time tCDRS Recovery time (Ta = 0 to +70°C) tR ∗ CE1 ≥ Vcc – 0.2V, CE2 ≥ Vcc – 0.2V (CE1 control) or CE2 ≤ 0.2V (CE2 control) –9– µA CXK58512TM/M Example of Representative Characteristics Supply current vs. Supply voltage 1.2 ICC1, ICC2– Supply current (Relative Value) ICC1, ICC2– Supply current (Relative Value) 1.5 1.25 1.0 ICC 2 ICC 1 0.75 Ta = 25°C 0.5 4.5 Supply current vs. Ambient temperature 1.1 ICC2 (Read) 1.0 ICC2 (Write) ICC1 0.9 VCC = 5.0V 0.8 4.75 5 5.25 5.5 0 Supply current vs. Frequency 55ns Write 0.8 Read 0.6 0.4 VCC = 5.0V Ta = 25°C 0.2 0 0 4 8 12 16 E 1.6 1.4 1.2 TAA, TCO1, TCO2 1.0 VCC = 5.0V Ta = 25°C 0.8 0.6 20 0 100 200 300 400 CL– Load capacity [pF] Access time vs. Ambient temperature TAA, TCO1, TCO2, TOE– Access time (Relative Value) TAA, TCO1, TCO2, TOE– Access time (Relative Value) 80 TO 1.8 Access time vs. Supply voltage 1.4 1.2 TO E 1.0 TAA, TCO1, TCO2 0.8 Ta = 25°C 4.75 5 5.25 VCC– Supply voltage [V] 60 2.0 Frequency (1 / tRC, 1 / tWC) [ MHz] 0.6 4.5 40 Access time vs. Load capacitance TAA, TCO1, TCO2, TOE– Access time (Relative Value) ICC2– Supply current (Relative Value) 70ns 100ns 1.0 20 Ta– Ambient temperature [°C] VCC – Supply voltage [V] 5.5 1.4 1.2 TOE 1.0 TCO1, TCO2, TAA 0.8 VCC = 5.0V 0.6 0 20 40 60 Ta– Ambient temperature [°C] – 10 – 80 CXK58512TM/M Standby current vs. Ambient temperature Standby current vs. Supply voltage 20 ISB1 – Standby current (Relative value) ISB1, ISB2 – Standby current (Relative value) 2.0 1.5 1.0 ISB2 ISB1 0.5 Ta = 25°C 0 2.0 5 2 1 0.5 VCC = 5.0V 0.2 3.0 4.0 5.0 6.0 0 20 40 60 80 VCC – Supply voltage [V] Ta – Ambient temperature [°C] Input voltage level vs. Supply voltage Standby current vs. Ambient temperature 1.2 1.4 ISB2 – Standby current (Relative value) VIL, VIH – Input voltage (Relative value) 10 1.1 VIL, VIH 1.0 0.9 Ta = 25°C 0.8 4.5 1.2 1.0 0.8 VCC = 5.0V 0.6 4.75 5.0 5.25 VCC – Supply voltage [V] 0 5.5 20 40 60 80 Ta – Ambient temperature [°C] Output high current vs. Output high voltage Output low current vs. Output low voltage IOL – Output low current (Relative value) IOH – Output high current (Ralative value) 1.4 1.2 1.0 0.8 VCC = 5.0V Ta = 25°C 1.8 1.4 1.0 VCC = 5.0V Ta = 25°C 0.6 0.6 1 2 3 4 VOH – Output high voltage [V] 0 5 0.2 0.4 0.6 VOL – Output low voltage [V] – 11 – 0.8 CXK58512TM/M Package Outline Unit: mm CXK58512TM 32PIN TSOP (I) (PLASTIC) + 0.2 1.07 – 0.1 8.0 ± 0.2 17 32 0.1 0.5 ± 0.1 20.0 ± 0.2 ∗18.4 ± 0.2 0.1 ± 0.1 0° to 10° DETAIL A A + 0.08 0.2 – 0.03 1 16 + 0.05 0.02 0.127 – 0.08 M 0.5 NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY / PHENOL RESIN SONY CODE TSOP (I) -32P-L01 LEAD TREATMENT SOLDER PLATING EIAJ CODE TSOP (I) 032-P-0820-A LEAD MATERIAL 42 ALLOY JEDEC CODE PACKAGE WEIGHT CXK58512M 32PIN SOP (PLASTIC) 525mil + 0.4 20.5 – 0.1 + 0.15 2.9 – 0.25 32 17 16 0.4 ± 0.1 A + 0.1 0.15 – 0.05 1.27 0.2 ± 0.1 0.8 ± 0.2 1 11.9 14.0 ± 0.4 + 0.3 11.2 – 0.1 0.1 0° to 10° 0.12 M DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY / PHENOL RESIN SONY CODE SOP-32P-L02 LEAD TREATMENT SOLDER PLATING EIAJ CODE ∗SOP032-P-0525-A LEAD MATERIAL 42 ALLOY JEDEC CODE PACKAGE WEIGHT – 12 –