SONY CXK77B1810AGB

CXK77B1810AGB -5/6
High Speed Bi-CMOS Synchronous Static RAM
Preliminary
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Description
The CXK77B1810AGB-5/6 is a high speed 1M bit
Bi-CMOS synchronous static RAM organized as
65536 words by 18 bits. This SRAM integrates input
registers, high speed SRAM and write buffer onto a
single monolithic IC and features the delayed write
system to reduce the dead cycles.
119 pin BGA (Plastic)
Features
• Fast cycle time
(Cycle)
(Frequency)
CXK77B1810AGB-5
5ns
200MHz
-6
6ns
167MHz
• Inputs and outputs are GTL/HSTL compatible
• Controlled Impedance Driver
• Single 3.3V power supply: 3.3V±0.15V
• Byte-write possible
• OE asynchronization
• JTAG test circuit
• Package 119TBGA
• 4 kinds of synchronous operation mode
Register-Register mode (R-R mode)
Register-Flow Thru mode (R-F mode)
Register-Latch mode (R-L mode)
Dual clock mode (D-C mode)
Function
65536 word x 18bit High Speed Bi-CMOS Synchronous SRAM
Structure
Silicon gate Bi-CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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PE96811
CXK77B1810AGB
Block Diagram
16
Input
Reg.
A0 to 15
2:1
Mux
Add.
Dout
64K × 18
Write
Store
Reg.
2:1
Mux
Output
latch
Din
Write
pulse
Reg.
Read
Comp.
S
Reg.
W
Reg.
Self
Time
Write
Logic
2
BW
a to b
Reg.
K/K
Output
Clock
C/C
M1
M2
Mode
Control
G
–2–
DQ
CXK77B1810AGB
Pin Configuration (Top View)
1
2
3
4
5
6
7
A
VDDQ
A
A
NC
A
A
VDDQ
B
NC
NC
NC
NC
NC
NC
NC
C
NC
A
A
VDD
A
A
NC
D
DQb
NC
VSS
ZQ
VSS
DQa
NC
E
NC
DQb
VSS
S
VSS
NC
DQa
F
VDDQ
NC
VSS
G
VSS
DQa
VDDQ
G
NC
DQb
BWb
C
VSS
NC
DQa
H
DQb
NC
VSS
C
VSS
DQa
NC
J
VDDQ
VDD
VREF
VDD
VREF
VDD
VDDQ
K
NC
DQb
VSS
K
VSS
NC
DQa
L
DQb
NC
VSS
K
BWa
DQa
NC
M
VDDQ
DQb
VSS
W
VSS
NC
VDDQ
N
DQb
NC
VSS
A
VSS
DQa
NC
P
NC
DQb
VSS
A
VSS
NC
DQa
R
NC
A
M1
VDD
M2
A
NC
T
NC
A
A
NC
A
A
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Pin Description
Symbol
Description
Symbol
Description
Symbol
Description
A
Address Input
BWX
Byte Write Enable
(a to b)
VDD
+3.3V power supply
DQx
Data I/O in byte
(a to b)
S
Chip Select
VDDQ
Output power supply
K
Positive Clock
G
Asyn Output Enable
VSS
Ground
K
Negative Clock
ZZ
Sleep Mode Select
M1, M2
Mode Select
C
Output Positive Clock(∗) TCK
JTAG Clock
ZQ
Output Impedance
Control
C
Output Negative
Clock(∗)
TMS
JTAG Mode Select
NC
No Connect
VREF
Input Reference
TDI
JTAG Data In
Write Enable
JTAG Data Out
TDO
W
(∗) These pins should be tied to VDD or VSS except D-C mode.
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CXK77B1810AGB
Package Outline
Unit: mm
119 TER M IN AL BG A(PLASTIC )
X
3.19
C
4-
0.84
C
1 2 3 4 5 6 7
5
1.
3C
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
C
1.
0
22.0
19.5
6
0.
~4
0.35 C
1.27
20.32
B
11.5
7.62
0.6}0. 1
A
1.27
14.0
0.10
0.6}0. 1
0. 75}0. 15
0. 3
1.5
C
A
B
0. 1
0.15 C
D ETAIL X
PAC KAG E STR U C TU R E
PAC KAG E M ATER IAL
EPO XY R ESIN
BO AR D M ATER IAL
C O PPER -C LAD LAM IN ATE
EIAJ C O D E
TER M IN AL M ATER IAL
SO LD ER
JED EC C O D E
PAC KAG E W EIG H T
0.8g
SO N Y C O D E
BG A-119P-01
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