CXP81720B/81724B CMOS 8-bit Single Chip Microcomputer Description The CXP81720B/81724B is a CMOS 8-bit microcomputer which consists of A/D converter, serial interface, timer/counter, time-base timer, highprecision timing pattern generation circuit, PWM output, 32kHz timer/counter, remote control reception circuit, as well as basic configurations like 8-bit CPU, ROM, RAM and I/O port. They are integrated into a single chip. Also CXP81720B/81724B provides sleep/stop functions which enables to lower power consumption. 100 pin QFP (PIastic) 100 pin LQFP (PIastic) Structure Silicon gate CMOS IC Features • A wide instruction set (213 instructions) which covers various types of data — 16-bit arithmetic/multiplication and division/Boolean bit operation instructions • Minimum instruction cycle 250ns at 16MHz operation (4.5 to 5.5V) 122µs at 32kHz operation (2.7 to 5.5V) • Incorporated ROM capacity 20K bytes (CXP81720B) 24K bytes (CXP81724B) • Incorporated RAM capacity 800 bytes • Peripheral functions — A/D converter 8 bits, 12 channels, successive approximation method (Conversion time of 20.0µs at 16MHz) — Serial interface Incorporated 8-bit and 8-stage FIFO, 1 channel (Auto transfer for 1 to 8 bytes) 8-bit clock sync type, 1 channel — Timer 8-bit timer, 8-bit timer/counter, 19-bit time-base timer 32kHz timer/counter — High-precision timing pattern generator PPG: maximum of 19 pins, 32 stages programmable RTG: 5 pins, 2 channels — PWM/DA gate output PWM: 12 bits, 2 channels (Repetitive frequency 62kHz/16MHz) DA gate pulse output: 12 bits, 4 channels — FRC capture unit Incorporated 26-bit and 8-stage FIFO — PWM output 14 bits, 1 channel — Remote control reception circuit 8-bit pulse measuring counter, 6-stage FIFO • Interruption 20 factors, 15 vectors, multi-interruption possible • Standby mode Sleep/stop • Package 100-pin plastic QFP/LQFP • Piggyback/evaluator CXP81800 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E97737-PS AVDD ADJ 12 BIT PWM GENERATOR CH1 12 BIT PWM GENERATOR CH0 14 BIT PWM GENERATOR PWM PWM0 DAA0 DAB0 PWM1 DAA1 DAB1 REMOCON INPUT RMC EXI1 FIFO 8 BIT TIMER 1 EXI0 8 BIT TIMER/COUNTER 0 TO FIFO EC SERIAL INTERFACE UNIT (CH0) A/D CONVERTER 2 4 2 2 2 INT0 NMI INT2 XTAL RST MP RAM 800 BYTES CH0 CH1 REALTIME PULSE GENERATOR 32kHz TIMER/COUNTER PRESCALER/ TIME BASE TIMER 5 2 VDD Vss CLOCK GENERATOR/ SYSTEM CONTROL AA 19 RAM PROGRAMMABLE PATTERN GENERATOR ROM 20K/24K BYTES SPC700 CPU CORE FIFO INT1/NMI FRC CAPTURE UNIT INTERRUPT CONTROLLER AVREF SERIAL INTERFACE UNIT (CH1) 12 AVss SI1 SO1 SCK1 CS0 SI0 SO0 SCK0 AN0 to AN11 TEX TX EXTAL PPO0/PPO18 PF4 to PF7 PG0 to PG7 PH0 to PH7 4 8 8 7 8 PJ0 to PJ7 PI1 to PI7 PF0 to PF3 PE2 to PE7 PE0 to PE1 PD0 to PD7 PC0 to PC7 PB0 to PB7 PA0 to PA7 4 6 2 8 8 8 8 PORT G –2– RTO3/RTO7 PORT A PORT B PORT C PORT D PORT E PORT F PORT H PORT I PORT J Block Diagram CXP81720B/81724B CXP81720B/81724B PI5/SCK1 PI4/INT1/NMI PI3/TO/ADJ PI2/PWM PI1/RMC TEX TX VDD VSS NC PA7/PPO7 PA6/PPO6 PA5/PPO5 PA4/PPO4 PA3/PPO3 PA2/PPO2 PA1/PPO1 PA0/PPO0 PB7/PPO15 PB6/PPO14 Pin Assignment (Top View) 100-pin QFP package 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PB5/PPO13 1 80 PI6/SO1 PB4/PPO12 2 79 PI7/SI1 PB3/PPO11 3 78 PE0/INT0 PB2/PPO10 4 77 PE1/EC/INT2 PB1/PPO9 5 76 PE2/PWM0 PB0/PPO8 6 75 PE3/PWM1 PC7/RTO7 7 74 PE4/DAA0 PC6/RTO6 8 73 PE5/DAA1 PC5/RTO5 9 72 PE6/DAB0 PC4/RTO4 10 71 PE7/DAB1 PC3/RTO3 11 70 PG0 PC2/PPO18 12 69 PG1 PC1/PPO17 13 68 PG2 PC0/PPO16 14 67 PG3 PJ7 15 66 PG4 PJ6 16 65 PG5 PJ5 17 64 PG6/EXI0 PJ4 18 63 PG7/EXI1 PJ3 19 62 AN0 PJ2 20 61 AN1 PJ1 21 60 AN2 PJ0 22 59 AN3 PD7 23 58 PF0/AN4 PD6 24 57 PF1/AN5 PD5 25 56 PF2/AN6 PD4 26 55 PF3/AN7 PD3 27 54 AVDD PD2 28 53 AVREF PD1 29 52 AVSS PD0 30 51 PF4/AN8 Note) PF5/AN9 PF6/AN10 PF7/AN11 SCK0 SO0 SI0 CS0 EXTAL XTAL VSS RST MP PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1. NC (Pin 90) is always connected to VDD. 2. Vss (Pins 41 and 88) are both connected to GND. –3– CXP81720B/81724B PE0/INT0 PI7/SI1 PI6/SO1 PI5/SCK1 PI4/INT1/NMI PI3/TO/ADJ PI2/PWM PI1/RMC TEX TX VDD VSS NC PA7/PPO7 PA6/PPO6 PA5/PPO5 PA4/PPO4 PA3/PPO3 PA2/PPO2 PA1/PPO1 PA0/PPO0 PB7/PPO15 PB6/PPO14 PB5/PPO13 PB4/PPO12 Pin Assignment (Top View) 100-pin LQFP package 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PB3/PPO11 1 75 PE1/EC/INT2 PB2/PPO10 2 74 PE2/PWM0 PB1/PPO9 3 73 PE3/PWM1 PB0/PPO8 4 72 PE4/DAA0 PC7/RTO7 5 71 PE5/DAA1 PC6/RTO6 6 70 PE6/DAB0 PC5/RTO5 7 69 PE7/DAB1 PC4/RTO4 8 68 PG0 PC3/RTO3 9 67 PG1 PC2/PPO18 10 66 PG2 PC1/PPO17 11 65 PG3 PC0/PPO16 12 64 PG4 PJ7 13 63 PG5 PJ6 14 62 PG6/EXI0 PJ5 15 61 PG7/EXI1 PJ4 16 60 AN0 PJ3 17 59 AN1 PJ2 18 58 AN2 PJ1 19 57 AN3 PJ0 20 56 PF0/AN4 PD7 21 55 PF1/AN5 PD6 22 54 PF2/AN6 PD5 23 53 PF3AN7 PD4 24 52 AVDD PD3 25 51 AVREF Note) 1. NC (Pin 88) is always connected to VDD. 2. Vss (Pins 39 and 86) are both connected to GND. –4– AVSS PF4/AN8 PF5/AN9 PF6/AN10 PF7/AN11 SO0 SCK0 SI0 CS0 EXTAL XTAL VSS MP RST PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 PD0 PD1 PD2 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 CXP81720B/81724B Pin Description Symbol I/O Description PA0/PPO0 to PA7/PPO7 Output/ Real time output (Port A) 8-bit output port. Data is gated with PPO contents by OR-gate and they are output. (8 pins) PB0/PPO8 to PB7/PPO15 Output/ Real time output (Port B) 8-bit output port. Data is gated with PPO contents by OR-gate and they are output. (8 pins) PC0/PPO16 to PC2/PPO18 I/O/ Real time output PC3/RTO3 to PC7/RTO7 I/O/ Real time output (Port C) 8-bit I/O port. I/O can be set in a unit of single bits. Data is gated with PPO or RTO contents by OR-gate and they are output. (8 pins) Programmable pattern generator (PPG) output. Functions as high-precision real-time pulse output port. (19 pins) Real-time pulse generator (RTG) output. Functions as high-precision real-time pulse output port. (5 pins) (Port D) 8-bit I/O port. I/O can be set in a unit of 4 bits. Can drive 12mA sink current. (8 pins) PD0 to PD7 I/O PE0/INT0 Input/input Input to request external interruption. Active at the falling edge. PE1/EC/INT2 Input/input/input External event Input to request external interruption. input for timer/counter. Active at the falling edge. (Port E) 8-bit port. Lower 2 bits are for input; upper 6 bits are for output. (8 pins) PE2/PWM0 Output/output PE3/PWM1 Output/output PE4/DAA0 Output/output PE5/DAA1 Output/output PE6/DAB0 Output/output PE7/DAB1 Output/output AN0 to AN3 Input PF0/AN4 to PF3/AN7 Input/input PF4/AN8 to PF7/AN11 Output/input (Port F) 8-bit port. Lower 4 bits are for input; upper 4 bits are for output. Lower 4 bits also serve as standby release input pin. (8 pins) SCK0 I/O Serial clock I/O (CH0). SO0 Ouput Serial data output (CH0). SI0 Input Serial data input (CH0). CS0 Input Serial chip select input (CH0). PWM outputs. (2 pins) DA gate pulse outputs. (4 pins) Analog inputs to A/D converter. (12 pins) –5– CXP81720B/81724B Symbol I/O PG0 to PG5 Input PG6/EXI0 Input/input PG7/EXI1 Input/input PH0 to PH7 Output PI1/RMC I/O/input PI2/PWM I/O/output Description (Port G) 8-bit input port. (8 pins) External input to FRC capture unit. (2 pins) (Port H) N-ch open drain output of medium drive voltage (12V) and large current (12mA). (8 pins) Remote control reception circuit input. 14-bit PWM output. (Port I) 7-bit I/O port. I/O port can be set in a unit of single bits. (7 pins) PI3/TO/ADJ I/O/output/output PI4/INT1/ NMI I/O/input/input PI5/SCK1 I/O/I/O PI6/SO1 I/O/output Serial data output (CH1). PI7/SI1 I/O/input Serial data input (CH1). PJ0 to PJ7 I/O EXTAL Input XTAL Output TEX Input TX Output Connects a crystal oscillator for 32kHz timer/counter clock. When used as event counter, input to TEX pin and leave TX pin open. RST Input System reset; active at Low level. MP Input Test mode pin. Always connect to GND. Input to request external interruption and non maskable interruption. Active at the falling edge. Serial clock I/O (CH1). (Port J) 8-bit I/O port. I/O and standby release input function can be set in a unit of single bits. Connnects a crystal oscillator for system clock. When supplying the external clock, input the external clock to EXTAL pin and input opposite phase clock to XTAL pin. Positive power supply of A/D converter. AVDD AVREF Timer/counter, 32kHz oscillation adjustment output. Input Reference voltage input of A/D converter. AVss GND of A/D converter. VDD Positive power supply. Vss GND. Connect both Vss pins to GND. –6– CXP81720B/81724B Input/Output Circuit Formats for Pins Pin When reset Circuit format Port A AA AA Port B PA0/PPO0 to PA7/PPO7 PB0/PPO8 to PB7/PPO15 AAAA AAAA PPO data Ports A, B data Data bus Hi-Z Output becomes active from high impedance by data writing to port register. RD (Port A or B) 16 pins Port C PC0/PPO16 to PC2/PPO18 AA AA AA AA AAAA AAAA AAAA PPO, RTO data Input protection circuit Port C data PC3/RTO3 to PC7/RTO7 Hi-Z IP Port C direction "0" when reset Data bus RD (Port C) 8 pins AA AA AA AA Port D PD0 to PD7 AAAA AAAA AAAA Large current 12mA Port D data IP Port D direction "0" when reset Data bus 8 pins RD (Port D) –7– Hi-Z CXP81720B/81724B Pin Circuit format AAAA AA Port E When reset Schmitt input PE0/INT0 PE1/EC/INT2 Interruption circuit/ event counter IP 2 pins RD (Port E) AA AA AAAA AA AAAA AAAA Port E AA DA gate output, PWM output MPX Hi-Z control PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 Hi-Z Data bus Port E data Hi-Z Port/DA output select "0" when reset Data bus 4 pins RD (Port E) Port E AA AA AAAA AA AAAA AAAA AA DA gate output MPX Hi-Z control PE6/DAB0 PE7/DAB1 Port E data H level Port/DA output select "1" when reset Data bus 2 pins RD (Port E) AN0 to AN3 AA AA AAAA AA AA AAAA Input multiplexer IP 4 pins Port F A/D converter Hi-Z Input multiplexer PF0/AN4 to PF3/AN7 A/D converter IP Hi-Z Data bus 4 pins RD (Port F) –8– CXP81720B/81724B Pin Circuit format AAAA AAAA AAAA AAAA AA AAAA When reset AA AA A Port F PF4/AN8 to PF7/AN11 Port F data Data bus RD (Port F) 4 pins PG0 to PG5 6 pins IP Port F function selection Schmitt input Data bus IP Hi-Z RD (Port G) Note) For PG4 and PG5, CMOS Schmitt input or TTL Schmitt input can be selected with the mask option. Port G PG6/EXI0 PG7/EXI1 AA A AAA IP 2 pins FRC capture unit Hi-Z Data bus RD (Port G) Port H PH0 to PH7 AAA AAA ∗ Port H data AA AA Hi-Z ∗ Large current 12mA Medium drive voltage 12V Data bus 8 pins Hi-Z Input multiplexer "0" when reset Port G A/D converter RD (Port H) AAAAA AAAAAAAA AAAAA AAA AAAAA AAA AAAAA Port I Port I function selection "0" when reset PI2: 14-bit PWM PI2/PWM PI3/TO/ADJ PI3: Timer/counter, 32kHz timer MPX Port I data Port I/O direction "0" when reset Data bus 2 pins RD (Port I) –9– AA AA AA AA IP Hi-Z CXP81720B/81724B AAAA AAAA AAAA AAAA PIn Circuit format Port I AA AA AA AA Port I data PI1/RMC PI4/INT1/NMI PI7/SI1 Port I direction "0" when reset Hi-Z IP Data bus RD (Port I) PI1: Remote control circuit PI4: Interruption circuit PI7: Serial interface CH1 3 pins When reset Schmitt input AAAAA AAAAA AA AAAA AA AAAA AA AAA AAAA AAA AAA AAAA AAAA AAAA AAAA AA AA Port I Port I function selection Serial interface CH1 PI5/SCK1 PI6/SO1 AA A MPX Port I data MPX Port I direction IP "0" when reset Data bus RD (Port I) 2 pins Serial interface CH1 Port J Port J data PJ0 to PJ7 Port J direction "0" when reset Data bus RD (Port J) 8 pins CS0 SI0 Edge detection AA AA AA Hi-Z IP AAAA AA Schmitt input SO0 SO Serial interface CH0 1 pin PI6 is not Schmitt input Standby release IP 2 pins Hi-Z SO output enable – 10 – CS Serial interface CH0 SI AA AA Hi-Z Hi-Z CXP81720B/81724B PIn Circuit format When reset AA AA AA AA SCK SCK0 Serial interface CH0 IP SCK output enable SCK Schmitt input 1 pin AA AA AA AA AA AA AA AA AA AA AA AA EXTAL XTAL EXTAL 2 pins XTAL TEX TX 2 pins Hi-Z TEX • Diagram shows the circuit composition during oscillation. IP • Feedback resistor is removed during stop mode. XTAL becomes High level. 32kHz timer counter • Diagram shows the circuit composition during oscillation. • Feedback resistor is removed during oscillation circuit stop by software. At this time TEX pin outputs Low level and TX pin outputs High level. IP Oscillation Oscillation TX Pull-up resistor RST OP Mask option Schmitt input 1 pin AA A IP – 11 – L level CXP81720B/81724B Absolute Maximum Ratings Item (Vss = 0V) Symbol VDD Supply voltage AVDD Rating Unit –0.3 to +7.0 AVss to +7.0∗1 V V Remarks V Input voltage VIN –0.3 to +0.3 –0.3 to +7.0∗2 Output voltage VOUT –0.3 to +7.0∗2 V Medium drive output voltage VOUTP –0.3 to +15.0 V High level output current IOH –5 mA High level total output current ∑IOH –50 mA Total of all output pins IOL 15 mA IOLC 20 mA Ports excluding large current outputs Large current outputs∗3 Low level total output current ∑IOL 130 mA Total of all output pins Operating temperature Topr –20 to +75 °C Storage temperature Tstg –55 to +150 °C Allowable power dissipation PD AVSS Low level output current V QFP package type 600 380 Port H pin mW LQFP package type ∗1 AVDD and VDD should be set to the same voltage. ∗2 VIN and VOUT should not exceed VDD + 0.3V. ∗3 The large current drive transistors are the N-CH transistors of the PD and PH ports. Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding those conditions may adversely affect the reliability of the LSI. – 12 – CXP81720B/81724B Recommended Operating Conditions Item Min. Max. 4.5 5.5 Guaranteed operation range for 1/2 and 1/4 frequency dividing clocks 3.5 5.5 Guaranteed operation range for 1/16 frequency dividing clock and sleep mode 2.7 5.5 2.5 5.5 4.5 5.5 V Guaranteed data hold range during stop mode ∗1 VIH 0.7VDD VDD V ∗2 VIHS 0.8VDD VDD V VIHTS 2.2 VDD V VIHEX VDD – 0.4 VDD + 0.3 V VIL 0 0.3VDD V VILS 0 0.2VDD V VILTS 0 0.8 V CMOS Schmitt input∗3 TTL Schmitt input∗4 VILEX –0.3 0.4 V EXTAL pin∗5 TEX pin∗6 Operating temperature Topr –20 +75 °C Supply voltage Analog voltage High level input voltage Low level input voltage Symbol (Vss=0V) VDD AVDD Unit V Remarks Guaranteed operation range by TEX clock CMOS Schmitt input∗3 TTL Schmitt input∗4 EXTAL pin∗5 TEX pin∗6 ∗2 ∗1 AVDD and VDD should be set to the same voltage. ∗2 Normal input port (PC, PD, PE0, PE1, PF0 to PF3, PG, PI and PJ pins), MP pin. ∗3 CS0, SI0, SCK0, RST, INT0, EC/INT2, PG (For PG4 and PG5, when CMOS Schmitt input is selected with mask option), RMC, INT1/NMI, SCK1 and SI1 pins. ∗4 PG4 and PG5 pins (When TTL Schmitt input is selected with mask option) ∗5 Specifies only when the external clock is input. ∗6 Specifies only when the event count clock is input. – 13 – CXP81720B/81724B Electrical Characteristics DC Characteristics (VDD = 4.5 to 5.5V) Item High level output voltage Low level output voltage Symbol VOH VOL Pins Input current Min. Typ. Max. Unit VDD = 4.5V, IOH = –0.5mA 4.0 V VDD = 4.5V, IOH = –1.2mA 3.5 V VDD = 4.5V, IOL = 1.8mA 0.4 V VDD = 4.5V, IOL = 3.6mA 0.6 V PD, PH VDD = 4.5V, IOL = 12.0mA 1.5 V EXTAL IIHT IILT Conditions PA to PD, PE2 to PE7, PF4 to PF7, PH (VOL only) PI1 to PI7 PJ, SO0, SCK0 IIHE IILE (Ta = –20 to +75°C, Vss = 0V) TEX VDD = 5.5V, VIH = 5.5V 0.5 40 µA VDD = 5.5V, VIL = 0.4V –0.5 –40 µA VDD = 5.5V, VIH = 5.5V 0.1 10 µA –0.1 –10 µA –1.5 –400 µA IILR RST∗1 VDD = 5.5V, VIL = 0.4V I/O leakage current IIZ PA to PG, PI, PJ, MP AN0 to AN3, CS0, SI0, SO0 SCK0, RST∗1 VDD = 5.5V, VI = 0, 5.5V ±10 µA Open drain output leakage current (in N-ch Tr OFF state) ILOH PH VDD = 5.5V VOH = 12V 50 µA 22 45 mA 35 100 µA 1.1 8 mA 9 30 µA 10 µA 20 pF 1/2 frequency dividing clock operation IDD1 VDD = 5.5V, 16MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3V, 32kHz crystal oscillation and termination of 16MHz crystal oscillation (C1 = C2 = 47pF) IDDS1 Supply current∗2 Sleep mode IDD2 IDDS2 IDDS3 Input capacity CIN VDD VDD = 5.5V, 16MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3V, 32kHz crystal oscillation, termination of 16MHz crystal oscillation (C1 = C2 = 47pF) Stop mode VDD = 5.5V, termination of 16MHz and 32kHz crystal oscillation Other than Clock 1MHz VDD, Vss, AVDD, 0V for no-measured pins and AVss 10 ∗1 RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current when non-resistor is selected. ∗2 When entire output pins are open. – 14 – CXP81720B/81724B AC Characteristics (1) Clock timing (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Item Symbol System clock frequency fC Event count input clock rise and fall times tXL, tXH tCR, tCF tEH, tEL tER, tEF System clock frequency fC Event count input clock pulse width tTL, tTH tTR, tTF System clock input pulse width System clock input rise and fall times Event count input clock pulse width Event count input clock rise and fall times Pins Conditions Min. XTAL EXTAL Fig. 1, Fig. 2 1 EXTAL Fig. 1, Fig. 2 External clock drive 28 EXTAL Fig. 1, Fig. 2 External clock drive EC Fig. 3 EC Fig. 3 TEX TX Fig. 2 VDD = 2.7 to 5.5V (32kHz clock applied condition) TEX Fig. 3 TEX Fig. 3 Max. Unit 16 MHz ns 200 4tsys∗1 ns ns 20 ns 32.768 kHz 10 µs 20 ms ∗1 tsys indicates three values according to the contents of the clock control register (CLC: 00FEh) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Fig. 1. Clock timing 1/fc VDD – 0.4V EXTAL 0.4V tCF tXH tXL tCR Fig. 2. Clock applied condition AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA Crystal oscillation Ceramic oscillation EXTAL External clock EXTAL XTAL C1 C2 32kHz clock applied condition crystal oscillation TEX XTAL 74HC04 TX C2 C1 Fig. 3. Event count clock timing 0.8VDD TEX EC 0.2VDD tEH tEF tEL tER tTH tTF tTL tTR – 15 – CXP81720B/81724B (2) Serial transfer (CH0) Item (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Symbol Pin Condition Min. Max. Unit CS0 ↓ → SCK0 delay time tDCSK SCK0 Chip select transfer mode (SCK0 = output mode) tsys + 200 ns CS0 ↑ → SCK0 float delay time tDCSKF SCK0 Chip select transfer mode (SCK0 = output mode) tsys + 200 ns CS0 ↓ → SO0 delay time tDCSO SO0 Chip select transfer mode tsys + 200 ns CS0 ↑ → SO0 float delay time tDCSOF SO0 Chip select transfer mode tsys + 200 ns CS0 High level width tWHCS CS0 Chip select transfer mode tsys + 200 ns SCK0 cycle time Input mode SCK0 2tsys + 200 ns tKCY 16000/fc ns SCK0 High and Low level widths tKH tKL tsys + 100 ns SCK0 8000/fc – 50 ns SI0 input setup time (for SCK0 ↑) SCK0 input mode 100 ns tSIK SI0 SCK0 output mode 200 ns SI0 input hold time (for SCK0 ↑) SI0 tsys + 200 ns tKSI 100 ns SCK0 ↓ → SO0 delay time tKSO SO0 Output mode Input mode Output mode SCK0 input mode SCK0 output mode SCK0 input mode SCK0 output mode tsys + 200 ns 100 ns Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 00FEh) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) The load of SCK0 output mode and SO0 output delay time is 50pF + 1TTL. – 16 – CXP81720B/81724B Fig. 4. Serial transfer CH0 timing tWHCS CS0 0.8VDD 0.2VDD tKCY tDCSK tKL tDCSKF tKH 0.8VDD 0.8VDD SCK0 0.2VDD tSIK tKSI 0.8VDD Input data SI0 0.2VDD tDCSO tKSO tDCSOF 0.8VDD SO0 Output data 0.2VDD – 17 – CXP81720B/81724B Serial transfer (CH1) Item (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Symbol Pins Conditions Min. Input mode SCK1 cycle time tKCY SCK1 SCK1 High and Low level widths tKH tKL SCK1 SI1 input setup time (for SCK1 ↑) tSIK SI1 SI1 input hold time (for SCK1 ↑) tKSI SI1 SCK1 ↓ → SO1 delay time tKSO SO1 Unit 1000 ns 16000/fc ns 400 ns 8000/fc – 50 ns SCK1 input mode 100 ns SCK1 output mode 200 ns SCK1 input mode 200 ns SCK1 output mode 100 ns Output mode Input mode Output mode SCK1 input mode 200 ns SCK1 output mode 100 ns Note) The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL. Fig. 5. Serial transfer CH1 timing tKCY tKL tKH SCK1 0.8VDD 0.2VDD tSIK tKSI 0.8VDD Input data SI1 Max. 0.2VDD tKSO 0.8VDD Output data SO1 0.2VDD – 18 – CXP81720B/81724B (3) A/D converter characteristics Item (Ta = –20 to +75°C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V) Symbol Pins Conditions Min. Typ. Resolution Ta = 25°C VDD = AVDD = AVREF = 5.0V VSS = AVSS = 0V Linearity error Absolute error Conversion time Sampling time tCONV tSAMP Reference input voltage VREF AVREF Analog input voltage AN0 to AN11 VIAN IREF AVREF current IREFS Unit 8 Bits ±1 LSB ±2 LSB 160/fADC∗1 µs 12/fADC∗1 µs AVDD AVDD – 0.5 Sleep mode Stop mode 32kHz operating mode 0.6 1.0 mA 10 µA Fig. 6. Definitions of A/D converter terms Digital conversion value FFh FEh Linearity error ∗1 The value of fADC is as follows by selecting ADC operation clock (MSC: Address 01FFh bit 0). When PS2 is selected, fADC = fc/2 When PS1 is selected, fADC = fc 01h 00h Analog input – 19 – V V 0 Operating mode AVREF Max. CXP81720B/81724B (4) Interruption, reset input Item (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Symbol Pin Condition External interruption High and Low level widths tIH tIL INT0 INT1 INT2 NMI PJ0 to PJ7 Reset input low level width tRSL Min. Max. Unit 1 µs RST 32/fc µs tIH tIL Fig. 7. Interruption input timing INT0 INT1 INT2 NMI PJ0 to PJ7 (During standby release input) (Falling edge) 0.8VDD 0.2VDD Fig. 8. Reset input timing tRSL RST 0.2VDD (5) Others Item EXI input High and Low level widths Note) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Symbol tEIH tEIL Pin EXI0 EXI1 Min. Condition tsys = 2000/fc Max. tsys + 200 Unit ns tsys indicates three values according to the contents of the clock control register (CLC: 00FEh) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") tFRC [ns] = 1000/fc Fig. 9. Other timings tEIH EXI0 EXI1 tEIL 0.8VDD 0.2VDD – 20 – CXP81720B/81724B Appendix Fig. 10. Recommended oscillation circuit AAAAA AAAAA AAAAA (i) EXTAL (ii) XTAL TEX Rd C1 Model C2 C1 fc (MHz) C1 (pF) C2 (pF) 10 10 8.00 RIVER ELETEC CO., LTD. HC-49/U03 10.00 12.00 5 5 8.00 16 12 10.00 16 12 12.00 12 12 16.00 12 12 32.768kHz 30 18 16.00 HC-49/U (-S) KINSEKI LTD. P3 TX Rd C2 Manufacturer AAAA AAAA AAAA Models with an asterisk (∗) have the built-in ground capacitance (C1, C2). Mask option table Item Reset pin pull-up resistor Input circuit format∗1 Content Non-existent Existent CMOS Schmitt TTL Schmitt ∗1 The input circuit format can be selected each for PG4 pin and PG5 pin. – 21 – Rd (Ω) Circuit example 0 (i) 0 (i) 470k (ii) CXP81720B/81724B Characteristics Curve IDD vs. VDD IDD vs. fc (fc = 16MHz, Ta = 25°C, Typical) (VDD = 5V, Ta = 25°C, Typical) 1/4 dividing mode 10.0 20 Sleep mode 1.0 0.5 32kHz mode (instruction) 32kHz Sleep mode 0.1 (100µA) 0.05 (50µA) IDD – Supply current [mA] 1/16 dividing mode 5.0 IDD – Supply current [mA] 1/2 dividing mode 1/2 dividing mode 20.0 15 1/4 dividing mode 10 5 1/16 dividing mode 0.01 (10µA) Sleep mode 2 3 4 5 6 7 0 VDD – Supply voltage [V] – 22 – 10 5 fc – System clock [MHz] 16 CXP81720B/81724B Unit: mm 100PIN QFP (PLASTIC) + 0.4 14.0 – 0.01 17.9 ± 0.4 15.8 ± 0.4 + 0.1 0.15 – 0.05 23.9 ± 0.4 + 0.4 20.0 – 0.1 A 0.65 + 0.35 2.75 – 0.15 ±0.12 M 0° to 15° DETAIL A 0.8 ± 0.2 (16.3) 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING SONY CODE QFP-100P-L01 LEAD TREATMENT EIAJ CODE ∗QFP100-P-1420-A LEAD MATERIAL COPPER / 42 ALLOY PACKAGE WEIGHT 1.4g JEDEC CODE 100PIN LQFP (PLASTIC) 16.0 ± 0.2 ∗ 14.0 ± 0.1 75 51 76 (15.0) 50 0.5 ± 0.2 A 26 (0.22) 100 1 0.5 ± 0.08 + 0.08 0.18 – 0.03 25 + 0.2 1.5 – 0.1 + 0.05 0.127 – 0.02 0.1 0.1 ± 0.1 0° to 10° 0.5 ± 0.2 Package Outline DETAIL A NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY/PHENOL RESIN SONY CODE LQFP-100P-L01 LEAD TREATMENT SOLDER PLATING EIAJ CODE ∗QFP100-P-1414-A LEAD MATERIAL 42 ALLOY JEDEC CODE PACKAGE WEIGHT – 23 –