CXP826P16
CMOS 8-bit Single Chip Microcomputer
Description
The CXP826P16 microcomputer is composed of a
CPU, ROM, RAM, and I/O ports. These chips feature
many other high-performance circuits in a single-chip
CMOS design, including an A/D converter, serial
interface, timer/counter, time-base timer, fluorescent
display controller/driver, remote control receiver and
32kHz timer/counter.
This device also includes a power-on reset function
and sleep/stop functions which can be used to
achieve low power consumption.
The CXP826P16 is the PROM-incorporated version of
the CXP82616 with built-in mask ROM, and it is able to
write directly into the program. Thus, it is most suitable
for evaluation use during system development and for
small-quantity production.
80 pin QFP (Plastic)
Features
• Instruction set which supports a wide array of data types
— 213 types of instructions which include 16-bit calculations, multiplication and division arithmetic, and
boolean bit operations.
• Minimum instruction cycle
400ns for 10MHz, 122µs for 32kHz operation
• On-chip PROM
16K bytes
• On-chip RAM
448 bytes (Including fluorescent display data area)
• Peripheral functions
— A/D converter
8-bit, 8-channel, successive approximation system
(conversion rate 32µs/10MHz)
— Serial interface
On-chip 8-bit, 8-stage FIFO (1 to 8 bytes auto transfer),
1 circuit 2-channel
— Timers
8-bit timer
8-bit timer/counter
19-bit time base timer
32kHz timer/counter
— Fluorescent display controller/driver
Maximum of 336 segments display available
1 to 16 digits dynamic display
Dimmer function
High voltage tolerance output (40V)
On-chip pull-down resistor (Mask option)
Hardware key scan function (Maximum of 8 x 16 key matrix available)
— Remote control receiver circuit
On-chip 6-stage FIFO 8-bit pulse measurement counter
• Interrupts
13 factors, 13 vectors, multi-interruption possible
• Standby mode
Sleep/stop
• Package
80-pin plastic QFP
Structure
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E94413A79-PS
PE7/ADJ
PE7/TO
PE0/EC
FIFO
FIFO
RAM
80 BYTES
8 BIT TIMER 1
8 BIT TIMER/COUNTER 0
SERIAL
INTERFACE
UNIT
PB1/CS0
PB3/SI0
PB4/SO0
PB2/SCK0
PB0/CS1
PB6/SI1
PB7/SO1
PB5/SCK1
FDP
CONTROLLER/
DRIVER
A/D CONVERTER
REMOCON
21
8
8
8
PE4/RMC
T0 to T7
T8/S28
to
T15/S21
S0 to S20
VFDP
PA0/AN0
to
PA7/AN7
2
2
PE0/INT0
PE1/INT1
PE2/INT2
PE3/INT3
PE3/NMI
2
PRESCALER/
TIME BASE TIMER
PROM
16K BYTES
SPC700
CPU CORE
PH2/TEX
PH3/TX
EXTAL
XTAL
RST
VDD
Vpp
Vss
32kHz
TIMER/COUNTER
RAM
448 BYTES
CLOCK GEN./
SYSTEM CONTROL
PD0 to PD7
PE0 to PE5
PE6 to PE7
8
8
6
2
PH0 to PH1
PH2 to PH3
2
PF0 to PF7
2
8
PB0 to PB7
8
PC0 to PC7
PA0 to PA7
8
PORT A
PORT B
PORT C
PORT D
PORT E
PORT F
–2–
PORT H
INTERRUPT CONTROLLER
Block Diagram
CXP826P16
CXP826P16
T5
T4
T3
T2
T1
T0
VFDP
VDD
PH3/TX
PH2/TEX
Vpp
PH1
PH0
PE0/EC/INT0
PE1/INT1
PE2/INT2
Pin Assignment (Top View)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
PE3/INT3/NMI
1
64
T6
PE4/RMC
2
63
T7
PE5
3
62
T8/S28
PE6
4
61
T9/S27
PE7/TO/ADJ
5
60
T10/S26
PB0/CS1
6
59
T11/S25
PB1/CS0
T12/S24
7
58
PB2/SCK0
8
57
T13/S23
PB3/SI0
9
56
T14/S22
PB4/SO0
10
55
T15/S21
PB5/SCK1
11
54
S20
PB6/SI1
12
53
S19
PB7/SO1
13
52
S18
PC0/KR0
14
51
S17
PC1/KR1
S16
15
50
PC2/KR2
16
49
PF7/S15
PC3/KR3
17
48
PF6/S14
PC4/KR4
18
47
PF5/S13
PC5/KR5
19
46
PF4/S12
PC6/KR6
20
45
PF3/S11
PC7/KR7
21
44
PF2/S10
PA0/AN0
22
43
PF1/S9
PA1/AN1
23
42
PF0/S8
PA2/AN2
24
41
PD7/S7
Note) 1. Vpp (Pin 75) is always connected to VDD.
2. PH3/TX (Pin 73) is input port during port selection;
oscillation output during oscillation selection
–3–
PD6/S6
PD5/S5
PD4/S4
PD3/S3
PD2/S2
PD1/S1
PD0/S0
Vss
XTAL
EXTAL
RST
PA7/AN7
PA6/AN6
PA5/AN5
PA4/AN4
PA3/AN3
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
CXP826P16
Pin Description
Symbol
I/O
PA0/AN0
to
PA7/AN7
I/O/Analog input
PB0/CS1
I/O/Input
PB1/CS0
I/O/Input
PB2/SCK0
I/O/I/O
PB3/SI0
I/O/Input
PB4/SO0
I/O/Output
PB5/SCK1
I/O/I/O
PB6/SI1
I/O/Input
PB7/SO1
I/O/Output
PC0/KR0
to
PC7/KR7
I/O/Input
PE0/INT0/
EC0
Input/Input/
Input
PE1/INT1
Input/Input
PE2/INT2
Input/Input
PE3/INT3/
NMI
Input/Input/
Input
PE4/RMC
Input/Input
PE5
Input
PE6
Input
PE7/TO/
ADJ
Output/Output
Functions
(Port A)
8-bit I/O port. I/O can
be set in a bit unit.
Incorporation of pull-up
resistor can be set
through the software in
a unit of 4 bits.
(8 pins)
Analog inputs to A/D converter.
(8 pins)
Chip select input for serial interface (CH1).
(Port B)
8-bit I/O port. I/O can
be set in a bit unit.
Incorporation of pull-up
resistor can be set
through the software in
a unit of 4 bits.
(8 pins)
Chip select input for serial interface (CH0).
Serial clock I/O (CH0).
Serial data input (CH0).
Serial data output (CH0).
Serial clock I/O (CH1).
Serial data input (CH1).
Serial data output (CH1).
(Port C)
8-bit I/O port. I/O can
be set in a bit unit.
Capable of driving
12mA sync current.
Incorporation of pull-up
resistor can be set
through the software in
a unit of 4 bits.
(8 pins)
(Port E)
8-bit port.
Upper 6 bits are for
inputs; lower 2 bits are
for outputs.
(8 pins)
Key return input for FDP segment signal which
performs key scanning.
External interrupt
request inputs.
(4 pins)
External event input to
timer/counter. (1 pin)
Non-maskable interruption request input.
Input for remote control receiver circuit.
Output for timer/counter rectangular waveform
and 32kHz oscillation frequency division.
–4–
CXP826P16
Symbol
I/O
Functions
PH0 to PH1
I/O
(Port H)
2-bit I/O port. I/O can be set in a bit unit. Incorporation of pull-up resistor
can be set through the software in a unit of 2 bits.
(2 pins)
PF0/S8
to
PF7/S15
Output/Output
(Port F)
8-bit output port.
(8 pins)
S16 to S20
Output
Segment signal output for FDP.
T8/S28
to
T15/S21
Output/Output
Output for FDP timing and segment signals.
T0 to T7
Output
Timing signal output for FDP.
PD0/S0
to
PD7/S7
Output/Output
(Port D)
8-bit output port.
(8 pins)
Segment signal output for FDP.
Segment signal output for FDP.
Provides voltage for FDP when on-chip resistor is selected under mask option.
VFDP
EXTAL
Input
XTAL
Output
PH2/TEX
Input/Input
PH3/TX
Input/Output
RST
Input
Crystal connectors for system clock oscillation. When the clock is
supplied externally, input to EXTAL; opposite phase clock should be
input to XTAL.
(Port H)
2-bit input
port.
(2 pins)
Crystal connectors for 32kHz timer/counter clock
oscillation circuit. Connect a 32kHz crystal oscillator
between TEX and TX. For usage as event input, connect
clock oscillation source to TEX, and leave TX open.
Low-level active. System reset. RST is input pin.
Vpp
Positive power supply pin for writing of built-in PROM.
Under normal operating conditions, connect to VDD.
VDD
Vcc supply.
Vss
GND
–5–
CXP826P16
I/O Circuit Format for Pins
Pin
When reset
Circuit format
AAAA
AAAA
AAAA
AAAA
Port A
∗
Pull-up resistor
"0" when reset
AA
AA
AA
Port A data
PA0/AN0
to
PA7/AN7
Port A direction
Input protection
circuit
IP
"0" when reset
Data bus
AAAA
Hi-Z
RD (Port A)
Port A input
selection
"0" when reset
Input multiplexer
A/D converter
∗ Pull-up transistors
approx. 100kΩ
8 pins
Port B
AAAA
AAAA
AAAA
AAAA
∗
Pull-up resistor
"0" when reset
AA
AA
AA
Port B data
PB0/CS1
PB1/CS0
PB3/SI0
PB6/SI1
Port B direction
IP
"0" when reset
Schmitt input
Data bus
RD (Port B)
4 pins
CS0
CS1
SI0
SI1
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
∗ Pull-up transistors
approx. 100kΩ
SI0 and SI1 are not schmitt input.
Port B
∗
Pull-up resistor
"0" when reset
SCK OUT
Output enable
AA
AA
AA
Port B output
selection
"0" when reset
PB2/SCK0
PB5/SCK1
IP
Port B data
Port B direction
"0" when reset
Data bus
Schmitt input
RD (Port B)
2 pins
Hi-Z
SCK in
–6–
∗ Pull-up transistors
approx. 100kΩ
Hi-Z
CXP826P16
Pin
Port B
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
When reset
Circuit format
∗
Pull-up resistor
"0" when reset
SO
Output enable
AA
AA
AA
Port B output
selection
PB4/SO0
PB7/SO1
"0" when reset
IP
Port B data
Port B direction
Hi-Z
"0" when reset
Data bus
RD (Port B)
2 pins
Port C
∗ Pull-up transistors
approx. 100kΩ
AAA
AAA
AAA
AAA
AAA
∗2
Pull-up resistor
"0" when reset
AA
AA
AA
Port C data
PC0/KR0
to
PC7/KR7
∗1
Port C direction
"0" when reset
Data bus
IP
Hi-Z
RD (Port C)
Key input signal
8 pins
PE0/EC/INT0
PE1/INT1
PE2/INT2
PE3/INT3/NMI
PE4/RMC
5 pins
PE5
∗1 Large current drive of 12mA possible
∗2 Pull-up transistors approx. 100kΩ
Port E
AA
A
AA
AA
A
AA
AAAA
AAAA
EC/INT0
INT1
INT2
INT3/NMI
RMC
Schmitt input
IP
Data bus
RD (Port E)
Port E
Data bus
IP
1 pin
Port E
PE6
Port E data
"1" when reset
Data bus
1 pin
Hi-Z
RD (Port E)
–7–
RD (Port E)
AA
AA
Hi-Z
*
High level
CXP826P16
Pin
When reset
Circuit format
Port E
PE7/TO/ADJ
AA
AAA
AA
AAA
AAA
AAA
AAA
Output enable
TO
ADJ16K
ADJ2K
Port E output
selection
Port E output
selection
"00" when reset
MPX
High level
High level with
150kΩ resistor
when reset
AA (
Port E output
selection
"0" when reset
Port E data
1 pin
"1" when reset
Data bus
RD (Port E)
AAAA
AAAA
AAAA
AAAA
AAAA
Port H
)
∗ ADJ signals are frequency division
outputs for 32kHz oscillation frequency
adjustment. ADJ2K provides usage as
buzzer output.
∗
Pull-up resistor
"0" when reset
AA
AA
AA
Port data
PH0 to PH1
Port direction
Hi-Z
IP
"0" when reset
Data bus
RD
∗ Pull-up transistors
approx. 100kΩ
2 pins
Port D
Port F
PD0/S0
to
PD7/S7
PF0/S8
to
PF7/S15
∗ High voltage tolerance transistor
Segment output data
AAAA
AAAA
∗
Output selection control signal
("0" when reset)
A
A
A
Hi-Z or
Low level
(When PD
resistor is
connected)
OP Mask option
Port D data or
Port F data
Pull-down
resistor
Data bus
RD (Port D or Port F)
16 pins
–8–
VFDP
CXP826P16
Pin
When reset
Circuit format
∗ High voltage tolerance transistor
S16 to S20
T15/S21
to
T8/S28
T0 to T7
Segment output data
∗
Output selection control signal
("0" when reset)
OP Mask option
Pull-down
resistor
21 pins
EXTAL
XTAL
2 pins
AA
AA
AA
AA
Hi-Z or
Low level
(When PD
resistor is
connected)
VFDP
AA
AA
AA
AA
EXTAL
A
AA
A AA
IP
IP
• Diagram shows circuit
construction for oscillation.
• During STOP feedback
resistor is disconnected,
and XTAL becomes "H"
level.
Oscillation
XTAL
32kHz oscillation
circuit control
"1" when reset
Data
bus
PH2/TEX
PH3/TX
AA
AA
AA AA
AA
AA
PH2/TEX
2 pins
RST
A
A
IP
IP
Data
bus
RD
Clock
input
Oscillation
halted
port input
PH3/TX
Pull-up resistor
AA
AA
AA
OP Mask option
1 pin
RD
Low level
IP
–9–
Schmitt input
CXP826P16
Absolute Maximum Ratings
Item
Supply voltage
(Vss = 0V)
Symbol
Rating
Unit
VDD
–0.3 to +7.0
V
Vpp
V
Remarks
Input voltage
VIN
–0.3 to +13.0
–0.3 to +7.0∗1
Output voltage
VOUT
–0.3 to +7.0∗1
V
Display output voltage
VOD
VDD – 40 to VDD + 0.3
V
As P channel transistor is open drain,
VDD voltage is determined as standard.
IOH
–5
mA
Other than display output pins∗2: per pin
IODH1
–15
mA
Display output S0 to S20: per pin
IODH2
–35
mA
Display output T0 to T7
,
T8/S28 to T15/S21: per pin
∑IOH
–40
mA
Total of other than display output pins
∑IODH
–100
mA
Total of display output pins
IOL
15
mA
Port 1 pin
IOLC
20
mA
Large current port pin∗3
Low level total output current ∑IOL
100
mA
Entire pin toral
High level output current
High level
total output current
Low level output current
Incorporated PROM
V
Operating temperature
Topr
–10 to +75
°C
Storage temperature
Tstg
–55 to +150
°C
Allowable power dissipation
PD
600
mW
∗1 VIN and VOUT must not exceed VDD + 0.3V.
∗2 Specifies output current of general-purpose I/O ports.
∗3 The large current drive transistor is an N-ch transistor of Port C (PC).
Note) If the absolute maximum ratings are exceeded, the LSI could reach permanent breakdown. Also,
observing recommended operating conditions is desirable; otherwise, the LSI's reliability could be
affected.
– 10 –
CXP826P16
Recommended Operating Conditions
Item
Supply voltage
Symbol
VDD
(Vss = 0V)
Min.
Max.
Unit
4.5
5.5
V
High speed mode (1/2, 1/4 clock)
guaranteed operation range
3.5
5.5
V
Low speed mode (1/16 clock)
guaranteed operation range
2.7
5.5
V
2.5
5.5
V
Vpp
Vpp = VDD
Remarks
Guaranteed operation range with TEX clock
V
Guaranteed data hold operation range
during STOP
∗4
VIH
0.7VDD
VDD
V
∗1
VIHS
0.8VDD
VDD
V
VIHEX
VDD – 0.4
VDD + 0.3
V
Hysteresis input∗2
EXTAL pin∗3
VIL
0
0.3VDD
V
∗1
VILS
0
0.2VDD
V
VILEX
–0.3
0.4
V
Hysteresis input∗2
EXTAL pin∗3
Operating temperature Topr
–10
+75
°C
High level
input voltage
Low level
input voltage
∗1
∗2
∗3
∗4
All regular input port (PA, PB3, PB4, PB6, PB7, PC, PE5, PH).
For pins RST, CS0, CS1, SCK0, SCK1, EC/INT0, INT1, INT2, INT3/NMI, RMC.
Specifies only for external clock input.
Vpp should be the same voltage as VDD.
– 11 –
CXP826P16
Electrical Characteristics
(Ta = –10 to +75°C, Vss = 0V)
DC Characteristics
Item
Symbol
High level
VOH
output voltage
Low level
output voltage VOL
Pin
PA, PB,
PC, PE6,
PE7, PH0,
PH1
PC
IIHE
IILE
EXTAL
IIHT
Input current
IILT
TEX
Condition
Min.
Typ.
Max.
Unit
VDD = 4.5V, IOH = –0.5mA
4.0
V
VDD = 4.5V, IOH = –1.2mA
3.5
V
VDD = 4.5V, IOL = 1.8mA
0.4
V
VDD = 4.5V, IOL = 3.6mA
0.6
V
VDD = 4.5V, IOL = 12.0mA
1.5
V
VDD = 5.5V, VIH = 5.5V
0.5
40
µA
VDD = 5.5V, VIL = 0.4V
–0.5
–40
µA
VDD = 5.5V, VIL = 5.5V
0.1
10
µA
VDD = 5.5V, VIL = 0.4V
–0.1
–10
µA
–1.5
–400
µA
–50
µA
IILR
RST∗1
IIL
PA to PC∗2
PH0∗2, PH1∗2 VDD = 4.5V, VIL = 4.0V
VDD = 5.5V, VIL = 0.4V
S0 to S20
VDD = 4.5V
VOH = VDD – 2.5V
Display
IOH
output current
S21/T15 to
S28/T8
T0 to T7
Open drain
output leak
current (P-CH
Tr off state)
ILOL
S0 to S20
S21/T15 to
S28/T8
T0 to T7
VDD = 5.5V
VOL = VDD – 35V
VFDP = VDD – 35V
Pull down
resistor∗3
RL
S0 to S20
S21/T15 to
S28/T8
T0 to T7
VDD = 5V
VOD – VFDP = 30V
Input/Output
leak current
IIZ
PA to PC∗2,
VDD = 5.5V
PH0∗2, PH1∗2,
VI = 0, 5.5V
RST∗2
– 12 –
–3.3
µA
–8
mA
–20
mA
60
100
–20
µA
270
kΩ
±10
µA
CXP826P16
Item
Symbol
Pin
Codition
Min.
Typ.
Max.
Unit
20
40
mA
400
1000
µA
1.2
8
mA
9
30
µA
30
µA
20
pF
High-speed mode operation
(1/2 frequency divider clock)
IDD1
VDD = 5.5V, 10MHz crystal oscillation
(C1 = C2 = 15pF)
VDD = 3V, 32kHz crystal oscillation
(C1 = C2 = 47pF)
IDD2
Supply
current∗4
VDD
IDDS1
VDD = 5.5V, 10MHz crystal oscillation
(C1 = C2 = 15pF)
VDD = 3V, 32kHz crystal oscillation
(C1 = C2 = 47pF)
IDDS2
Stop mode, VDD = 5.5V,
Termination of 10MHz and 32kHz
crystal oscillation.
IDDS3
Input
capacitance
CIN
Sleep mode
For pins
other than
S0 to S28,
T0 to T7,
PE6, PE7,
VDD, Vss,
VFDP
1MHz clock
0V other than the measured pins
10
∗1 RST specifies the input current when pull-up resistor has been selected; leakage current when no resistor
has been selected.
∗2 Pins PA to PC, PH0, and PH1 specifies the input current when pull-up resistor has been selected; leakage
current when no resistor has been selected.
∗3 Applies when the on-chip pull-down resistor is selected under the mask option.
∗4 All output pins are left open.
– 13 –
CXP826P16
AC Characteristics
(1) Clock timing
(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Item
Symbol
System clock frequency
fC
Event count input clock
rise and fall time
tXL,
tXH
tCR,
tCF
tEH,
tEL
tER,
tEF
System clock frequency
fC
Event count input clock
input pulse width
tTL,
tTH
tTR,
tTF
System clock input pulse width
System clock input
rise and fall time
Event count input clock
pulse width
Event count input clock
rise and fall time
Pins
Conditions
XTAL
EXTAL
Fig. 1, Fig. 2
EXTAL
Fig. 1, Fig. 2
External clock drive
EXTAL
Fig. 1, Fig. 2
External clock drive
EC
Fig. 3
EC
Fig. 3
TEX
TX
VDD = 2.7 to 5.5V
Fig. 2 (32kHz clock
application condition)
TEX
Fig. 3
TEX
Fig. 3
Min.
Typ.
1
Max.
Unit
10
MHz
ns
37.5
200
tsys + 50∗
ns
ns
20
ms
kHz
32.768
µs
10
20
ms
∗ tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock
control registor (address: 00FEH).
tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")
Fig. 1. Clock timing
1/fc
VDD – 0.4V
EXTAL
0.4V
tXH
tCF
tXL
tCR
Fig. 2. Clock applied conditions
AAAAAAAAAAAA
AAAAAAAAAAAA
Crystal oscillation
Ceramic oscillation
EXTAL
External clock
EXTAL
XTAL
C1
C2
32kHz clock applied condition
Crystal oscillation
TEX
XTAL
74HC04
TX
C2
C1
Fig. 3. Event count clock timing
0.8VDD
TEX
EC
0.2VDD
tEH
tTH
tEF
tTF
– 14 –
tEL
tTL
tER
tTR
CXP826P16
(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
(2) Serial transfer
Item
Symbol
Pin
Condition
Min.
Max.
Unit
CS0 ↓ → SCK0 (CS1 ↓ → SCK1)
delay time
tDCSK SCK0 Chip select transfer mode
tsys + 200 ns
CS0 ↑ → SCK0 (CS1 ↑ → SCK1)
float delay time
tDCSKF SCK0 Chip select transfer mode
tsys + 200 ns
CS0 ↓ → SO0 (CS1 ↓ → SO1)
delay time
tDCSO SO0
Chip select transfer mode
tsys + 200 ns
CS0 ↑ → SO0 (CS1 ↑ → SO1)
float delay time
tDCSOF SO0
Chip select transfer mode
tsys + 200 ns
CS0 (CS1) high level width
tWHCS CS0
Chip select transfer mode
SCK0 (SCK1) cycle time
tKCY
SCK0 (SCK1)
high and low level widths
(SCK1) (SCK0 (SCK1) = output mode)
(SCK1) (SCK0 (SCK1) = output mode)
(SO1)
(SO1)
tsys + 200
ns
SCK0 Input mode
(SCK1) Output mode
2tsys + 200
ns
16000/fc
ns
tKH
tKL
SCK0 Input mode
(SCK1) Output mode
tsys + 100
ns
8000/fc – 50
ns
SI0 (SI1) input setup time
(for SCK0 ↑ (SCK1 ↑) )
SI0
(SI1)
SCK0 (SCK1) input mode
100
ns
tSIK
SCK0 (SCK1) output mode
200
ns
SI0 (SI1) input hold time
(for SCK0 ↑ (SCK1 ↑) )
SI0
(SI1)
SCK0 (SCK1) input mode
tsys + 200
ns
tKSI
100
ns
SCK0 ↓ → SO0 (SCK1 ↓ → SO1)
delay time
tKSO
SO0
(SO1)
SCK0 (SCK1) input mode
(CS1)
SCK0 (SCK1) output mode
SCK0 (SCK1) output mode
tsys + 200
ns
100
ns
Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selection) of the
control clock registor (address: 00FEH).
tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits =
"11")
Note 2) The load condition for the SCK0 (SCK1) output mode, SO0 (SO1) output delay time is 50pF + 1TTL.
– 15 –
CXP826P16
Fig. 4. Serial transfer CH0 timing
tWHCS
CS0
(CS1)
0.8VDD
0.2VDD
tKCY
tDCSK
tKL
tDCSKF
tKH
0.8VDD
0.8VDD
SCK0
(SCK1)
0.2VDD
tSIK
tKSI
0.8VDD
Input
data
SI0
(SI1)
0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD
SO0
(SO1)
Output data
0.2VDD
– 16 –
CXP826P16
(3) A/D converter characteristics
Item
Symbol
(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Max.
Unit
Resolution
8
Bits
Linearity error
±3
LSB
Zero transition
voltage
VZT∗1
Full-scale transition
voltage
VFT∗2
Conversion time
tCONV
tSAMP
Sampling time
Analog input voltage VIAN
Pin
Condition
Ta = 25°C
VDD = 5.0V
VSS = 0V
Min.
Typ.
–10
10
70
mV
4910
4970
5030
mV
160/fADC∗3
12/fADC∗3
–0.3
AN0 to AN7
µs
µs
VDD + 0.3
Fig. 5. Definition of A/D converter terms
Digital conversion value
FFH
FEH
∗1 VZT : Value at which the digital conversion value changes
from 00H to 01H and vice versa.
∗2 VFT : Value at which the digital conversion value changes
from FEH to FFH and vice versa.
∗3 fADC indicates the below values due to the Bit6 (CKS) of
A/D control register (address: 00F9H) and the Bit7 (PCK1)
and Bit6 (PCK0) of clock control register (address: 00FEH)
Linearity error
01H
00H
CKS
VZT
VFT
Analog input
0 (φ /2 selection)
1 (φ selection)
00 (φ = fEX/2)
fADC = fC/2
fADC = fC
01 (φ = fEX/4)
fADC = fC/4
fADC = fC/2
11 (φ = fEX/16)
fADC = fC/16
fADC = fC/8
PCK1, 0
– 17 –
V
CXP826P16
(4) Interruption, reset input
Item
(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Symbol
Pin
External interruption
high and low level widths
tIH
tIL
INT0
INT1
INT2
INT3
NMI
Reset input low level width
tRSL
RST
Condition
Min.
Max.
Unit
1
µs
32/fc
µs
Fig 6. Interruption input timing
tIH
tIL
0.8VDD
INT0
INT1
INT2
INT3
NMI
(NMI specifies only for
the falling edge)
0.2VDD
tIL
tIH
Fig. 7. RST input timing
tRSL
RST
0.2VDD
– 18 –
CXP826P16
Appendix
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
Fig. 8. Recommended oscillation circuit
(i) Main clock
EXTAL
(ii) Main clock
EXTAL
XTAL
Rd
EXTAL
TEX
XTAL
Rd
C2
C1
(iii) Sub clock
XTAL
TX
Rd
C2
C1
C1 C2
Model
Manufacturer
MURATA
MFG
CO., LTD.
fc (MHz)
CSA4.19MG
4.19
CSA8.00MTZ
8.00
CSA10.0MTZ
10.00
CST4.19MGW∗
CST8.00MTW∗
CST10.0MTW∗
RIVER
HC-49/U03
ELETEC
CORPORATION
HC-49/U (-S)
P3
C2 (pF)
Rd (Ω)
Circuit
example
(i)
30
30
0
4.19
(ii)
8.00
10.00
4.19
12
8.00
12
0
10.00
(i)
4.19
KINSEKI
LTD.
C1 (pF)
27
27
10.00
20
20
32.768kHz
50
22
8.00
0
1M
(iii)
Those marked with an asterisk (∗) signify types with built-in ground capacitance (C1, C2).
Selection Guide
Option Item
Package
Mask Product
CXP826P16Q-1-
80-pin plastic QFP
80-pin plastic QFP
12Kbyte/16Kbyte
PROM 16Kbyte
Reset pin pull-up resistor
Existent/Non-Existent
Existent
High voltage drive output pin
pull-down resistor
Existent/Non-Existent
Non-Existent (PD0/S0 to PF7/S15)
Existent (T0 to S16)
ROM capacitance
– 19 –
CXP826P16
Charactreistics Curves
IDD vs. VDD
IDD vs. fc
(fc = 10MHz, Ta = 25°C, Typical)
(VDD = 5V, Ta = 25°C, Typical)
20.0
1/2 dividing mode
10.0
20
1/16 dividing mode
32kHz mode
(instruction)
Sleep mode
1.0
0.5
0.1
(100µA)
0.05
(50µA)
IDD – Supply current [mA]
IDD – Supply current [mA]
5.0
15
1/2 dividing mode
10
32kHz
Sleep mode
5
1/16 dividing mode
0.01
(10µA)
sleep mode
2
3
4
5
6
0
7
0
VDD – Supply voltage [V]
– 20 –
5
10
fc – System clock [MHz]
15
CXP826P16
Package Outline
Unit : mm
80PIN QFP (PLASTIC)
23.9 ± 0.4
+ 0.1
0.15 – 0.05
+ 0.4
20.0 – 0.1
64
0.15
41
65
16.3
17.9 ± 0.4
+ 0.4
14.0 – 0.1
40
A
+ 0.2
0.1 – 0.05
25
1
24
0.8
0.2
M
+ 0.15
0.35 – 0.1
+ 0.35
2.75 – 0.15
0° to 10°
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP-80P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
QFP080-P-1420
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
1.6g
JEDEC CODE
– 21 –
0.8 ± 0.2
80