CXP84632/84640/84648 CMOS 8-bit Single Chip Microcomputer Description The CXP84632/84640/84648 is a CMOS 8-bit single chip microcomputer integrating on a single chip an A/D converter, serial interface, timer/counter, time base timer, capture timer/counter, I2C bus interface, remote control reception circuit, PWM output, and 32kHz timer/counter besides the basic configurations of 8-bit CPU, ROM, RAM, and I/O port. The CXP84632/84640/84648 also provides a sleep/ stop function that enables lower power consumption. 80 pin QFP (Plastic) Structure Silicon gate CMOS IC Features • Wide range instruction system (213 instructions) to cover various of data. — 16-bit arithmetic/multiplication and division/Boolean bit operation instructions • Minimum instruction cycle 250ns at 16MHz operation (4.5 to 5.5V) 333ns at 12MHz operation (3.0 to 5.5V) 122µs at 32kHz operation (2.7 to 5.5V) • Incorporated ROM capacity 32K bytes (CXP84632) 40K bytes (CXP84640) 48K bytes (CXP84648) • Incorporated RAM capacity 2048 bytes • Peripheral functions — A/D converter 8 bits, 8 channels, successive approximation method (Conversion time 20µs/16MHz) — Serial interface Srart-stop synchronization (UART), 1 channel Incorporated buffer RAM (Auto transfer for 1 to 32 bytes), 1 channel Incorporated 8-bit, 10-stage FIFO (Auto transfer for 1 to 10 bytes), 1 channel 8-bit clock syncronization (MSB/LSB first selectable), 1 channel — Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer, 16-bit capture timer/counter, 32kHz timer/counter 2 — I C bus interface — Remote control reception circuit 8-bit pulse measurement counter, 6-stage FIFO — PWM output circuit 12 bits, 2 channels • Interruption 21 factors, 15 vectors, multi-interruption possible • Standby mode SLEEP/STOP • Package 80-pin plastic QFP • Piggyback/evaluation chip CXP84600 80-pin ceramic QFP Perchase of Sony's I2C components conveys a licence under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E96309-ST –2– I2C BUS INTERFACE UNIT SCL0 SCL1 SDA0 SDA1 ADJ 16 BIT CAPTURE TIMER/COUNTER 2 TO CINT EC1 8 BIT TIMER 1 8 BIT TIMER/COUNTER 0 EC0 SERIAL INTERFACE UNIT (CH1) SI1 SO1 SCK1 SERIAL INTERFACE UNIT (CH2) FIFO SERIAL INTERFACE UNIT (CH0) CS0 SI0 SO0 SCK0 SI2 SO2 SCK2 BUFFER RAM REMOCON IN FIFO 12 BIT PWM GENERATOR 1 12 BIT PWM GENERATOR 0 RMC PWM0 PWM1 UART BAUD RATE GENERATOR UART RECEIVER UART TRANSMITTER A/D CONVERTER AVSS TxD 8 AVREF RxD AN0 to AN7 2 2 NMI NMI INT0 INT1 INT2 INT3 INT4 INTERRUPT CONTROLLER Block Diagram 2 PRESCALER/ TIME BASE TIMER ROM 32K/40K/48K BYTES SPC 700 CPU CORE VSS VDD XTAL RST TX EXTAL TEX 32kHz TIMER/COUNTER RAM 2048 BYTES CLOCK GENERATOR/ SYSTEM CONTROL 8 8 8 PI0 to PI7 PH0 to PH7 PG0 to PG7 PF7 PF0 to PF6 PE4 to PE5 2 7 PE0 to PE3 PD0 to PD7 PC0 to PC7 PB0 to PB7 PA0 to PA7 4 8 8 8 8 CXP84632/84640/84648 PORT I PORT H PORT G PORT F PORT E PORT D PORT C PORT B PORT A CXP84632/84640/84648 PI5/SCK2 PI6/SI2 PI7/SO2 PG0 PG1 PG2 PG3 VDD NC PG4 PG5 PG6 PG7 PF0/SCL0 PF1/SCL1 PF2/SDA0 Pin Assignment (Top View) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 PF3/SDA0 1 64 PI4/INT4 PF4/PWM0 2 63 PI3/INT3 PF5/PWM1 3 62 PI2/INT2 PF6/TxD 4 61 PI1/INT1 PF7/RxD 5 60 PI0/INT0 PD0 6 59 PE5/TO/ADJ PD1 7 58 PE4 PD2 8 57 PE3/NMI PD3 9 56 PE2/RMC PD4 10 55 PE1/EC1 PD5 11 54 PE0/EC0 PD6 12 53 PB7/SO1 PD7 13 52 PB6/SI1 PC0 14 51 PB5/SCK1 PC1 15 50 PB4/SO0 PC2 16 49 PB3/SI0 PC3 17 48 PB2/SCK0 PC4 18 47 PB1/CS0 PC5 19 46 PB0/CINT PC6 20 45 PA7/AN7 PC7 21 44 PA6/AN6 PH0 22 43 PA5/AN5 PH1 23 42 PA4/AN4 PH2 24 41 PA3/AN3 Note) NC (Pin 73) must be connected VDD. –3– PA2/AN2 PA1/AN1 PA0/AN0 AVSS AVREF TEX TX VSS XTAL EXTAL RST PH7 PH6 PH5 PH4 PH3 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 CXP84632/84640/84648 Pin Description Pin code I/O PA0/AN0 to PA7/AN7 I/O/Analog input PB0/CINT I/O/Input PB1/CS0 I/O/Input PB2/SCK0 I/O/I/O PB3/SI0 I/O/Input PB4/SO0 I/O/Output PB5/SCK1 I/O/I/O PB6/SI1 I/O/Input PB7/SO1 I/O/Output Functions (Port A) 8-bit I/O port. I/O can be set in a unit of signle bits. Incorporation of the pullup resistance can be set through the software in a unit of 4 bits. (8 pins) Analog inputs to A/D converter. (8 pins) External capture input to 16-bit timer/counter. (Port B) I/O can be set in a unit of single bits for lower 7 bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) Chip select input for serial interface (CH0). Serial clock I/O (CH0). Serial data input (CH0). Serial data output (CH0). Serial clock I/O (CH1). Serial data input (CH1). Serial data output (CH1). I/O (Port C) 8-bit I/O port. I/O can be set in a unit of single bits. Capable of driving 12mA sync current. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) PD0 to PD7 I/O (Port D) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pullup resistor can be set through the software in a unit of 4 bits. (8 pins) PE0/EC0 Input/Input PE1/EC1 Input/Input PE2/RMC Input/Input PE3/NMI Input/Input PE4 Output PE5/TO/ ADJ Output/Output/ Output PF0/SCL0 PF1/SCL1 Output/I/O PF2/SDA0 PF3/SDA1 Output/I/O PF4/PWM0 Output/Output PF5/PWM1 Output/Output PF6/TxD Output/Output PF7/RxD Input/Input PC0 to PC7 External event inputs for timer/counter. (2 pins) (Port E) 6-bit port. Lower 4 bits are for inputs; upper 2 bits are for outputs. (6 pins) Remote control reception circuit input. Non-maskable interruption request input. Rectangular wave output for 16-bit timer/counter. Output for 32kHz oscillation frequency division. (Port F) Lower 7 bits are for output; of which lower 4 bits are large current (12mA) N-ch open drain output. The uppermost bit (PF7) is for input. (8pins) –4– Transfer clock I/O for I2C bus interface. (2pins) Transfer data I/O for I2C bus interface. (2pins) PWM outputs. (2pins) UART transmission data output. UART reception data input. CXP84632/84640/84648 Pin code I/O Functions I/O (Port G) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pullup resistor can be set through the software in a unit of 4 bits. (8 pins) PH0 to PH7 I/O (Port H) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pullup resistor can be set through the software in a unit of 4 bits. (8 pins) PI0/INT0 to PI4/INT4 I/O/Input PI5/SCK2 I/O/I/O PI6/SI2 I/O/Input PI7/SO2 I/O/Output EXTAL Input XTAL Output TEX Input TX Output Crystal connectors for 32kHz timer/counter clock oscillation. For usage as event counter, input to TEX, and open TX. RST Input Low-level active, system reset. PG0 to PG7 External interruption request inputs. (5 pins) Serial clock I/O. (CH2) Serial data input. (CH2) Serial data output. (CH2) Crystal connectors for system clock oscillation. When the clock is supplied externally, input to EXTAL; opposite phase clock should be input to XTAL. NC. Under normal operating conditions, connect to VDD. NC AVREF (Port I) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) Input Reference voltage input for A/D converter. AVss A/D converter GND. VDD Positive power supply. Vss GND. –5– CXP84632/84640/84648 I/O Circuit Format for Pins Pin When reset Circuit format AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA Port A ∗ Pull-up resistance AA AAAA “0” when reset Port A data PA0/AN0 to PA7/AN7 Port A direction IP “0” when reset Data bus Input protection circuit Hi-Z RD (Port A) Port A function selection “0” when reset 8 pins Input multiplexer A/D converter ∗ Pull-up transistors approx. 100kΩ Port B ∗ Pull-up resistance Port I AA AA AA AA “0” when reset PB0/CINT PB1/CS0 PB3/SI0 PB6/SI1 PI6/SI2 Port B, I data Port B, I direction IP “0” when reset Hi-Z Schmitt input Data bus RD (Port B, I) 5 pins CINT CS0 SI0 SI1 AAAA AAAA AAAAA AAAAA AAAA AAAA AAAA ∗ Pull-up transistors approx. 100kΩ Port B Port I ∗ Pull-up resistance A AAA “0” when reset SCK OUT Serial clock output enable Port B, I function selection PB2/SCK0 PB5/SCK1 PI5/SCK2 “0” when reset IP Port B, I data Port B, I direction “0” when reset Schmitt input Data bus RD (Port B, I) 3 pins SCK in –6– ∗ Pull-up transistors approx. 100kΩ Hi-Z CXP84632/84640/84648 Pin When reset Circuit format AAAA AAAAA AAAA AAAA AAAA Port B Port I ∗ Pull-up resistance “0” when reset SO Serial data output enable AA AAAA Port B, I function selection PB4/SO0 PB7/SO1 PI7/SO2 “0” when reset IP Port B, I data Port B, I direction Hi-Z “0” when reset Data bus RD (Port B, I) ∗ Pull-up transistors approx. 100kΩ 3 pins AAAA AAAA AAAA AAAA AAAA Port C ∗2 Pull-up resistance AA AA AA AA “0” when reset Port C data PC0 to PC7 ∗1 Port C direction “0” when reset Data bus RD (Port C) ∗1 Large current 12mA ∗2 Pull-up transistors approx. 100kΩ 8 pins PE0/EC0 PE1/EC1 PE2/RMC PE3/NMI PF7/RxD 5 pins Port E A A Port F Schmitt input IP EC0, EC1, RMC, NMI, RxD Data bus AAAA AAAA Port E data “1” when reset Data bus 1 pin Hi-Z RD (Port E, F) Port E PE4 Hi-Z IP RD (Port E) –7– AA AA High level CXP84632/84640/84648 Pin When reset Circuit format Port E AAAAA AAAAAA AAAAAA Internal reset signal PE5/TO/ADJ Port E data 00 “1” when reset TO ADJ16K∗1 01 ADJ2K∗1 11 AA AA( ) MPX ∗2 10 Port E function selection (upper) Port E function selection (lower) ∗1 ADJ signals are frequency dividing output for “00” when reset TO output enable 1 pin Port D Port G Port H Pull-up resistance “0” when reset Port D, G, H direction “0” when reset Data bus RD (Port D, G, H) 24 pins Port I AAAA AAAA AAAA AAAA AAAA Pull-up resistance “0” when reset Port I data PI0/INT0 to PI4/INT4 Port I direction “0” when reset Data bus RD (Port I) 5 pins 32kHz oscillation frequency adjustment. ADJ2K provides usage as buzzer output. ∗2 Pull-up transistor approx. 150kΩ AAAAA AAAAA AAAAA AAAAA AAAAA Port D, G, H data PD0 to PD7 PG0 to PG7 PH0 to PH7 High level with approx. 150kΩ resistor when reset INT0 INT1 INT2 INT3 INT4 –8– ∗ AA AA AA AA IP Hi-Z ∗ Pull-up transistors approx. 100kΩ ∗ AA AA AA AA IP ∗ Pull-up transistors approx. 100kΩ Hi-Z CXP84632/84640/84648 Pin Circuit format Port F SCL, SDA PF0/SCL0 PF1/SCL1 PF2/SDA0 PF3/SDA1 AAA AAA AA AA I2C output enable (“0” when reset) Port F data ∗ AA AA IP “1” when reset When reset Hi-Z Schmitt input SCL, SDA (To I2C circuit) BUS SW To internal I2C pin (SCL1 for SCL0) ∗ Large current 12mA 4 pins Port F AAAAA AAAAA AAAAA AA AA PWM Port F output selection PF4/PWM0 PF5/PWM1 “0” when reset Port F data High level “1” when reset Data bus 2 pins RD (Port F) Port F AAAAA AAAAA AAAAA AAAA AAAA AAAA AA AA UART transmission circuit Port F output selection PF6/TxD “0” when reset Port F data “1” when reset 1 pin Data bus RD (Port F) Port H Port H data “0” when reset Port H direction PH0 to PH7 Data bus RD (Port H) Edge detection Standby release Data bus 8 pins RD (Port H direction) –9– AA AA AA AA AA AA High level IP Hi-Z CXP84632/84640/84648 Pin AA AA A AA AA AA A AA EXTAL XTAL EXTAL 2 pins XTAL TEX TX 2 pins When reset Circuit format IP TEX TX IP IP • Diagram shows circuit composition during oscillation. • Feedback resistor is removed during stop, and XTAL becomes High level. Oscillation • Diagram shows circuit composition during oscillation. IP • When the operation of the oscillation circuit is stopped by the software, the feedback resistor is removed, and TEX and TX become Low level and High level respectively. Oscillation Pull-up resistor RST AA A AA A OP Mask option Low level IP 1 pin – 10 – Schmitt input CXP84632/84640/84648 Absolute Maximum Ratings Item Supply voltage (Vss = 0V reference) Symbol Rating Unit VDD –0.3 to +7.0 V AVSS V Remarks Input voltagte VIN –0.3 to +0.3 –0.3 to +7.0∗1 Output voltage VOUT –0.3 to +7.0∗1 V High level output current IOH –5 mA Output (value per pin) –50 mA Total for all output pins IOL 15 mA All pins excluding large current outputs (value per pin) IOLC 20 mA Large current outputs (value per pin) ∗2 Low level total output current ∑IOL 100 mA Total for all output pins Operating temperature Topr –20 to +75 °C Storage temperature Tstg –55 to +150 °C Allowable power dissipation PD 600 mW High level total output current ∑IOH Low level output current V ∗1 VIN and VOUT must not exceed VDD + 0.3V. ∗2 The large current output is for each pin of Port C (PC), Port F0 (PF0) to Port 3 (PF3). Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSI. – 11 – CXP84632/84640/84648 Recommended Operating Conditions Item Supply voltage Symbol VDD VIH HIgh level input voltage VIHS VIHEX VIL Low level input voltage VILS VILEX Operating temperature Topr (Vss = 0V reference) Min. Max. Unit Remarks 4.5 5.5 V 3.0 5.5 V fc = 16MHz or less Guaranteed operation range for 1/2 and 1/4 fc = 12MHz or less frequency dividing clock. 2.7 5.5 V Guaranteed operation range for 1/16 frequency dividing clock or SLEEP mode 2.7 5.5 V Guaranteed operation range by TEX clock 2.5 5.5 V 0.7VDD VDD V Guaranteed data hold operation range during STOP ∗1, ∗5 0.8VDD VDD V ∗1, ∗6 0.8VDD VDD V VDD – 0.4 VDD + 0.3 V VDD – 0.2 VDD + 0.2 V Hysteresis input∗2 EXTAL pin∗3, ∗5 TEX pin∗4, ∗5 0 0.3VDD V EXTAL pin∗3, ∗6 TEX pin∗4, ∗6 ∗1, ∗5 0 0.2VDD V ∗1, ∗6 0 0.2VDD V –0.3 0.4 V Hysteresis input∗2 EXTAL pin∗3, ∗5 TEX pin∗4, ∗5 –0.3 0.2 V EXTAL pin∗3, ∗6 TEX pin∗4, ∗6 –20 +75 °C ∗1 Normal input port (each pin of PA, PB4, PB7, PC, PF0 to PF4, PG, PH and PI7) ∗2 Each pin of RST, CINT, CS0, SCK0, SCK1, SCK2, SI0, SI1, SI2, EC0, EC1, RMC, NMI, RxD, INT0, INT1, INT2, INT3 and INT4 ∗3 It is specified only when the external clock is input. ∗4 It is specified only when the external event count clock is input. ∗5 This case applies to the range of 4.5 to 5.5V supply voltage (VDD). ∗6 This case applies to the range of 3.0 to 5.5V supply voltage (VDD). – 12 – CXP84632/84640/84648 Electrical Characteristics DC Characteristics Supply voltage (VDD) 4.5 to 5.5V Item Symbol High level VOH output voltage Low level output voltage VOL Pins PA to PD, PE4, PE5, PF4, PF5, PF6, PG to PI IILT Min. Typ. Max. Unit VDD = 4.5V, IOH = –0.5mA 4.0 V VDD = 4.5V, IOH = –1.2mA 3.5 V 0.4 V VDD = 4.5V, IOL = 3.6mA 0.6 V PC, PF0 to PF3 VDD = 4.5V, IOL = 12.0mA 1.5 V PF0 to PF3 VDD = 4.5V, IOL = 3.0mA (SCL0, SCL1, SDA0, SDA1) VDD = 4.5V, IOL = 4.0mA 0.4 V 0.6 V EXTAL IIHT Input current Conditions VDD = 4.5V, IOL = 1.8mA IIHE IILE (Ta = –20 to +75°C, Vss = 0V reference) TEX IILR RST∗1 IIL PA to PD∗2, PG to PI∗2 IIZ PA to PD∗2, PG to PI∗2, RST∗1 VDD = 5.5V, VIH = 5.5V 0.5 40 µA VDD = 5.5V, VIL = 0.4V –0.5 –40 µA VDD = 5.5V, VIL = 5.5V 0.1 10 µA VDD = 5.5V, VIL = 0.4V –0.1 –10 µA –1.5 –400 µA –45 µA VDD = 5.5V, VIL = 0.4V VDD = 4.5V, VIL = 4.0V –2.78 µA VDD = 5.5V VI = 0, 5.5V ±10 µA Open drain output leakage ILOH current (N-ch Tr off state) PF0 to PF3 VDD = 5.5V (SCL0, SCL1, VOH = 5.5V SDA0, SDA1) 10 µA I2C bus switch connection impedance RBS (Output Tr off state) SCL0: SCL1 SDA0: SDA1 120 Ω I/O lealage current VDD = 4.5V VSCL0 = VSCL1 = 2.25V VSDA0 = VSDA1 = 2.25V – 13 – CXP84632/84640/84648 Item Symbol Pins Conditions Min. Typ. Max. Unit 31 50 mA 40 100 µA 2.5 10 mA 8 30 µA 10 µA 20 pF 1/2 frequency dividing clock operation IDD1 VDD = 5.5V, 16MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3V, 32kHz crystal oscillation; and termination of 16MHz oscillation (C1 = C2 = 47pF) IDD2 Supply current∗3 SLEEP mode IDDS1 IDDS2 IDDS3 Input capacity CIN VDD VDD = 5.5V, 16MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3V, 32kHz crystal oscillation; and termination of 16MHz oscillation (C1 = C2 = 47pF) STOP mode VDD = 5.5V, termination of 16MHz and 32kHz crystal oscillation PA to PC, PE0 to PE5, Clock 1MHz PF to PI, 0V for all pins excluding measured EXTAL, pins TEX, RST 10 ∗1 RST specifies the input current when pull-up resistance has been selected; leakage current when no resistance has been selected. ∗2 PA to PD, and PG to PI specify the input current when pull-up resistance has been selected; leakage current when no resistance has been selected. ∗3 When all pins are open. – 14 – CXP84632/84640/84648 Electrical Characteristics DC Characteristics Supply voltage (VDD) 3.0 to 3.6V Item Symbol High level VOH output voltage Low level output voltage VOL Pins PA to PD, PE4, PE5, PF4, PF5, PF6 IILT Min. Typ. Max. Unit VDD = 3.0V, IOH = –0.15mA 2.7 V VDD = 3.0V, IOH = –0.5mA 2.3 V 0.3 V VDD = 3.0V, IOL = 1.6mA 0.5 V PC, PF0 to PF3 VDD = 3.0V, IOL = 5.0mA 1 V PF0 to PF3 VDD = 3.0V, IOL = 2.0mA (SCL0, SCL1, SDA0, SDA1) VDD = 3.0V, IOL = 2.5mA 0.3 V 0.5 V EXTAL IIHT Input current Conditions VDD = 3.0V, IOL = 1.2mA IIHE IILE (Ta = –20 to +75°C, Vss = 0V reference) TEX IILR RST∗1 IIL PA to PD∗2, PG to PI∗2 IIZ PA to PD∗2, PG to PI∗2, RST∗1 VDD = 3.6V, VIH = 3.6V 0.3 20 µA VDD = 3.6V, VIL = 0.3V –0.3 –20 µA VDD = 3.6V, VIL = 3.6V 0.1 10 µA VDD = 3.6V, VIL = 0.4V –0.1 –10 µA –0.9 –200 µA –20 µA VDD = 3.6V, VIL = 0.3V VDD = 3.0V, VIL = 2.7V –1.0 µA VDD = 3.6V VI = 0, 3.6V ±10 µA Open drain output leakage ILOH current (N-ch Tr off state) PF0 to PF3 VDD = 3.6V (SCL0, SCL1, VOH = 3.6V SDA0, SDA1) 10 µA I2C bus switch connection impedance RBS (Output Tr off state) SCL0: SCL1 SDA0: SDA1 300 Ω I/O lealage current VDD = 3.0V VSCL0 = VSCL1 = 1.5V VSDA0 = VSDA1 = 1.5V – 15 – CXP84632/84640/84648 Item Symbol Pins Conditions Min. Typ. Max. Unit 11 25 mA 0.5 2.5 mA 10 µA 20 pF 1/2 frequency dividing clock operation IDD1 Supply current∗3 SLEEP mode IDDS1 IDDS3 Input capacity VDD = 3.6V, 12MHz crystal oscillation (C1 = C2 = 15pF) CIN VDD VDD = 3.6V, 12MHz crystal oscillation (C1 = C2 = 15pF) STOP mode VDD = 3.6V, termination of 16MHz and 32kHz crystal oscillation PA to PC, PE0 to PE5, Clock 1MHz 0V for all pins excluding measured PF to PI, pins EXTAL, TEX, RST 10 ∗1 RST specifies the input current when pull-up resistance has been selected; leakage current when no resistance has been selected. ∗2 PA to PD, and PG to PI specify the input current when pull-up resistance has been selected; leakage current when no resistance has been selected. ∗3 When all pins are open. – 16 – CXP84632/84640/84648 AC Characteristics (1) Clock timing (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item Symbol System clock frequency fC System clock input pulse width tXL tXH System clock input rise time, fall time Event count input clock rise time, fall time tCR tCF tEH tEL tER tEF System clock frequency fC Event count input clock input pulse width tTL tTH tTR tTF Event count input clock pulse width Event count input clock rise time, fall time Pin Conditions Min. VDD = 4.5 to 5.5V XTAL EXTAL Fig. 1, Fig. 2 EXTAL Fig. 1, Fig. 2 VDD = 4.5 to 5.5V External clock drive EXTAL Fig. 1, Fig. 2 External clock drive EC0 EC1 Fig. 3 EC0 EC1 Fig. 3 TEX TX VDD = 2.7 to 5.5V Fig. 2 (32kHz clock applied condition) TEX Fig. 3 TEX Fig. 3 Typ. Max. 1 16 1 12 Unit MHz 28 ns 37.5 ns 200 4tsys∗1 ns 20 ms kHz 32.768 µs 10 20 ms ∗1 tsys indicates the three values below according to the upper two bits (CPU clock selection) of the control clock register (CLC: 00FEH). tsys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (Upper two bits = “11”) 1/fc Fig. 1. Clock timing VDD – 0.4V (VDD = 4.5 to 5.5V) VDD – 0.3V EXTAL 0.4V (VDD = 4.5 to 5.5V) 0.3V tXH tCF tXL tCR AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA Fig. 2. Clock applied conditions Crystal oscillation Ceramic oscillation EXTAL XTAL C1 External clock EXTAL C2 32kHz clock applied condition Crystal oscillation TEX XTAL 74HC04 C1 TX C2 Fig. 3. Event count clock timing TEX EC0 EC1 0.8VDD 0.2VDD tEH tTH tEF tTF – 17 – tEL tTL tER tTR CXP84632/84640/84648 (2) Serial transfer (CH0) Item Symbol (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Pin Condition Min. Max. Unit CS↓ → SCK delay time tDCSK SCK0 Chip select transfer mode (SCK = output mode) tsys + 200 ns CS↑ → SCK floating delay time tDCSKF SCK0 Chip select transfer mode (SCK = output mode) tsys + 200 ns CS↓ → SO delay time tDCSO SO0 Chip select transfer mode tsys + 200 ns CS↓ → SO floating delay time tDCSOF SO0 Chip select transfer mode tsys + 200 ns CS High level width tWHCS CS0 Chip select transfer mode SCK cycle time tKCY SCK0 SCK High and Low level widths tKH tKL SCK0 SI input setup time (against SCK↑) tSIK SI0 SI input hold time (against SCK↑) tKSI SI0 SCK↓ → SO delay time tKSO SO0 Input mode Output mode Input mode Output mode SCK input mode SCK output mode SCK input mode SCK output mode SCK input mode SCK output mode tsys + 200 2tsys + 200 ns 16000/fc ns tsys + 100 ns 8000/fc – 100 ns –tsys + 100 ns 200 ns 2tsys + 100 ns 100 ns ns 2tsys + 200 ns 100 ns Note 1) tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (upper 2 bits = “00”), 4000/fc (upper 2 bits = “01”), 16000/fc (upper 2 bits = “11”) Note 2) CS, SCK, SI and SO represent CS0, SCK0, SI0 and SO0, respectively. Note 3) The load of SCK output mode and SO output delay time is 50pF + 1TTL. – 18 – CXP84632/84640/84648 Serial transfer (CH0) Item (Ta = –20 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V reference) Symbol Pin Condition Min. Max. Unit CS↓ → SCK delay time tDCSK SCK0 Chip select transfer mode (SCK = output mode) tsys + 250 ns CS↑ → SCK floating delay time tDCSKF SCK0 Chip select transfer mode (SCK = output mode) tsys + 200 ns CS↓ → SO delay time tDCSO SO0 Chip select transfer mode tsys + 250 ns CS↓ → SO floating delay time tDCSOF SO0 Chip select transfer mode tsys + 200 ns CS High level width tWHCS CS0 Chip select transfer mode SCK cycle time tKCY SCK0 SCK High and Low level widths tKH tKL SCK0 SI input setup time (against SCK↑) tSIK SI0 SI input hold time (against SCK↑) tKSI SI0 SCK↓ → SO delay time tKSO SO0 Input mode Output mode Input mode Output mode SCK input mode SCK output mode SCK input mode SCK output mode SCK input mode SCK output mode tsys + 200 2tsys + 200 ns 16000/fc ns tsys + 100 ns 8000/fc – 150 ns –tsys + 100 ns 200 ns 2tsys + 100 ns 100 ns ns 2tsys + 250 ns 125 ns Note 1) tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (upper 2 bits = “00”), 4000/fc (upper 2 bits = “01”), 16000/fc (upper 2 bits = “11”) Note 2) CS, SCK, SI and SO represent CS0, SCK0, SI0 and SO0, respectively. Note 3) The load of SCK output mode and SO output delay time is 50pF. – 19 – CXP84632/84640/84648 Fig. 4. Serial transfer CH0 timing tWHCS CS0 0.8VDD 0.2VDD tKCY tDCSK tKL tDCSKF tKH 0.8VDD 0.8VDD SCK0 0.2VDD tSIK tKSI 0.8VDD Input data SI0 0.2VDD tDCSO tKSO tDCSOF 0.8VDD SO0 Output data 0.2VDD – 20 – CXP84632/84640/84648 Serial transfer (CH1, CH2) Item (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol Pin Condition Min. Max. Unit 2tsys + 200 ns 16000/fc ns tsys + 100 ns 8000/fc – 50 ns SCK input mode 100 ns SCK output mode 200 ns tsys + 200 ns 100 ns tKCY SCK1 SCK2 Input mode SCK cycle time SCK High and Low level widths tKH tKL SCK1 SCK2 Input mode SI input setup time (against SCK↑) tSIK SI1 SI2 SI input hold time (against SCK↑) tKSI SI1 SI2 SCK input mode SCK↓ → SO delay time tKSO SO1 SO2 SCK input mode Output mode Output mode SCK output mode SCK output mode tsys + 200 ns 100 ns Note 1) tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01’), 16000/fc (Upper 2 bits = “11”) Note 2) SCK, SI and SO represent SCK1, SI1, and SO1, respectively for CH1; they represent SCK2, SI2 and SO2, respectively for CH2. Note 3) The load of SCK1 and SCK2 output modes and SO1 and SO2 output delay times is 50pF+1TTL. Serial transfer (CH1, CH2) Item (Ta = –20 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V reference) Symbol Pin Condition Min. Max. Unit 2tsys + 200 ns 16000/fc ns tsys + 100 ns 8000/fc – 150 ns SCK input mode 100 ns SCK output mode 200 ns tsys + 200 ns 100 ns tKCY SCK1 SCK2 Input mode SCK cycle time SCK High and Low level widths tKH tKL SCK1 SCK2 Input mode SI input setup time (against SCK↑) tSIK SI1 SI2 SI input hold time (against SCK↑) tKSI SI1 SI2 SCK input mode SCK↓ → SO delay time tKSO SO1 SO2 SCK input mode Output mode Output mode SCK output mode SCK output mode tsys + 250 ns 125 ns Note 1) tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01’), 16000/fc (Upper 2 bits = “11”) Note 2) SCK, SI and SO represent SCK1, SI1, and SO1, respectively for CH1; they represent SCK2, SI2 and SO2, respectively for CH2. Note 3) The load of SCK1 and SCK2 output modes and SO1 and SO2 output delay times is 50pF. – 21 – CXP84632/84640/84648 Fig. 5. Serial transfer CH1 and CH2 timing tKCY tKL tKH 0.8VDD SCK1 SCK2 0.2VDD tSIK tKSI 0.8VDD SI1 SI2 Input data 0.2VDD tKSO 0.8VDD SO1 SO2 Output data 0.2VDD – 22 – CXP84632/84640/84648 (3) A/D converter characteristics (Ta = –20 to +75°C, VDD = 3.0 to 5.5V, AVREF = 2.7 to VDD, Vss = AVSS = 0V reference) Item Symbol Max. Unit Resolution 8 Bits Linearity errror ±3 LSB Zero transition voltage VZT∗1 Full-scale transition voltage VFT∗2 Pin Condition Min. Ta = 25°C VDD = AVREF = 5.0V VSS = AVSS = 0V Typ. –50 10 70 mV 4910 4970 5030 mV ±5 LSB Linearity errror Zero transition voltage VZT∗1 Full-scale transition voltage VFT∗2 Convertion time tCONV Sampling time tSAMP Reference input voltage VREF Analog input voltage VIAN Ta = 25°C VDD = AVREF = 3.3V VSS = AVSS = 0V 6.5 70 mV 3215 3280 3345 mV 160/fADC∗3 12/fADC∗3 AVREF µs VDD – 0.5 VDD V VDD = 3.0 to 3.6V VDD – 0.3 VDD V 0 AVREF V 0.6 1.0 mA 0.4 0.7 mA 10 µA Operation VDD = 5.5V mode VDD = 3.6V AVREF µs VDD = 4.5 to 5.5V AN0 to AN7 IREF AVREF current –10 SLEEP mode STOP mode 32kHz operation mode IREFS Fig.6. Definition of A/D converter terms ∗1 VZT: Value at which the digital conversion value changes from 00H to 01H and vice versa. ∗2 VFT: Value at which the digital conversion value changes from FEH to FFH and vice versa. ∗3 fADC indicates the below values due to the contents of bit 6 (CKS) of the A/D control register (ADC: 00F9H) and bits 7 (PCK1) and 6 (PCK0) of the clock control register (CLC: 00FEH). Digital conversion value FFH FEH Linearity error CKS 01H 00H VFT VZT Analog input 0(φ/2 selection) 1(φ selection) PCK1, PCK0 00 (φ = fEX/2) fADC = fC/2 fADC = fC 01 (φ = fEX/4) fADC = fC/4 fADC = fC/2 11 (φ = fEX/16) fADC = fC/16 fADC = fC/8 – 23 – CXP84632/84640/84648 (4) Interruption, reset input (Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V reference) Item Symbol Pin External interruption HIgh, Low level width tIH tIL INT0 INT1 INT2 INT3 INT4 NMI Reset input Low level width tRSL RST Condition Min. Max. Unit 1 µs 32/fc µs Fig. 7. Interruption input timing tIH INT0 INT1 INT2 INT3 INT4 NMI (NMI is specified only for the falling edge) tIL 0.8VDD 0.2VDD tIL tIH Fig. 8. RST input timing tRSL RST 0.2VDD – 24 – CXP84632/84640/84648 (5) I2C bus timing (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item Symbol Pin Condition Min. Max. Unit 0 100 kHz SCL clock frequency fSLC SCL Bus-free time before starting transfer tBUF tHD; STA tLOW tHIGH tSU; STA tHD; DAT tSU; DAT tR tF tSU; STO SDA, SCL 4.7 µs SDA, SCL 4.0 µs SCL 4.7 µs SCL 4.0 µs SDA, SCL µs SDA, SCL 4.7 0∗1 SDA, SCL 250 ns Hold time for starting transfer Clock Low level width Clock High level width Setup time for repetitive transfers Data bold time Data setup time SDA, SCL rise time SDA, SCL fall time Setup time for transfer completion µs SDA, SCL 1 µs SDA, SCL 300 ns SDA, SCL 4.7 µs ∗1 The data hold time must exceed 300ns because the SCL rise time (300ns max.) is not taken into consideration. Fig. 9. I2C bus transfer timing SDA tBUF tR tF tHD; STA SCL tHD; STA tSU; STA P S tLOW tHD; DAT tHIGH St tSU; DAT tSU; STO P Fig. 10. Recommended circuit example for I2C device I2C device RS I2C device RS RS R S RP RP SDA0 (or SDA1) SCL0 (or SCL1) • Pull-up resistors (RP) must be connected to SDA0 (or SDA1) and SCL0 (or SCL1). • Serial resistance (Rs = 300Ω or less) of SDA0 (or SDA1) and SCL0 (or SCL1) reduces spike noise caused by CRT flash-over. – 25 – CXP84632/84640/84648 Appendix Fig. 11. SPC700 Series recommended oscillation circuit AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA (i) EXTAL (ii) TEX XTAL Rd C1 C2 Manufacturer Model RIVER ELETEC CO., LTD. HC-49/U03 TX Rd C2 C1 Rd (Ω) Circuit example 0 (i) fc (MHz) C1 (pF) C2 (pF) 8.00 10 10 5 5 8.00 16 (12) 16 (12) 10.00 16 (12) 16 (12) 12.00 12 12 0 16.00 12 12 0 32.768kHz 30 18 470k 10.00 12.00 16.00 HC-49/U (-S) KINSEKI LTD. P3 Mask option table Item Reset pin pull-up resistor Content Existent Non-existent – 26 – 0 (i) (ii) CXP84632/84640/84648 Characteristics Curve IDD vs. VDD IDD vs. VDD (fc = 16MHz, Ta = 25°C, Typical) (fc = 12MHz, Ta = 25°C, Typical) 50.0 50.0 1/2 frequency mode 1/4 frequency mode 1/2 frequency mode 10.0 10.0 1/16 frequency mode 5.0 1/4 frequency mode 5.0 SLEEP mode 1.0 0.5 32kHz mode (instruction) 0.1 (100µA) IDD–Supply current [mA] IDD–Supply current [mA] 1/16 frequency mode 32kHz SLEEP mode 0.05 (50µA) 0.01 (10µA) SLEEP mode 1.0 0.5 0.1 (100µA) 0.05 (50µA) 0.01 (10µA) 3 4 5 6 3 VDD–Supply voltage [V] 5 6 IDD vs. fc IDD vs. fc (VDD = 5.0V, Ta = 25°C, Typical) (VDD = 3.3V, Ta = 25°C, Typical) 30 30 1/2 frequency mode 20 1/4 frequency mode 10 IDD–Supply current [mA] IDD–Supply current [mA] 4 VDD–Supply voltage [V] 20 1/2 frequency mode 10 1/4 frequency mode 1/16 frequency mode 0 SLEEP mode 1 5 10 15 16 fc–System clock [MHz] 1/16 frequency mode 0 SLEEP mode 1 5 10 fc–System clock [MHz] – 27 – 15 16 CXP84632/84640/84648 Package Outline Unit: mm 80PIN QFP (PLASTIC) 23.9 ± 0.4 + 0.1 0.15 – 0.05 + 0.4 20.0 – 0.1 64 0.15 41 65 16.3 17.9 ± 0.4 + 0.4 14.0 – 0.1 40 A + 0.2 0.1 – 0.05 25 1 24 0.8 0.12 M + 0.15 0.35 – 0.1 + 0.35 2.75 – 0.15 0° to 10° DETAIL A PACKAGE STRUCTURE SONY CODE QFP-80P-L01 EIAJ CODE ∗QFP080-P-1420-A JEDEC CODE PACKAGE MATERIAL EPOXY RESIN LEAD TREATMENT SOLDER PLATING LEAD MATERIAL COPPER / 42 ALLOY PACKAGE WEIGHT 1.6g – 28 – 0.8 ± 0.2 80