CXP828P60
CMOS 8-bit Single Chip Microcomputer
Description
The CXP828P60 is a CMOS 8-bit single chip
microcomputer integrating on a single chip an A/D
converter, serial interface, timer/counter, time base
timer, capture timer/counter, fluorescent display panel
controller/driver, remote control reception circuit, and
PWM output circuit besides the basic configurations
of 8-bit CPU, PROM, RAM, and I/O port.
The CXP828P60 also provides sleep/stop function
that enables lower power consumption.
CXP828P60 is the PROM-incorporated version of
the CXP82860 with bult-in mask ROM. This provides
the additional feature of being able to write directly
into the program. Thus, it is most suitable for
evaluation use during system development and for
small-quantity production.
100 pin QFP (Plastic)
Structure
Silicon gate CMOS IC
Features
• Wide-range instruction system (213 instructions) to cover various types of data
— 16-bit arithmetic/multiplication and division/Boolean bit operation instructions
• Minimum instruction cycle
400ns at 10MHz operation
122µs at 32kHz operation
• Incorporated PROM capacity
60K bytes
• Incorporated RAM capacity
1536 bytes (including fluorescent display area)
• Peripheral functions
— A/D converter
8 bist, 8 channels, successive approximation method
(Conversion time of 32µs/10MHz)
— Serial interface
8-bit, 8-stage FIFO incorporated
(Auto transfer for 1 to 8 bytes), 1 channel
8-bit clock synchronized type, 1 channel
— Timer
8-bit timer, 8-bit timer/counter, 19-bit time base timer
16-bit capture timer/counter, 32kHz timer/counter
— Fluorescent display panel controller/driver Supports the universal grid fluorescent display panel.
High voltage drive output port of 56 pins (40V)
Maximum of 640 segments display possible
Display timing number of 1 to 20
Dimmer function
Incorporated pull-down resistor
Hardware key scan function (Maximum of 16 x 8 key matrix
supportable)
— Remote control reception circuit
8-bit pulse measurement counter, 6-stage FIFO
— PWM output
14 bits, 1 channel
• Interruption
16 factors, 15 vectors, multi-interruption possible
• Standby mode
SLEEP/STOP
• Package
100-pin plastic QFP
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E95Z36-ST
8
32
A16 to A23
A24 to A55
VFDP
KR0 to KR7
AVREF
RAM
ADJ
TO
CINT
EC1
16 BIT CAPTURE
TIMER/COUNTER 2
8 BIT TIMER 1
8 BIT TIMER/COUNTER 0
EC0
FIFO
SERIAL INTERFACE UNIT 1
SERIAL
INTERFACE
UNIT 0
CS0
SI0
SO0
SCK0
FIFO
SI1
SO1
SCK1
REMOCON
14 BIT PWM GENERATOR
KEY SCAN
FDP
CONTROLLER/
DRIVER
A/D CONVERTER
2
2
INTERRUPT CONTROLLER
AVSS
RMC
PWM
16
G0/A0 to G15/A15
8
8
AN0 to AN7
2
PRESCALER/
TIME BASE TIMER
PROM
60K BYTES
SPC 700
CPU CORE
TEX
TX
EXTAL
XTAL
RST
VDD
VSS
32KHz
TIMER/COUNTER
RAM
1536 BYTES
CLOCK
GENERATOR/
SYSTEM CONTROL
PB0 to PB7
PC0 to PC7
PD0 to PD7
PE0 to PE5
PE6 to PE7
PF0 to PF7
PG0 to PG7
8
8
8
6
2
8
8
8
PH0 to PH7
PA0 to PA7
8
PORT B
PORT E
–2–
PORT F
INT0
INT1
INT2
INT3/NMI
2
PORT A
PORT C
PORT D
PORT G
PORT H
Block Diagram
CXP828P60
CXP828P60
A20
A19
A18
A17
A16
G15/A15
G14/A14
G13/A13
VDD
G12/A12
G11/A11
G10/A10
G9/A9
G8/A8
G7/A7
G6/A6
G5/A5
G4/A4
G3/A3
G2/A2
Pin Assignment (Top View)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
G1/A1
1
80
A21
G0/A0
2
79
A22
Vpp
3
78
A23
PE0/EC0/INT0
4
77
PH7/A24
PE1/EC1/INT1
5
76
PH6/A25
PE2/INT2
6
75
PH5/A26
PE3/INT3/NMI
7
74
PH4/A27
PE4/RMC
8
73
PH3/A28
PE5
9
72
PH2/A29
PE6/PWM
10
71
PH1/A30
PE7/TO/ADJ
11
70
PH0/A31
PC0/KR0
12
69
PG7/A32
PC1/KR1
13
68
PG6/A33
PC2/KR2
14
67
PG5/A34
PC3/KR3
15
66
PG4/A35
PC4/KR4
16
65
PG3/A36
PC5/KR5
17
64
PG2/A37
PC6/KR6
18
63
PG1/A38
PC7/KR7
19
62
PG0/A39
PB0/CINT
20
61
PF7/A40
PB1/CS0
21
60
PF6/A41
PB2/SCK0
22
59
PF5/A42
PB3/SI0
23
58
PF4/A43
PB4/SO0
24
57
PF3/A44
PB5/SCK1
25
56
PF2/A45
PB6/SI1
26
55
PF1/A46
PB7/SO1
27
54
PF0/A47
AVREF
28
53
PD7/A48
PA0/AN0
29
52
PD6/A49
PA1/AN1
30
51
PD5/A50
Note) Vpp (Pin 3) must be connected to VDD.
–3–
PD4/A51
PD3/A52
PD2/A53
PD1/A54
PD0/A55
VFDP
VDD
TEX
TX
Vss
XTAL
EXTAL
RST
AVSS
PA7/AN7
PA6/AN6
PA5/AN5
PA4/AN4
PA3/AN3
PA2/AN2
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
CXP828P60
Pin Description
Pin code
I/O
Functions
(Port A)
8-bit I/O port. I/O can be set in a
unit of single bits. Incorporation
of the pull-up resistance can be
set through the software in a unit
of 4 bits.
(8pins)
PA0/AN0
to
PA7/AN7
I/O/
Analog input
PB0/CINT
I/O/Input
PB1/CS0
I/O/Input
PB2/SCK0
I/O/I/O
PB3/SI0
I/O/Input
PB4/SO0
I/O/Output
PB5/SCK1
I/O/I/O
PB6/SI1
I/O/Input
Serial data input (CH1).
PB7/SO1
I/O/Output
Serial data output (CH1).
Analog inputs to A/D converter.
(8 pins)
Capture input to 16-bit timer/counter.
(Port B)
8-bit I/O port. I/O can be set in a
unit of single bits. Incorporation
of the pull-up resistance can be
set through the software in a unit
of 4 bits.
(8 pins)
Chip select input for serial interface (CH0).
Serial clock I/O (CH0).
Serial data input (CH0).
Serial data output (CH0).
Serial clock I/O (CH1).
PC0/KR0
to
PC7/KR7
I/O/Input
(Port C)
8-bit I/O port. I/O can be set in a
unit of single bits. Capable of
driving 12mA sync current.
Incorporation of the pull-up
resistance can be set through
the software in a unit of 4 bits.
(8 pins)
PD0/A55
to
PD7/A48
Output/Output
(Port D)
8-bit output port.
(8 pins)
PE0/INT0/
EC0
Input/Input/Input
PE1/INT1/
EC1
Input/Input/Input
PE2/INT2
Input/Input
PE3/INT3/
NMI
Input/Input/Input
PE4/RMC
Input/Input
PE5
Input
PE6/PWM
Output/Output
14-bit PWM output.
PE7/TO/ADJ
Output/Output/
Output
Output for the 16-bit timer/counter
rectangular waves, and 32kHz
oscillation frequency division.
PF0/A47
to
PF7/A40
Output/Output
(Port E)
8-bit port. Lower 6 bits are for
inputs; upper 2 bits are for
outputs.
(8 pins)
(Port F)
8-bit output port.
(8pins)
–4–
Serves as key return inputs when
operating key scan with fluorescent
display panel (FDP) segment signal.
(8 pins)
FDP segment signal (anode
connection) outputs.
Inputs for
external
interruption
request.
(4 pins)
External event inputs
for timer/counter.
(2 pins)
Non-maskable
interruption request input.
Remote control reception circuit input.
FDP segment signal (anode
connection) outputs.
CXP828P60
Pin code
I/O
Functions
PG0/A39
to
PG7/A32
Output/Output
(Port G)
8-bit output port.
(8 pins)
FDP segment signal (anode
connection) outputs.
PH0/A31
to
PH7/A24
Output/Output
(Port H)
8-bit output port.
(8 pins)
FDP segment signal (anode
connection) outputs.
(8 pins)
A16 to A23
Output
FDP segment signal (anode connection) outputs.
(8 pins)
G0/A0
to
G15/A15
Output/Output
Outputs for FDP timing signals (grid connection)/segment signals (anode
connection).
(16 pins)
VFDP
FDP voltage supply for incorporated pull-down (PD) resistor.
Crystal connectors for system clock oscillation. When the clock is
supplied externally, input to EXTAL; opposite phase clock should be
input to XTAL.
EXTAL
Input
XTAL
Output
TEX
Input
TX
Output
Crystal connectors for 32kHz timer/counter clock oscillation. For usage
as event input, input to TEX, and open TX.
RST
Input
Low-level active, system reset.
AVREF
Input
Reference voltage input for A/D converter.
AVSS
A/D converter GND.
VDD
VCC supply.
Vpp
Vcc supply for incorporated PROM writing.
Connect to VDD during normal operation.
VSS
GND.
–5–
CXP828P60
I/O Circuit Format for Pins
Pin
When reset
Circuit format
Port A
∗
Pull-up resistor
"0" when reset
Port A data
PA0/AN0
to
PA7/AN7
Port A direction
IP Input protection circuit
"0" when reset
Hi-Z
Data bus
RD (Port A)
Port A input selection
Input multiplexer
"0" when reset
A/D converter
∗ Pull-up transistor approx.
8 pins
100kΩ
Port B
∗
Pull-up resistor
"0" when reset
Port B data
PB0/CINT
PB1/CS0
PB3/SI0
PB6/SI1
Port B direction
IP
Hi-Z
"0" when reset
Schmitt input
Data bus
RD (Port B)
CINT
CS0
SI0
SI1
4 pins
∗ Pull-up transistor approx.
100kΩ
Port B
∗
Pull-up resistor
"0" when reset
SCK OUT
Serial clock output enable
Port B output selection
PB2/SCK0
PB5/SCK1
"0" when reset
Hi-Z
Port B data
IP
Port B direction
"0" when reset
Schmitt input
Data
bus
RD (Port B)
2 pins
∗ Pull-up transistor approx.
100kΩ
SCK in
–6–
CXP828P60
Pin
When reset
Circuit format
Port B
∗
Pull-up resistor
"0" when reset
SO
Serial data output enable
Port B output selection
PB4/SO0
PB7/SO1
"0" when reset
Hi-Z
Port B data
IP
Port B direction
"0" when reset
Data
bus
RD (Port B)
∗ Pull-up transistor approx.
100kΩ
2 pins
Port C
∗2
Pull-up resistor
"0" when reset
Port C data
PC0/KR0
to
PC7/KR7
Hi-Z
∗1
Port C direction
IP
"0" when reset
Data bus
∗1 Large current 12mA
∗2 Pull-up transistor approx. 100kΩ
RD (Port C)
8 pins
Key input signal
Port E
PE0/EC0/INT0
PE1/EC1/INT1
PE2/INT2
PE3/INT3/NMI
PE4/RMC
EC0/INT0
EC1/INT1
INT2
INT3/NMI
RMC
Data bus
Schmitt input
IP
Hi-Z
RD (Port E)
5 pins
PE5
Port E
Data bus
IP
1 pin
RD (Port E)
–7–
Hi-Z
CXP828P60
Pin
When reset
Circuit format
Port E
PWM
Port E output selection
"0" when reset
PE6/PWM
High level
Port E data
Output enable
"1" when reset
Data bus
1 pin
RD (Port E)
Port E
Internal reset signal
PE7/TO/ADJ
Port E data
00
TO
"1" when reset
ADJ16K∗1
ADJ2K∗1
01
10
11
MPX
∗2
Port E output selection (upper)
Port E output selection (lower)
∗1 ADJ signal is a frequency dividing output
for 32kHz oscillation frequency adjustment.
ADJ2K can be used for buzzer output.
"00" when reset
TO output enable
∗2
High level
(with approx.
150kΩ
resistor when
reset)
Pull-up transistor approx. 150kΩ
1 pin
PD0/A55
to
PD7/A48
PF0/A47
to
PF7/A40
PG0/A39
to
PG7/A32
PH0/A31
to
PH7/A24
Port D
Port F
Segment output data
Port G
Port H
Output selection control signal
("0" when reset)
∗
Hi-Z or Low
level (when
PD resistor is
connected)
Port D, F, G and H data
"0" when reset
Data bus
RD (Port D, F, G and H)
32 pins
–8–
∗ High voltage drive transistor
CXP828P60
Pin
When reset
Circuit format
Segment output data
∗
Output selection control signal
("0" when reset)
A16 to A23
Pull-down resistor
VFDP
Hi-Z or
Low level
(when PD
resistor is
connected)
∗ High voltage drive transistor
8 pins
Segment output data
Timing output data
G0/A0
to
G15/A15
∗
Output selection control signal
("0" when reset)
Pull-down resistor
VFDP
Hi-Z or
Low level
(when PD
resistor is
connected)
∗ High voltage drive transistor
16 pins
EXTAL
XTAL
EXTAL
IP
IP
• Diagram shows circuit
composition during
oscillation.
• Feedback resistor is
removed and XTAL
becomes High level
during stop.
XTAL
Oscillation
2 pins
TEX
TX
• Diagram shows circuit
composition during
oscillation.
TEX
IP
IP
TX
2 pins
• When the operation of the
oscillation circuit is
stopped by the software,
the feedback resistor is
removed, and TEX
becomes Low level and
TX becomes High level.
Oscillation
Pull-up resistor
RST
Low level
IP
Schmitt input
1 pin
–9–
CXP828P60
Absolute Maximum Ratings
Item
Rating
Unit
VDD
–0.3 to +7.0
V
Vpp
–0.3 to +13.0
V
AVss
–0.3 to +0.3
V
A/D converter GND
voltage
AVSS
–0.3 to +0.3
V
A/D converter reference
voltage
AVREF
–0.3 to +7.0∗1
V
FDP display supply
voltage
VFDP
–40∗2 to +7.0∗1
V
Input voltage
VIN
Output voltage
VOUT
–0.3 to +7.0∗1
–0.3 to +7.0∗1
Display output voltage
VOD
–40∗2 to +7.0∗1
V
IOH
–5
mA
All pins excluding display outputs∗3
(value per pin)
IODH1
–15
mA
Display outputs A20 to A55 (value per pin)
IODH2
–50
mA
Display outputs G0/A0 to G15/A15, and
A16 to A19 (value per pin)
∑IOH
–30
mA
Total for all pins excluding display outputs
∑IODH
–120
mA
Total for all display outputs
IOL
15
mA
Port (value per pin)
IOLC
20
mA
Large current port (value per pin)∗4
Low level total output current ∑IOL
100
mA
Total for all output pins
Supply voltage
High level output current
High level total output
current
Low level output current
Symbol
(Vss = 0V reference)
V
Topr
–20 to +75
°C
Storage temperature
Tstg
–55 to +150
°C
600
mW
∗1)
∗2)
∗3)
∗4)
Incorporated PROM
V
Operating temperature
Allowable power dissipation PD
Remarks
VIN, VOUT, VOD and AVREF must not exceed VDD + 0.3V.
VFDP and VOD must not exceed VDD – 40V.
Specifies output current of general-purpose I/O ports.
The large current drive transistor is the N-CH transistor of Port C (PC).
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be
conducted under the recommended operating conditions. Exceeding these conditions may adversely affect
the reliability of the LSI.
– 10 –
CXP828P60
Recommended Operating Conditions
Item
Supply voltage
High level input
voltage
Symbol
Min.
Max.
Unit
4.5
5.5
V
Guaranteed operation range during
high-speed mode (1/2, 1/4 frequency
dividing clock)
3.5
5.5
V
Guaranteed operation range during
low-speed mode or SLEEP mode
(1/16 frequency dividing clock)
2.7
5.5
V
Guaranteed operation range with TEX
clock
2.5
5.5
V
VIH
0.7VDD
VDD
V
VIHS
0.8VDD
VDD
V
VDD
VIHEX
Low level input
voltage
Operating temperature
(Vss = 0V reference)
VDD – 0.4 VDD + 0.3
Remarks
Guaranteed data hold range during STOP
∗1
V
Hysteresis input∗2
EXTAL∗3
∗1
VIL
0
0.3VDD
V
VILS
0
0.2VDD
V
VILEX
–0.3
0.4
V
Topr
–10
+75
°C
Hysteresis input∗2
EXTAL∗3
∗1) Value for each pin of normal input port (PA, PB4, PB7, PC).
∗2) Value of the following pins: RST, CINT, CS0, SCK0, SCK1, EC0/INT0, EC1/INT1, INT2, INT3/NMI, RMC.
∗3) Specifies only during external clock input.
– 11 –
CXP828P60
Electrical Characteristics
DC Characteristics
Item
High level
output current
Low level
output current
(Ta = –10 to +75°C, VSS = 0V reference)
Symbol
Pins
3.5
V
EXTAL
TEX
IILR
RST
IIL
PA to PC∗1
0.4
V
VDD = 4.5V, IOL = 3.6mA
0.6
V
VDD = 4.5V, IOL = 12.0mA
1.5
V
VDD = 5.5V, VIH = 5.5V
0.5
40
µA
VDD = 5.5V, VIL = 0.4V
–0.5
–40
µA
VDD = 5.5V, VIL = 5.5V
0.1
10
µA
VDD = 5.5V, VIL = 0.4V
–0.1
–10
µA
–1.5
–400
µA
–50
µA
VDD = 5.5V, VIL = 0.4V
VDD = 4.5V, VIL = 4.0V
A20 to A55
Display output
IOH
current
Open drain
output leakage
current (P-CH
Tr off state)
ILOL
Pull-down
resistance
RL
I/O leakage
current
IIZ
Unit
PA, PB, PC, VDD = 4.5V, IOH = –1.2mA
PE6, PE7
VDD = 4.5V, IOL = 1.8mA
IIHE
IILT
Max.
V
PC
Input current
Typ.
4.0
VOL
IIHT
Min.
VDD = 4.5V, IOH = –0.5mA
VOH
IILE
Conditions
G0/A0 to
G15/A15
A16 to A19
VDD = 4.5V
VOH = VDD –2.5V
G0/A0 to
G15/A15
A16 to A55
VDD = 5.5V
VOL = VDD –35V
VFDP = VDD –35V
G0/A0 to
G15/A15
A16 to A55
PA to PC∗1
PE0 to PE5
RST
VDD = 5V
VOD –VFDP = 30V
VDD = 5.5V
VI = 0, 5.5V
– 12 –
–3.3
µA
–8
mA
–30
mA
60
100
–20
µA
270
kΩ
±10
µA
CXP828P60
Item
Symbol
Pins
Conditions
VDD = 5.5V, 10MHz crystal
oscillation (C1 = C2 = 15pF)
VDD = 3V, 32kHz crystal
oscillation (C1 = C2 = 47pF)
IDD2
IDDS1
VDD
VDD = 3V, 32kHz crystal
oscillation (C1 = C2 = 47pF)
Unit
22
50
mA
45
130
µA
2.3
10
mA
11
30
µA
30
µA
20
pF
STOP mode
VDD = 5.5V, termination of 10MHz
and 32kHz oscillation
IDDS3
CIN
Max.
SLEEP mode
VDD = 5.5V, 10MHz crystal
oscillation (C1 = C2 = 15pF)
IDDS2
Input
capacity
Typ.
High-speed mode operation
(1/2 frequency dividing clock)
IDD1
Power supply
current∗2
Min.
PA to AC,
PE0 to 5,
XTAL,
EXTAL,
TEX, RST
Clock 1MHz
0V for all pins excluding
measured pins
10
∗1) PA to PC pins specify the input current when pull-up resistance has been selected; leakage current when
no resistance has been selected.
∗2) When all pins are open.
– 13 –
CXP828P60
AC Characteristics
(1) Clock timing
(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
System clock frequency
fC
Event count input clock
rise time, fall time
tXL
tXH
tCR
tCF
tEH
tEL
tER
tEF
System clock frequency
fC
Event count input
pulse width
tTL
tTH
tTR
tTF
System clock input pulse width
System clock input rise time,
fall time
Event count input clock
pulse width
Event count input rise time,
fall time
Pin
Conditions
Min.
Typ.
XTAL
EXTAL
Fig. 1, Fig. 2
EXTAL
Fig. 1, Fig. 2
External clock drive
37.5
EXTAL
Fig. 1, Fig. 2
External clock drive
tsys + 50∗1
EC0,
EC1
Fig. 3
EC0,
EC1
Fig. 3
TEX
TX
VDD = 2.7 to 5.5V
Fig. 2 (32kHz clock
applied condition)
TEX
Fig. 3
TEX
Fig. 3
1
Max.
Unit
10
MHz
ns
200
ns
ns
20
ms
kHz
32.768
µs
10
20
ms
∗1) tsys indicates the three values below according to the upper two bits (CPU clock selection) of the control
clock register (CLC: 00FEH).
tsys (ns)=2000/fc (upper two bits="00"), 4000/fc (upper two bits="01"), 16000/fc (upper two bits="11")
1/fc
Fig. 1. Clock timing
VDD – 0.4V
EXTAL
0.4V
tCF
tXH
tXL
tCR
AAAAA
AAAA
AAAA
AAAAAAAAA AAAA
AAAAAAAAA AAAA
Fig. 2. Clock applied conditions
Crystal oscillation
Ceramic oscillation
EXTAL
External clock
EXTAL
XTAL
C1
C2
32kHz clock applied condition
Crystal oscillation
TEX
XTAL
74HC04
TX
C1
C2
Fig. 3. Event count clock timing
0.8VDD
TEX
EC0
EC1
0.2VDD
tEH
tTH
tEF
tTF
– 14 –
tEL
tTL
tER
tTR
CXP828P60
(2) Serial transfer (CH0)
Item
(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Symbol
Condition
Pin
Min.
Max.
Unit
CS0 ↓ → SCK0
delay time
tDCSK
SCK0
Chip select transfer mode
(SCK0 = output mode)
tsys + 200
ns
CS0 ↑ → SCK0
float delay time
tDCSKF SCK0
Chip select transfer mode
(SCK0 = output mode)
tsys + 200
ns
CS0 ↓ → SO0
delay time
tDCSO
SO0
Chip select transfer mode
tsys + 200
ns
CS0 ↑ → SO0
float delay time
tDCSOF SO0
Chip select transfer mode
tsys + 200
ns
CS0 High level width
tWHCS CS0
Chip select transfer mode
tsys + 200
ns
SCK0 cycle time
tKCY
Input mode
2tsys + 200
ns
SCK0
16000/fc
ns
SCK0
High, Low level width
tKH
tKL
Input mode
tsys + 100
ns
SCK0
Output mode
8000/fc–50
ns
SI0 input set-up time
(for SCK0 ↑)
tSIK
SCK0 input mode
100
ns
SI0
SCK0 output mode
200
ns
SI0 input hold time
(for SCK0 ↑)
tKSI
tsys + 200
ns
SI0
100
ns
SCK0 ↓ → SO0
delay time
tKSO
SO0
Output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode
tsys + 200
ns
100
ns
Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selection) of the
control clock register (CLC: 00FEH).
tsys (ns)=2000/fc (upper two bits="00"), 4000/fc (upper two bits="01"), 16000/fc (upper two bits="11")
Note 2) The load condition for the SCK0 output mode, SO0 output delay time is 50pF + 1TTL.
– 15 –
CXP828P60
Fig. 4. Serial transfer CH0 timing
tWHCS
CS0
0.8VDD
0.2VDD
tKCY
tDCSK
tKL
tDCSKF
tKH
0.8VDD
0.8VDD
SCK0
0.2VDD
tSIK
tKSI
0.8VDD
SI0
Input data
0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD
SO0
Output data
0.2VDD
– 16 –
CXP828P60
Serial transfer (CH1)
Item
(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Symbol
Pin
tKCY
SCK1
SCK1
High, Low level width
tKH
tKL
SCK1
SI1 input set-up time
(for SCK1 ↑)
tSIK
SI1
SI1 input hold time
(for SCK1 ↑)
tKSI
SI1
SCK1 ↓ → SO1 delay time
tKSO
SO1
SCK1 cycle time
Condition
Min.
Max.
Input mode
1000
ns
Ouput mode
16000/fc
ns
Input mode
400
ns
Ouput mode
8000/fc–50
ns
SCK1 input mode
100
ns
SCK1 ouput mode
200
ns
SCK1 input mode
200
ns
SCK1 ouput mode
100
ns
SCK1 input mode
200
ns
SCK1 ouput mode
100
ns
Note) The load condition for the SCK1 output mode, SO1 output delay time is 50pF + 1TTL.
Fig. 5. Serial transfer CH1 timing
tKCY
tKL
tKH
0.8VDD
SCK1
0.2VDD
tSIK
tKSI
0.8VDD
Input data
SI1
Unit
0.2VDD
tKSO
0.8VDD
SO1
Output data
0.2VDD
– 17 –
CXP828P60
(3) A/D converter characteristics
(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, AVREF = 4.0 to VDD, Vss = AVSS = 0V reference)
Item
Symbol
Pin
Condition
Max.
Unit
Resolution
8
Bits
Linearity error
±3
LSB
Ta = 25°C
VDD = AVREF = 5.0V
VSS = AVSS = 0V
Zero transition
voltage
VZT∗1
Full-scale
transition voltage
VFT∗2
Conversion time
Sampling time
tCONV
tSAMP
Reference input voltage
VREF
AVREF
Analog input voltage
VIAN
AN0 to AN7
Typ.
–50
10
70
mV
4910
4970
5030
mV
160/fADC∗3
12/fADC∗3
IREF
AVREF current
Min.
µs
µs
VDD – 0.5
VDD
V
0
AVREF
V
1.0
mA
10
µA
0.6
Operation mode
SLEEP mode
STOP mode
32kHz operation mode
AVREF
IREFS
Fig. 6. Definition of A/D converter terms
Digital conversion value
FFH
FEH
∗1) VZT: Value at which the digital transfer value changes
from 00H to 01H and vice versa.
∗2) VFT: Value at which the digital transfer value changes
from FEH to FFH and vice versa.
∗3) fADC indicates the below values due to the contents of
bit 6 (CKS) of the A/D control register (ADC: 00F9H)
and bits 7 (PCK1) and 6 (PCK0) of the clock control
register (CLC: 00FEH).
Linearity error
01H
00H
CKS
VFT
VZT
Analog input
PCK1, PCK0
0 (φ/2 selection)
1 (φ selection)
00 (φ = fEX/2)
fADC = fC/2
fADC = fC
01 (φ = fEX/4)
fADC = fC/4
fADC = fC/2
11 (φ = fEX/16)
fADC = fC/16
fADC = fC/8
– 18 –
CXP828P60
(4) Interruption, reset input
Item
(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Symbol
Pin
Condition
External interruption
High, Low level width
tIH
tIL
INT0
INT1
INT2
NMI/INT3
Reset input Low level width
tRSL
RST
Min.
Max.
Unit
1
µs
32/fc
µs
Fig. 7. Interruption input timing
tIH
tIL
0.8VDD
INT0
INT1
INT2
NMI/INT3
(NMI specifies only for the
falling edge)
0.2VDD
tIL
tIH
Fig. 8. RST input timing
tRSL
RST
0.2VDD
– 19 –
CXP828P60
Appendix
Fig. 9. Recommended oscillation circuit
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
EXTAL
EXTAL
XTAL
Rd
C1
AAAA
AAAA
AAAA
(ii) Main clock
(i) Main clock
(iii) Sub clock
EXTAL
TEX
XTAL
Rd
XTAL
TX
Rd
C2
C1
C2
C1 C2
Manufacturer
MURATA
MFG
CO., LTD.
Model
fc (MHz)
CSA4.19MG
4.19
CSA8.00MTZ
8.00
CSA10.0MTZ
10.00
CST4.19MGW∗
CST8.00MTW∗
CST10.0MTW∗
RIVER
ELETEC
CO., LTD
C2 (pF)
Rd (Ω)
Circuit
example
(i)
30
30
0
4.19
8.00
(ii)
10.00
4.19
HC-49/U03
8.00
12
12
0
10.00
(i)
4.19
HC-49/U (-S)
KINSEKI
LTD.
C1 (pF)
P3
27
8.00
27
0
10.00
20
20
32.768kHz
50
22
1M
(iii)
Models marked with an asterisk (∗) have the built-in ground capacitance (C1, C2).
Mask option table
Product
Option item
Mask product
CXP82832 CXP82840 CXP82852 CXP82860
Package
ROM capacitance
Reset pull-up resistance
High voltage drive pin
pull-down resister
PROM version
CXP828P60Q-1-
80-pin plasitc QFP
80-pin plasitc QFP
32K bytes 40K bytes 52K bytes 60K bytes
PROM 60K bytes
Existent/Non-existent
Existent
Existent/Non-existent
Non-existent
(PD7/A24 to PD0/A55)
Existent
(G0/A0 to A23)
– 20 –
CXP828P60
Characteristics Curve
IDD vs. VDD
IDD vs. fc
(fc = 10MHz, Ta = 25°C, Typical)
(VDD = 5V, Ta = 25°C, Typical)
1/2 dividing mode
1/4 dividing mode
20.0
20
10.0
1/16 dividing mode
SLEEP mode
1.0
0.5
32kHz mode
(instruction)
0.1
(100µA)
0.05
(50µA)
IDD – Supply current [mA]
IDD – Supply current [mA]
5.0
1/2 dividing mode
15
1/4 dividing mode
10
5
32kHz
SLEEP mode
1/16 dividing mode
SLEEP mode
0.01
(10µA)
2
3
4
5
6
7
0
VDD – Supply voltage [V]
– 21 –
5
10
fc – System clock [MHz]
15
CXP828P60
Package Outline
Unit : mm
100PIN QFP (PLASTIC)
23.9 ± 0.4
+ 0.4
20.0 – 0.1
+ 0.1
0.15 – 0.05
80
51
+ 0.4
14.0 – 0.1
17.9 ± 0.4
15.8 ± 0.4
50
81
A
31
100
1
0.65
30
+ 0.15
0.3 – 0.1
0.13
+ 0.2
0.1 – 0.05
+ 0.35
2.75 – 0.15
M
0° to 10°
DETAIL A
0.8 ± 0.2
(16.3)
0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP-100P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
QFP100-P-1420
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
1.7g
JEDEC CODE
– 22 –