CXP822P24
CMOS 8-bit Single Chip Microcomputer
Description
The CXP822P24 is a CMOS 8-bit single chip
microcomputer integrating on a single chip an A/D
converter, serial interface, timer/counter, time base
timer, capture timer counter, fluorescent display tube
controller/driver, remote control reception circuit, CTL
duty detection circuit, 14-bit PWM output and highspeed output circuit besides the basic configurations
of 8-bit CPU, PROM, RAM, and I/O port.
The CXP822P24 also provides sleep/stop function
that enables lower power consumption.
CXP822P24 is the PROM-incorporated version of
the CXP82224 with built-in mask ROM. This provides
the additional feature of being able to write directly into
the program. Thus, it is most suitable for evaluation
use during system development and for smallquantity producton.
100 pin QFP (Plastic)
Structure
Silicon gate CMOS IC
Features
• Wide-range instruction system (213 instructions) to cover various types of data.
— 16-bit arithmetic/multiplication and division/Boolean bit operation instructions
• Minimum instruction cycle
400ns at 10MHz operation
122µs at 32kHz operation
• Incorporated PROM capacity 24K bytes
• Incorporated RAM capacity
704 bytes (including fluorescent display area)
• Peripheral functions
— A/D converter
8-bit, 8-channel, successive approximation method
(Conversion time of 32µs/10MHz)
— Serial interface
SIO with 8-bit, 8-stage FIFO incorporated for data use
(Auto transfer for 1 to 8 bytes), 1 channel
8-bit standard SIO, 1 channel
— Timer
8-bit timer, 8-bit timer/counter, 19-bit time base timer
16-bit capture timer/counter, 32kHz timer/counter
— Fluorescent display tube controller/driver Maximum of 384 segment display possible
1 to 16-digit dynamic display
Dimmer function
High voltage drive output (40V)
Incorporated pull-down resistor
Hardware key scan function
Maximum of 16 × 8 key matrix compatible
— Remote control reception circuit
Incorporated noise elimination circuit
Incorporated 8-bit, 6-stage FIFO for measurement data
— PWM output circuit
14 bits, 1 channel
— CTL duty detection circuit
— High-speed output circuit
Precision of 800ns at 10MHz, 4 outputs.
• Interruption
19 factors, 15 vectors, multi-interruption possible
• Standby mode
Sleep/stop
• Package
100-pin plastic QFP
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E93242A78-PS
–2–
PE7/TO
PB0/CINT
PE1/EC1
16 BIT CAPTURE
TIMER/COUNTER 2
8 BIT TIMER 1
8 BIT TIMER/COUNTER 0
PE0/EC0
FIFO
SERIAL INTERFACE UNIT 1
SERIAL
INTERFACE
UNIT 0
PB1/CSO
PB3/SI0
PB4/SO0
PB2/SCK0
FIFO
PB6/SI1
PB7/SO1
PB5/SCK1
REMOCON
PE4/RMC
CTL DUTY DET
RAM
80 BYTES
PE5/CTL
PE7/DDO
FDP CONTROLLER/
DRIVER
A/D CONVERTER
AVSS
14 BIT PWM GENERATOR
24
8
8
8
2
2
PE0/EC0/INT0
PE1/EC1/INT1
PE2/INT2
2 2 2
INTERRUPT CONTROLLER
AVREF
PE6/PWM
T0 to T7
T8/S31 to
T15/S24
PD0/S0 to
PI7/S23
VFDP
PA0/AN0 to
PA7/AN7
2
CH0
4
CH1
REALTIME
PULSE
GENERATOR
PRESCALER/
TIME BASE TIMER
PROM
24K BYTES
SPC700
CPU CORE
PG0/RTO0
to
PG3/RTO3
Block Diagram
TEX
TX
EXTAL
XTAL
RST
VDD
VSS
32kHz
TIMER/COUNTER
RAM
704 BYTES
CLOCK GEN./
SYSTEM CONTROL
PF0 to PF7
PG0 to PG7
PH0 to PH7
8
8
8
PI0 to PI7
PE6 to PE7
8
PE0 to PE5
2
PD0 to PD7
PC0 to PC7
PB0 to PB7
PA0 to PA7
6
8
8
8
8
CXP822P24
PORT I PORT H PORT G PORT F PORT E PORT D PORT C PORT B PORT A
PE3/INT3/NMI
CXP822P24
T5
T6
T4
T3
T2
T1
VFDP
T0
VDD
Vpp
VSS
PG0/RTO0
PG1/RTO1
PG2/RTO2
PG3/RTO3
PG4
PG5
PG7
PG6
PE0/EC0/INT0
Pin Assignment (Top View)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
PE1/EC1/INT1
1
PE2/INT2
80
T7
2
79
T8/S31
PE3/INT3/NMI
3
78
T9/S30
PE4/RMC
4
77
T10/S29
PE5/CTL
5
76
T11/S28
PE6/PWM
6
75
T12/S27
PE7/TO/DDO/ADJ
7
74
T13/S26
PB0/CINT
8
73
T14/S25
PB1/CS0
9
72
T15/S24
PB2/SCK0
10
71
P17/S23
PB3/SI0
11
70
P16/S22
PB4/SO0
12
69
P15/S21
PB5/SCK1
13
68
P14/S20
PB6/SI1
14
67
P13/S19
PB7/SO1
15
66
P12/S18
PC0/KR0
16
65
P11/S17
PC1/KR1
17
64
P10/S16
PC2/KR2
18
63
PF7/S15
PC3/KR3
19
62
PF6/S14
PC4/KR4
20
61
PF5/S13
PC5/KR5
21
60
PF4/S12
PC6/KR6
22
59
PF3/S11
PC7/KR7
23
58
PF2/S10
PH0
24
57
PF1/S9
PH1
25
56
PF0/S8
PH2
26
55
PD7/S7
PH3
27
54
PD6/S6
PH4
28
53
PD5/S5
PH5
29
52
PD4/S4
PH6
30
51
PD3/S3
Note) Vpp (Pin 90) must be connected to VDD.
–3–
PD1/S1
PD2/S2
AVSS
PD0/S0
AVREF
PA7/AN7
TEX
PA6/AN6
TX
VSS
XTAL
RST
EXTAL
PA5/AN5
PA4/AN4
PA3/AN3
PA2/AN2
PA0/AN0
PA1/AN1
PH7
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
CXP822P24
Pin Description
Symbol
I/O
PA0/AN0
to
PA7/AN7
I/O/
Analog input
PB0/CINT
I/O/Input
PB1/CS0
I/O/Input
Functions
(Port A)
8-bit I/O port. I/O can be
set in a unit of single bit .
(8 pins)
Analog inputs to A/D converter.
(8 pins)
Capture input to 16-bit timer/counter.
Chip select input for serial interface (CH0).
(Port B)
8-bit I/O port. I/O for lower
7bits can be set in a unit
of single bits. Uppermost
bit (PB7) is for output only.
(8 pins)
Serial clock I/O (CH0).
PB2/SCK0
I/O/I/O
PB3/SI0
I/O/Input
PB4/SO0
I/O/Output
PB5/SCK1
I/O/I/O
PB6/SI1
I/O/Input
Serial data input (CH1).
PB7/SO1
Output/Output
Serial data output (CH1).
PC0/KR0
to
PC7/KR7
PD0/S0
to
PD7/S7
Serial data input (CH0).
Serial data output (CH0).
Serial clock I/O (CH1).
I/O/Input
(Port C)
8-bit I/O port. I/O can be
set in a unit of single bits.
Capable of driving 12mA
sync current.
Serves as key return inputs when operating
key scan with FDP segment signal.
Output/Output
(Port D)
8-bit output port.
(8 pins)
FDP segment signal outputs.
PE0/INT0/EC0 Input/Input/Input
PE1/INT1/EC1 Input/Input/Input
Inputs for
external
interruption
request.
(4 pins)
External event inputs for
timer/counter.
(2 pins)
PE2/INT2
Input/Input
PE3/INT3/NMI
Input/Input/Input
PE4/RMC
Input/Input
PE5/CTL
Input/Input
PE6/PWM
Output/Output
14-bit PWM output.
PE7/TO/DDO/
ADJ
Output/Output/
Output/Output
Output for the 16-bit timer/counter
rectangular waves, CTU duty detection,
and 32kHz oscillation frequuency
demultiplication.
PF0/S8
to
PF7/S15
Output/Output
PG0/PTO0
to
PG3/RTO3
I/O/Output
PG4 to PG7
I/O
(Port E)
8-bit port. Lower 6 bits are
for inputs; upper 2 bits are
for outputs.
(8 pins)
(Port F)
8-bit output port.
(8 pins)
(Port G)
8-bit I/O port. I/O can be
set in a unit of single bits.
Data for the lower 4 bits
are gated with the contents
of RTO or OR-gate output.
(8 pins)
–4–
Non-maskable
interruption request input.
Remote control reception circuit input.
Input for CTL duty direction circuit.
FDP segment signal
outputs.
Outputs for real-time pulse generator (RTG).
Functions as high-precision, real-time pulse
output port.
(4 pins)
CXP822P24
Symbol
I/O
Functions
PH0 to PH7
I/O
(Port H)
8-bit I/O port. I/O can be set in a unit of single bits.
(8 pins)
PI0/S16
to
PI7/S23
Output/Output
(Port I)
8-bit output ports.
(8 bits)
T8/S31
to
T15/S24
Output/Output
Outputs for FDP timing (digit) signals/sagment signals.
T0 to T7
Output
FDP timing signal outputs.
VFDP
FDP segment signal outputs.
FDP voltage supply when incorporated resistor is set by mask option.
EXTAL
Input
XTAL
Output
TEX
Input
TX
Output
Crystal connectors for 32kHz timer/counter clock oscillation. Set 32kHz
crystal oscillator between TEX and TX. For usage as event input, attach
clock source to TEX, and open TX.
RST
Input
Low-level active, system reset.
AVREF
Input
Reference voltage input for A/D converter.
Crystal connectors for system clock oscillation. When the clock is supplied
externally, input to EXTAL; opposite phase clock should be input to XTAL.
AVSS
A/D converter GND.
VDD
Vcc supply.
Vpp
Vcc supply for incorporated PROM writing.
Connect to VDD during normal operation.
VSS
GND.
–5–
CXP822P24
Input/Output Circuit Formats for Pins
When reset
Circuit format
Pin
Port A
Port A data
PA0/AN0
to
PA7/AN7
Port A direction
IP
Input protection circuit
"0" when reset
Hi-Z
Data bus
RD (Port A)
Port A input selection
"0" when reset
Input multiplexer
A/D converter
8 pins
Port B
Port B data
PB0/CINT
PB1/CS0
PB3/SI0
PB6/SI1
Port B direction
IP
"0" when reset
Hi-Z
Schmitt input
Data bus
RD (Port B)
CINT
CS0
SI0
SI1
4 pins
Port B
SCK out
Output enable
Port B output selection
"0" when reset
Port B data
PB2/SCK0
PB5/SCK1
IP
Hi-Z
Port B direction
"0" when reset
Data bus
Schmitt input
RD (Port B)
2 pins
SCK in
–6–
CXP822P24
Circuit format
Pin
When reset
Port B
SO
Output enable
Port B output selection
"0" when reset
PB4/SO0
Port B data
IP
Hi-Z
Port B direction
"0" when reset
Data bus
1 pin
RD (Port B)
Port B
Internal reset signal
SO
Output enable
PB7/SO1
Port B output selection
∗
"1" when reset
High level
Port B data
"1" when reset
Data bus
1 pin
∗ Pull-up transistor approx.
200kΩ
RD (Port B)
Port C
Port C data
PC0/KR0
to
PC7/KR7
∗
Port C direction
IP
"0" when reset
Hi-Z
Data bus
RD (Port C)
Key input signal
∗ High current drive of 12mA possible
8 pins
PE0/EC0/INT0
PE1/EC1/INT1
PE2/INT2
PE3/INT3/NMI
PE4/RMC
PE5/CTL
Port E
EC0/INT0
EC1/INT1
INT2
INT3/NMI
RMC
CTL
Schmitt input
IP
Data bus
6 pins
RD (Port E)
–7–
Hi-Z
CXP822P24
Circuit format
Pin
When reset
Port E
PWM
Port E output selection
PE6/PWM
"0" when reset
Port E data
High level
"1" when reset
Data bus
RD (Port E)
1 pin
Port E
Output enable
TO
DDO
∗
ADJ16K
∗
ADJ2K
PE7/TO/
DDO/ADJ
0
1
MPX
2
3
Port E output selection
Port E output selection
High level
"00" when reset
Port E output selection
"0" when reset
Port E data
"1" when reset
Data bus
1 pin
∗ ADJ signal is a frequency demultiplication
output for 32kHz oscillation frequency
adjustment.
ADJ2 can be used for buzzer output.
RD (Port E)
Port G
RTO data
"0" when reset
Port G data
PG0/RTO0
to
PG3/RTO3
Hi-Z
Port G direction
IP
"0" when reset
Data bus
4 pins
RD (Port G)
–8–
CXP822P24
Pin
Circuit format
When reset
Port G
Port H
Port G or Port H data
PG4 to PG7
PH0 to PH7
Port G or Port H
direction
Hi-Z
IP
"0" when reset
Data bus
RD (Port G or Port H)
12 pins
PD0/S0
to
PD7/S7
Port D
Port F
Port I
PF0/S8
to
PF7/S15
∗ High voltage drive transistor
Segment output data
∗
Output selection control signal
("0" when reset)
Port D, F, or I data
PI0/S16
to
PI7/S23
24 pins
Pull-down
OP
resistor
"0" when reset
Mask option
Data bus
Hi-Z or Low
level
(when PD
resistance is
added)
VFDP
RD (Port D, F, or I)
∗ High voltage drive transistor
T15/S24
to
T8/S31
Segment output data
∗
Output selection control signal
("0" when reset)
Pull-down
OP Mask option
resistor
T0 to T7
Hi-Z or Low
level
(when PD
resistance is
added)
VFDP
16 pins
∗ Diagram shows circuit
EXTAL
XTAL
composition during
oscillation.
EXTAL
IP
IP
∗ Feedback resistor is
removed during stop.
2 pins
XTAL
–9–
Oscillation
CXP822P24
Pin
When reset
Circuit format
∗ Diagram shows circuit
TEX
TX
TEX
IP
IP
composition during
oscillation.
∗ When the operation of the oscillation
Oscillation
circuit is stopped by the software,
the feedback resistor is removed,
and TEX and TX become "Low" level
and "High" level respectively.
TX
2 pins
Pull-up resistor
RST
OP
Low level
Mask option
IP
Schmitt input
1 pin
– 10 –
CXP822P24
Absolute Maximum Ratings
Item
(Vss = 0V reference)
Rating
Unit
VDD
–0.3 to +7.0
V
Vpp
–0.3 to +13.0
V
AVSS
V
VIN
–0.3 to +0.3
–0.3 to +7.0∗1
Output voltage
VOUT
–0.3 to +7.0∗1
V
Display output voltage
VOD
VDD – 40 to
VDD + 0.3
V
IOH
–5
mA
IODH1
–15
mA
Display outputs S0 to S23 (value per pin)
IODH2
–35
mA
Display outputs T0 to T7, and T8/S31 to
T15/S24 (value per pin)
∑IOH
–40
mA
Total for all pins excluding display outputs
∑IODH
–100
mA
Total for all display outputs
IOL
15
mA
Port 1
IOLC
20
mA
High current Port 1 ∗3
Low level total output current
∑IOL
100
mA
Total for all output pins
Operating temperature
Topr
–10 to +75
°C
Storage temperature
Tstg
–55 to +150
°C
Allowable power dissipation
PD
600
mW
Supply voltage
Input voltage
High level output current
High level total output current
Low level output current
Symbol
Remarks
Incorporated PROM
V
As P channel transistor is open drain,
VDD is reference.
All pins excluding display outputs∗2
(value per pin)
∗1 VIN and VOUT must not exceed VDD + 0.3V.
∗2 Specifies output current of general-purpose l/O ports.
∗3 The high current drive transistor is the N-CH transistor of Port C (PC).
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
be conducted under the recommended operating conditions. Exceeding these conditions may adversely
affect the reliability of the LSl.
– 11 –
CXP822P24
Recommended Operating Conditions
Item
Symbol
VDD
(Vss = 0V reference)
Min.
Max.
Unit
4.5
5.5
3.5
5.5
2.7
5.5
Guaranteed operation range with TEX clock
2.5
5.5
V
Guaranteed data hold range during STOP
∗4
∗1
High-speed mode
Guaranteed operation range
V
Supply voltage
Vpp = VDD
Vpp
High level input voltage
VIH
0.7VDD
VDD
V
VIHS
0.8VDD
VDD
V
VIHEX
Low level input voltage
Operating temperature
∗1
∗2
∗3
∗4
VDD – 0.4 VDD + 0.3
Remarks
Low-speed mode
Guaranteed operation range
V
Hysteresis input∗2
EXTAL∗3
∗1
VIL
0
0.3VDD
V
VILS
0
0.2VDD
V
VILEX
–0.3
0.4
V
Topr
–10
+75
°C
Hysteresis input∗2
EXTAL∗3
Value for each pin of normal input ports (PA, PB3, PB4, PB6, PC, PG, PH).
Value of the following pins: RST, CINT, CS0, SCK0, SCK1, EC0/INT0, EC1/INT1 , INT2, INT3/MTI, RMC, CTL.
Specifies only during external clock input.
Vpp and VDD should be set to the same voltage.
– 12 –
CXP822P24
Electrical Characteristics
DC Characteristics
Item
High level
output voltage
Low level
output voltage
(Ta = –10 to +75°C, Vss = 0V reference)
Symbol
Pins
VOH
PA, PB, PC,PE6,
PE7, PG, PH
VOL
PC
IIHE
EXTAL
IILE
Input current
IIHT
TEX
IILT
IILR
Display output
current
RST
S0 to S23
IOH
S24/T15 to S31/T8
T0 to T7
Conditions
VDD = 4.5V, IOH = –0.5mA
4.0
V
VDD = 4.5V, IOH = –1.2mA
3.5
V
VDD = 4.5V, IOL = 1.8mA
0.4
V
VDD = 4.5V, IOL = 3.6mA
0.6
V
VDD = 4.5V, IOL = 12.0mA
1.5
V
µA
VDD = 5.5V, VIH = 5.5V
0.5
40
VDD = 5.5V, VIL = 0.4V
–0.5
–40 µA
VDD = 5.5V, VIH = 5.5V
0.1
10
VDD = 5.5V,
VIL = 0.4V
–0.1
–10 µA
–1.5
–400 µA
VDD = 4.5V,
VOH = VDD – 2.5V
Open drain output
leakage current
ILOL
(P-CH Tr in off state)
S24/T15 to S31/T8
T0 to T7
VDD = 5.5V
VOL = VDD – 35V
VFDP = VDD – 35V
Pull-down
resistance
RL
S24/T15 to S31/T8
T0 to T7
VDD = 5V
VFDP = VDD – 35V
I/O leakage current IIZ
PA to PC, PE, PG,
PH
VDD = 5.5V
VI = 0, 5.5V
VDD = 5.5V, 10MHz crystal
oscillation (C1 = C2 = 15pF)
VDD = 3V, 32kHz crystal
oscillation (C1 = C2 = 47pF)
IDD2
Input capacity
IDDS1
VDD
–8
mA
–20
mA
–20 µA
60
100 270 kΩ
±10 µA
VDD = 5.5V, 10MHz crystal
oscillation (C1 = C2 = 15pF)
VDD = 3V, 32kHz crystal
oscillation (C1 = C2 = 47pF)
IDDS3
Stop mode
VDD = 5.5V, Termination of 10MHz
and 32kHz crystal oscillation
Pins other than
S0 to S31, T0 to
T7, PB7, PE6,
AVREF, AVSS,
VFDP, VDD, VSS
20
40 mA
400 1000 µA
Sleep mode
IDDS2
CIN
µA
High-speed mode operation
(1/2 frequency demultiplier clock)
IDD1
Power supply
current∗
Min. Typ. Max. Unit
Clock 1MHz
0V for all pins excluding measured
pins
∗ When all pins are open.
– 13 –
1.2
8
mA
9
30
µA
30
µA
20
pF
10
CXP822P24
AC Characteristics
(1) Clock timing
(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
Pin
Conditions
Min.
System clock frequency
fC
XTAL
Fig. 1, Fig. 2
EXTAL
System clock input pulse width
tXL
tXH
Fig. 1, Fig. 2
EXTAL External clock drive
Fig. 1, Fig. 2
EXTAL External clock drive
Event count input clock
rise time, fall time
tCR
tCF
tEH
tEL
tER
tEF
System clock frequency
fC
System clock input rise time,
fall time
Event count input clock
pulse width
tTL
tTH
tTR
tTF
Event count input pulse width
Event count input rise time,
fall time
∗1
Typ.
1
Max.
Unit
10
MHz
ns
37.5
200
tsys + 50∗1
EC0,
EC1
Fig. 3
EC0,
EC1
Fig. 3
TEX
TX
VDD = 2.7 to 5.5V
Fig. 2 (32kHz clock
application condition)
TEX
Fig. 3
TEX
Fig. 3
ns
ns
20
ms
kHz
32.768
µs
10
20
ms
tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock
control register (address: 00FEH).
tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")
Fig. 1. Clock timing
1/fc
VDD – 0.4V
EXTAL
0.4V
tXH
tCF
tXL
tCR
Fig. 2. Clock applied conditions
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA AAAA AAAA
Crystal oscillation
Ceramic oscillation
EXTAL
C1
XTAL
C2
External clock
EXTAL
32kHz clock applied condition
crystal oscillation
TEX
XTAL
74HC04
– 14 –
C1
TX
C2
CXP822P24
Fig. 3. Event count clock timing
0.8VDD
TEX
EC0
EC1
0.2VDD
tEH
tEF
tEL
tER
tTH
tTF
tTL
tTR
(2) Serial transfer (CH0)
Item
(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss=0V reference)
Symbol
Condition
Pin
Min.
Max.
Unit
CS0 ↓ → SCK0
delay time
tDCSK
SCK0
Chip select transfer mode
(SCK0 = output mode)
tsys + 200
ns
CS0 ↑ → SCK0
float delay time
tDCSKF SCK0
Chip select transfer mode
(SCK0 = output mode)
tsys + 200
ns
CS0 ↓ → SO0
delay time
tDCSO
SO0
Chip select transfer mode
tsys + 200
ns
CS0 ↑ → SO0
float delay time
tDCSOF SO0
Chip select transfer mode
tsys + 200
ns
CS0
High level width
tWHCS CS0
Chip select transfer mode
tsys + 200
ns
SCK0
cycle time
tKCY
Input mode
2tsys + 200
ns
SCK0
16000/fc
ns
SCK0
High, Low level width
tKH
tKL
Input mode
tsys + 100
ns
SCK0
Output mode
8000/fc – 50
ns
SI0 input set-up time
(for SCK0 ↑)
tSIK
SCK0 input mode
100
ns
SI0
SCK0 output mode
200
ns
SI0 input hold time
(for SCK0 ↑)
tKSI
tsys + 200
ns
SI0
100
ns
SCK0 ↓ → SO0
delay time
tKSO
SO0
Note 1)
Output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode
tsys + 200
ns
100
ns
tsys indicates the three values below according to the upper two bits (CPU clock selection) of the
clock control register (address: 00FEH).
tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits
= "11")
Note 2) The load condition for the SCK0 output mode, SO0 output delay time is 50pF + 1TTL.
– 15 –
CXP822P24
Fig. 4. Serial transfer CH0 timing
tWHCS
CS0
0.8VDD
0.2VDD
tKCY
tDCSK
tKL
tDCSKF
tKH
0.8VDD
0.8VDD
SCK0
0.2VDD
tSIK
tKSI
0.8VDD
Input
data
SI0
0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD
SO0
Output data
0.2VDD
– 16 –
CXP822P24
Serial transfer (CH1)
Item
SCK1 cycle time
(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Symbol
tKCY
Pin
Condition
Min.
Input mode
SCK1
tKH
tKL
SCK1
SI1 input set-up time
(for SCK1 ↑)
tSIK
SI1
SI1 input hold time
(for SCK1 ↑)
tKSI
ns
16000/fc
ns
400
ns
8000/fc – 50
ns
SCK1 input mode
100
ns
SCK1 output mode
200
ns
SCK1 input mode
200
ns
SCK1 output mode
100
ns
SCK1 ↓ → SO1
delay time
tKSO
Input mode
Output mode
SI1
SO1
SCK1 input mode
200
ns
SCK1 output mode
100
ns
Note) The load condition for the SCK1 output mode, SO1 output delay time is 50pF + 1TTL.
Fig. 5. Serial transfer CH1 timing
tKCY
tKL
tKH
SCK1
0.8VDD
0.2VDD
tSIK
tKSI
0.8VDD
SI1
Unit
1000
Output mode
SCK1 High, Low level width
Max.
Input data
0.2VDD
tKSO
0.8VDD
Output data
SO1
0.2VDD
– 17 –
CXP822P24
(3) A/D converter characteristics
(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVss = 0V reference)
Item
Symbol
Pin
Condition
Min.
Typ.
Resolution
Linearity error
Zero transition voltage
VZT∗1
Full-scale
transition voltage
VFT∗2
Conversion time
tCONV
tSAMP
Sampling time
Reference input voltage VREF
Analog input voltage
VIAN
Ta = 25°C
VDD = AVDD = 5.0V
VDD = AVss = 0V
IREFS
Unit
8
Bits
±3
LSB
–10
70
150
mV
4930
5050
5120
mV
160/fADC ∗3
12/fADC ∗3
AVREF
AN0 to AN7
Operation mode
IREF
AVREF current
Max.
AVREF
Sleep mode
Stop mode
32kHz operation mode
µs
µs
VDD – 0.5
VDD
V
0
AVREF
V
1.0
mA
10
µA
0.6
Fig. 6. Definitions of A/D converter terms
FFH
FEH
Digital conversion value
∗1 VZT : Value at which the digital conversion value
changes from 00H to 01H and vice versa.
∗2 VFT : Value at which the digital conversion value
changes from FEH to FFH and vice versa.
∗3 fADC indicates the below values due to ADC operation
clock selection (ADCS: Bit 6 of address 00F9H).
During PS2 selection, fADC = fc/2
During PS1 selection, fADC = fc
Linearity error
01H
00H
VZT
VFT
Analog input
– 18 –
CXP822P24
(4) Interruption, reset input
Item
(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Symbol
Pin
External interruption
High, Low level width
tIH
tIL
INT0
INT1
INT2
NMI/INT3
Reset input Low level width
tRSL
RST
Condition
Min.
Max.
Unit
1
µs
8/fc
µs
Fig. 7. Interruption input timing
tIH
tIL
0.8VDD
INT0
INT1
INT2
NMI/INT3
(NMI specifies only for
the falling edge)
0.2VDD
tIL
tIH
Fig. 8. RST input timing
tRSL
RST
0.2VDD
(5) Others
(Ta = –10 to +75°C, VDD = 4.5 to 5.0V, VSS = 0V reference)
Item
CLK input
High, Low level width
Symbol
tCTH
tCTL
Pin
CTL
Condition
Min.
tsys = 2000/fc
tsys + 200
Fig. 9. Other timing
tCTH
tCTL
0.8VDD
CTL
0.2VDD
– 19 –
Max.
Unit
ns
CXP822P24
Appendix
Fig. 10. Recommended oscillation circuit
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA AAAAA
(i) Main clock
EXTAL
AAAA
AAAA
AAAA
(ii) Main clock
EXTAL
XTAL
TEX
XTAL
Rd
C1
(iii) Sub clock
Rd
Rd
C2
MURATA MFG
CO., LTD
Model
fc (MHz)
CSA4.19MG
4.19
CSA8.00MTZ
8.00
CSA10.0MTZ
10.00
CST4.19MGW∗
CST8.00MTW∗
C2
C1
C2
C1
Manufacturer
TX
C1 (pF)
C2 (pF)
Rd (Ω)
Circuit
example
(i)
30
4.19
30
0
(ii)
8.00
CST10.0MTW∗
10.00
4.19
RIVER
ELETEC
HC-49/U03
CORPORATION
8.00
15
15
0
10.00
(i)
4.19
HC-49/U (-S)
8.00
KINSEKI LTD.
27
27
0
30
39
330k
10.00
P3
32.768kHz
(iii)
Those marked with an asterisk (∗) signify types with built-in ground capacitance (C1, C2).
Selection Guide
Optional item
Mask product
CXP822P24Q-1-
Package
100-pin plastic QFP
100-pin plastic QFP
ROM capacitance
20K bytes/24K bytes
PROM 24K bytes
Reset pin pull-up resistor
Existent/Non-existent
Existant
High voltage drive pin pull-up resistor
Existent/Non-existent
Non existent (S0/PD0 to S23/PF7)
Existent (T0 to T15/S24)
– 20 –
CXP822P24
Unit: mm
100PIN QFP (PLASTIC)
+ 0.4
14.0 – 0.01
17.9 ± 0.4
15.8 ± 0.4
+ 0.1
0.15 – 0.05
23.9 ± 0.4
+ 0.4
20.0 – 0.1
A
0.65
+ 0.35
2.75 – 0.15
±0.12 M
(16.3)
0.15
0° to 15°
DETAIL A
0.8 ± 0.2
Package Outline
PACKAGE STRUCTURE
SONY CODE
QFP-100P-L01
EIAJ CODE
∗QFP100-P-1420-A
JEDEC CODE
– 21 –
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
SOLDER PLATING
LEAD MATERIAL
COPPER / 42 ALLOY
PACKAGE WEIGHT
1.4g