CXP823P24 CMOS 8-bit Single Chip Microcomputer Description The CXP823P24 is a highly integrated CMOS 8-bit single-chip microcomputer which is mainly composed of an 8-bit CPU, PROM, RAM and I/O ports. This microcomputer features many other high-performance circuits in a single-chip CMOS design, including an A/D converter, serial interface, timer/counter, timebase timer, capture timer/counter, fluorescent display tube controller/driver, and remote control receiver. Also, the CXP823P24 provides the power-on reset function as well as the sleep/stop function which assures reduced power consumption. Being a PROM-incorporated version of the CXP82324 which has on-chip mask ROM, the CXP823P24 permits program writing. Therefore, it is ideally suited for use in system development stage evaluation and job lot production. 80 pin QFP (Plastic) Structure Silicon gate CMOS IC Features • Instruction set which supports a wide array of data types 213 types — 16-bit arithmetic instruction/multiplication and division instructions/boolean bit operation instruction • Minimum instruction cycle During operation 400ns/10MHz • Incorporated PROM capacity 24K bytes • Incorporated RAM capacity 704 bytes (Including fluorescent display data area) • Peripheral functions — A/D converter 8-bit, 8-channel, successive comparison type (conversion time: 32µs at 10MHz) — Serial interface 1 channel data interface with an 8-bit, 8-stage FIFO (1 to 8 byte automatic transfer) 1-channel, 8-bit clock synchronized interface — Timers 8-bit timer 8-bit timer/counter 19-bit time-base timer 16-bit capture timer/counter — Fluorescent display tube controller/driver Display of up to 336 segments 1 to 16 digit dynamic display Dimmer function High voltage tolerance output (40V) Built-in pull-down resistor — Remote control receiver Built-in noise suppressor circuit Built-in 8-bit pulse counter and 6-stage FIFO • Interrupts 14 factors, 15 vectors, multiple interrupt pocessing • Standby mode Sleep/stop • Package 80-pin plastic QFP Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E92Y35A78-PS –2– 8 8 21 T0 to T7 T8/S28 to T15/S21 S0 to S20 PE7/TO PB0/CINT PE1/INT1/EC1 PE0/INT0/EC0 PB6/SI1 PB7/SO1 PB5/SCK1 PB1/CS0 PB3/SI0 PB0/SO0 PB2/SCK0 PE4/RMC VFDP 8 FIFO FIFO RAM 80 BYTES 16 BIT CAPTURE TIMER/COUNTER 2 8 BIT TIMER 1 8 BIT TIMER/COUNTER 0 SERIAL INTERFACE UNIT 1 SERIAL INTERFACE UNIT 0 REMOCON FDP CONTROLLER/ DRIVER A/D CONVERTER 2 PE0/EC0/INT0 PE1/EC1/INT1 PE2/INT2 PE3/INT3 2 PRESCALER/ TIME BASE TIMER PROM 24K BYTES SPC700 CPU CORE INTERRUPT CONTROLLER EXTAL XTAL RST VDD Vpp VSS RAM 704 BYTES CLOCK GENERATOR/ SYSTEM CONTROL PB0 to PB6 7 PE0 to PE5 PE6 to PE7 PF0 to PF7 6 2 8 4 PG0 to PG3 PD0 to PD7 8 PC0 to PC7 PB7 PA0 to PA7 8 8 PORT E PA0/AN0 to PA7/AN7 PORT A PORT B PORT C PORT D PORT F PORT G Block Diagram CXP823P24 CXP823P24 T5 T4 T3 T2 T1 T0 VFDP VDD PG0 Vpp PG1 PG2 PG3 PE0/EC0/INT0 PE1/EC1/INT1 PE2/IN2 Pin Assignment (Top View) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 PE3/INT3 1 64 T6 PE4/RMC 2 63 T7 PE5 3 62 T8/S28 PE6 4 61 T9/S27 PE7/TO 5 60 T10/S26 PB0/CINT 6 59 T11/S25 PB1/CS0 7 58 T12/S24 PB2/SCK0 8 57 T13/S23 PB3/SI0 9 56 T14/S22 PB4/SO0 10 55 T15/S21 PB5/SCK1 11 54 S20 PB6/SI1 12 53 S19 PB7/SO1 13 52 S18 PC0/KR0 14 51 S17 PC1/KR1 15 50 S16 PC2/KR2 16 49 PF7/S15 PC3/KR3 17 48 PF6/S14 PC4/KR4 18 47 PF5/S13 PC5/KR5 19 46 PF4/S12 PC6/KR6 20 45 PF3/S11 PC7/KR7 21 44 PF2/S10 PA0/AN0 22 43 PF1/S9 PA1/AN1 23 42 PF0/S8 PA2/AN2 24 41 PD7/S7 Note) Vpp (Pin 73) is always connected to VDD. –3– PD6/S6 PD5/S5 PD4/S4 PD3/S3 PD2/S2 PD1/S1 VSS PD0/S0 XTAL EXTAL RST PA7/AN7 PA6/AN6 PA5/AN5 PA4/AN4 PA3/AN3 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 CXP823P24 Pin Description Symbol I/O Description (Port A) 8-bit port; single bit addressable. (8 pins) PA0/AN0 to PA7/AN7 I/O/Analog input PB0/CINT I/O/Input External capture input for 16-bit timer/counter. PB1/CS0 I/O/Input Chip select input for serial interface (CH0). PB2/SCK0 I/O/I/O PB3/SI0 I/O/Input PB4/SO0 I/O/Output PB5/SCK1 I/O/I/O PB6/SI1 I/O/Input Serial data (CH1) input. PB7/SO1 Output/Output Serial data (CH1) output. PC0/KR0 to PC7/KR7 I/O/Input (Port B) Single bit addressable from amongst lower 7 bits; highest bit (PB7) dedicated to output. (8 pins) (Port C) 8-bit port; single bit addressable. Can provide 12mA sink current. (8 pins) Analog input to A/D converter. (8 pins) Serial clock (CH0) input/output. Serial data (CH0) input. Serial data (CH0) output. Serial clock (CH1) input/output. Key return input for FDP segment signal which performs key scanning. PE0/INT0/EC0 Input/Input/Input PE1/INT1/EC1 Input/Input/Input Input for external interrupt requests. (4 pins) External event input to timer/counter. (2 pins) PE2/INT2 Input/Input PE3/INT3 Input/Input PE4/RMC Input/Input PE5 Input PE6 Output PE7/TO Output/Output PG0 to PG3 I/O (Port G) 4-bit input/output port; single bit addressable. (4 pins) PF0/S8 to PF7/S15 Output/Output (Port F) 8-bit dedicated output port. (8 pins) S16 to S20 Output Segment signal output for FDP. T8/S28 to T15/S21 Output/Output Dual purpose output for FDP timing and segment signals. T0 to T7 Output Timing signal output for FDP. PD0/S0 to PD7/S7 Output/Output (Port D) 8-bit dedicated output port. Segment signal output for FDP. (8 pins) (Port E) 8-bit port with lower 6 bits dedicated to input and upper 2 bits dedicated to output. (8 pins) Input for remote control receiving circuit. Output pin for 16-bit timer/counter rectangular waveform. –4– Segment signal output for FDP. CXP823P24 Symbol I/O VFDP Description Provides voltage for FDP. EXTAL Input XTAL Output RST I/O Connection for system clock oscillation crystal. When using an external clock, input normal signal to EXTAL and reverse phase signal to the XTAL pin. System reset, active "L". The RST pin is an input/output pin which outputs a "L" level from the on-chip power on reset circuit when the power is turned on. Vpp Positive power supply for the programmable on-chip PROM; connect to VDD for nomal operation. VDD Positive power supply pin. VSS GND –5– CXP823P24 Input/Output Circuit Formats for Pins When reset Circuit format Pin Port A Port A data PA0/AN0 to PA7/AN7 Port A direction Input protection circuit IP "0" when reset Hi-Z Data bus RD (Port A) Port A input select "0" when reset Input multiplexer A/D converter 8 pins Port B Port B data PB0/CINT PB1/CS0 PB3/SI0 PB6/SI1 Port B direction IP "0" when reset Hi-Z Schmitt input Data bus RD (Port B) CINT CS0 SI0 SI1 4 pins Port B SCK OUT Output enable Port B output select "0" when reset Port B data PB2/SCK0 PB5/SCK1 IP Hi-Z Port B direction "0" when reset Data bus Schmitt input RD (Port B) 2 pins SCK in –6– CXP823P24 Circuit format Pin When reset Port B SO Output enable Port B output select "0" when reset Port B data PB4/SO0 IP Hi-Z Port B direction "0" when reset Data bus RD (Port B) 1 pin Port B Internal reset signal SO Output enable Port B output select PB7/SO1 ∗ "0" when reset High level Port B data "1" when reset Data bus ∗Pull-up transistor approx. 200kΩ RD (Port B) 1 pin Port C Port C data PC0/KR0 to PC7/KR7 ∗ Port C direction IP "0" when reset Hi-Z Data bus RD (Port C) Key input signal 8 pins ∗Capable of driving 12mA large current Port E PE0/EC0/INT0 PE1/EC1/INT1 PE2/INT2 PE3/INT3 PE4/RMC EC0/INT0 EC1/INT1 INT2 INT3 RMC Schmitt input IP Data bus 5 pins RD (Port E) –7– Hi-Z CXP823P24 Circuit format Pin When reset Port E PE5 IP Data bus Hi-Z RD (Port E) 1 pin Port E PE6 High level Port E data "1" when reset 1 pin Port E TO Output enable (T2OE) Port E output select PE7/TO "0" when reset High level Port E data "1" when reset Data bus 1 pin RD (Port E) Port G Port G data PG0 to PG3 Port G direction IP "0" when reset Data bus RD (Port G) 4 pins –8– Hi-Z CXP823P24 Pin Circuit format Port D PD0/S0 to PD7/S7 Port F When reset ∗High voltage tolerance transistor Segment output data ∗ Output selection control signal ("0" when reset) Port D data or Port F data PF0/S8 to PF7/S15 OP "0" when reset Mask option Pull-down resistor Data bus Hi-Z or Low level (when pulldown resistor is connected) VFDP 16 pins RD (Port D or Port F) ∗High voltage tolerance transistor S16 to S20 T15/S21 to T8/S28 T0 to T7 Segment output data ∗ Output selection control signal ("0" when reset) OP Mask option Pull-down resistor Hi-Z or Low level (when pulldown resistor is connected) VFDP 21 pins ∗Diagram shows EXTAL XTAL circuit construction for oscillation. EXTAL IP IP ∗During stop feedback resistor is disconnected. Oscillation XTAL 2 pins Pull-up resistor RST OP Mask option IP 1 pin Schmitt input From power on reset circuit (Mask option) –9– Low level CXP823P24 Absolute Maximum Ratings Item Supply voltage (Vss = 0V) Symbol Rating Unit VDD –0.3 to +7.0 V Vpp V Remarks Input voltage VIN –0.3 to +13.0 –0.3 to +7.0∗1 Output voltage VOUT –0.3 to +7.0∗1 V Display output voltage VOD VDD – 40 to VDD + 0.3 V IOH –5 mA As P channel transistor is open drain, VDD voltage is determined as standerd. Other than display output pins∗2 : per pin IODH1 –15 mA Display outputs S0 to S20: per pin IODH2 –35 mA Display outputs T0 to T7, T8/S28 to T15/S21: per pin ∑IOH –40 mA Total of other than display output pins ∑IODH –100 mA Total of display output pins IOL 15 mA Port 1 pin IOLC 20 mA Large current port pin ∗3 Low level total output current ∑IOL 100 mA Entire pin total Operating temperature Topr –10 to +75 °C Storage temperature Tstg –55 to +150 °C Allowable power dissipation PD 600 mW High level output current High level total output current Low level output current Incorporated PROM V ∗1 VIN and VOUT cannot exceed VDD + 0.3V. ∗2 Rating for output current of general input/output port. ∗3 The large current drive transistor is an N-channel transistor of Port C. Note) If the absolute maximum ratings are exceeded, the LSI could reach permanent breakdown. Also, observing recommended operating conditions is desirable; otherwise, the LSI's reliability could be affected. – 10 – CXP823P24 Recommended Operating Conditions Item Symbol VDD Supply voltage Vpp High level input voltage (Vss = 0V) Min. Max. 4.5 5.5 3.5 5.5 2.5 5.5 Vpp = VDD Unit High-speed mode (1/2, 1/4 clock) guaranteed range during operation V V ∗1 0.7VDD VDD V VIHS 0.8VDD VDD V V Hysteresis input∗2 EXTAL pin∗3 ∗1 VIL 0 0.3VDD V VILS 0 0.2VDD V VILEX –0.3 0.4 V Operating temperature Topr –10 +75 °C Low level input voltage ∗1 ∗2 ∗3 ∗4 Low-speed mode (1/16 clock) guaranteed range during operation Guaranteed data hold operation range during stop ∗4 VIH VIHEX VDD – 0.4 VDD + 0.3 Remarks Hysteresis input EXTAL pin∗3 All regular input ports (PA, PB3, PB4, PB6, PC, PE5, PG). For pins RST, CINT, CS0, SCK0, SCK1, EC0/INT0, EC1/INT1, INT2, INT3, RMC. Rating only for external clock input. Vpp and VDD should be set to the same voltage. – 11 – CXP823P24 Electrical Characteristics DC Characteristics Item High level output voltage Low level output voltage (Ta = –10 to +75°C, Vss = 0V) Symbol VOH Pins PA, PB, PC, PE6, PE7, PG, RST (for VOL only) VOL PC IIHE Input current IILE IILR EXTAL RST Condition VDD = 4.5V, IOH = –0.5mA 4.0 V VDD = 4.5V, IOH = –1.2mA 3.5 V VDD = 4.5V, IOL = 1.8mA 0.4 V VDD = 4.5V, IOL = 3.6mA 0.6 V VDD = 4.5V, IOL = 12.0mA 1.5 V µA VDD = 5.5V, VIH = 5.5V 0.5 40 VDD = 5.5V, VIL = 0.4V –0.5 –40 µA VDD = 5.5V, VIL = 0.4V –1.5 –400 µA S0 to S20 VDD = 4.5V VOH = VDD – 2.5V Display output current IOH Open drain output leak current (P-CH Tr off state) ILOL S0 to S20 S21/T15 to S28/T8 T0 to T7 VDD = 5.5V VOL = VDD – 35V VFDP = VDD – 35V Pull-down resistor RL S0 to S20 S21/T15 to S28/T8 T0 to T7 VDD = 5V VOD – VFDP = 30V Input/output leak current IIZ PA to PC, PE, PG VDD = 5.5V VI = 0, 5.5V S21/T15 to S28/T8 T0 to T7 Min. Typ. Max. Unit –8 mA –20 mA –20 µA 60 100 270 kΩ ±10 µA VDD = 5.5V High-speed mode (1/2 clock) operation IDD1 Supply current∗ Input capacitance VDD 10MHz crystal oscillator (C1 = C2 = 15pF) IDDSL Sleep mode IDDST Stop mode CIN For pins other than S0 to S28, T0 to T7, PB7, PE6, PE7, VDD, VSS, VFDP 1MHz clock 0V other than the measured ∗ All output pins are left open. – 12 – 25 40 mA 3 8 mA 30 µA 20 pF 10 CXP823P24 AC Characteristics (1) Clock timing (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Item Symbol Pins Conditions Min. Max. Unit 10 MHz System clock frequency fC XTAL Fig. 1, Fig. 2 EXTAL 1 System clock input pulse width tXL, tXH Fig. 1, Fig. 2 EXTAL External clock driver 45 tCR, tCF tEH, tEL tER, tEF Fig. 1, Fig. 2 EXTAL External clock driver System clock input rising and falling times Event count input clock pulse width Event count input clock rising and falling times ∗1 EC0, EC1 Fig. 3 EC0, EC1 Fig. 3 ns 200 tsys + 50∗1 ns ns 20 ms tsys is determind by the upper two bits of the clock control resister (Address: 00FEH; CPU clock selected) resulting in one of the 3 following values: tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits= "11") Fig. 1. Clock timing 1/fc VDD – 0.4V EXTAL 0.4V tXH tCF tXL tCR Fig. 2. Clock applying condition AAAA AAAA AAAA AAAA AAAA AAAA Crystal oscillation Ceramic oscillation EXTAL External clock EXTAL XTAL C1 C2 XTAL 74HC04 Fig. 3. Event count clock timing 0.8VDD EC0 EC1 0.2VDD tEH tEF tEL tER tTH tTF tTL tTR – 13 – CXP823P24 (2) Serial transfer (CH0) Item (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Symbol Pin Condition Min. Max. Unit CS0 ↓ → SCK0 delay time tDCSK SCK0 Chip select transfer mode (SCK0 = output mode) tsys + 200 ns CS0 ↑ → SCK0 float delay time tDCSKF SCK0 Chip select transfer mode (SCK0 = output mode) tsys + 200 ns CS0 ↓ → SO0 delay time tDCSO SO0 Chip select transfer mode tsys + 200 ns CS0 ↑ → SO0 float delay time tDCSOF SO0 Chip select transfer mode tsys + 200 ns CS0 high level width tWHCS CS0 Chip select transfer mode SCK0 cycle time tKCY SCK0 SCK0 high and low level width tKH tKL SCK0 SI0 input setup time (against SCK0 ↑) tSIK SI0 SI0 input hold time (against SCK0 ↑) tKSI SI0 SCK0 ↓ → SO0 delay time tKSO SO0 tsys + 200 2tsys + 200 ns 16000/fc ns Input mode tsys + 100 ns Output mode 8000/fc – 50 ns SCK0 input mode 100 ns SCK0 output mode 200 ns tsys + 200 ns 100 ns Input mode Output mode SCK0 input mode SCK0 output mode SCK0 input mode SCK0 output mode ns tsys + 200 ns 100 ns tsys is determind by the upper two bits of the clock control resister (Address: 00FEH; CPU clock selected) resulting in one of the 3 following values: tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) The load of SCK0 output mode and SO0 output delay time is 50pF + 1TTL. Note 1) – 14 – CXP823P24 Fig. 4. Serial transfer CH0 timing tWHCS CS0 0.8VDD 0.2VDD tKCY tDCSK tKL tDCSKF tKH 0.8VDD 0.8VDD SCK0 0.2VDD tSIK tKSI 0.8VDD Input data SI0 0.2VDD tDCSO tKSO tDCSOF 0.8VDD SO0 Output data 0.2VDD – 15 – CXP823P24 Serial transfer (CH1) Item SCK1 cycle time (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Symbol tKCY Pin Condition SCK1 Min. Input mode tKH tKL SCK1 SI1 input setup time (against SCK1 ↑) tSIK SI1 SI1 input hold time (against SCK1 ↑) tKSI ns 16000/fc ns 400 ns 8000/fc – 50 ns SCK1 input mode 100 ns SCK1 output mode 200 ns SCK1 input mode 200 ns SCK1 output mode 100 ns SCK1 ↓ → SO1 delay time tKSO Input mode Output mode SI1 SO1 SCK1 input mode 200 ns SCK1 output mode 100 ns Note) The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL. Fig. 5. Serial transfer CH1 timing tKCY tKL tKH SCK1 0.8VDD 0.2VDD tSIK tKSI 0.8VDD SI1 Unit 1000 Output mode SCK1 high and low level width Max. Input data 0.2VDD tKSO 0.8VDD Output data SO1 0.2VDD – 16 – CXP823P24 (3) A/D converter characteristics Item Symbol (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Pin Condition Min. Typ. Resolution Linearity error Zero transition voltage VZT∗1 Full-scale transition voltage VFT∗2 Conversion time Sampling time tCONV tSAMP Analog input voltage VIAN A/D converter operation only Ta = 25°C VDD = 5.0V VSS = 0V Max. Unit 8 Bits ±3 LSB –10 70 150 mV 4930 5050 5120 mV 160/fADC ∗3 12/fADC ∗3 AN0 to AN7 0 µs µs VDD V Fig. 6. Definition of A/D converter terms FFH FEH Digital conversion value ∗1 VZT : Digital Value converted between 00H to 01H. ∗2 VFT : Digital Value converted between FEH and FFH. ∗3 fADC : ADC operation clock selection (MSC: Bit 0 of address 01FFH) and assumes following values: fADC = fc/2 when PS2 is selected. fADC = fc when PS1 is selected. Linearity error 01H 00H VZT VFT Analog input – 17 – CXP823P24 (4) Interrupts, reset inputs (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Item Symbol Pin Condition Min. Max. Unit External interrupt High and Low level widths tIH tIL INT0 INT1 INT2 INT3 1 µs Reset input Low level width tRSL RST 8/fc µs Fig. 7. Interrupt input timing tIH tIL 0.8VDD 0.2VDD INT0 INT1 INT2 INT3 tIL tIH 0.8VDD 0.2VDD Fig. 8. RST input timing tRSL RST 0.2VDD (5) Power-on reset Power-on reset (Ta = –10 to +75°C, VDD = 4.5 to 5.0V, VSS = 0V) Item Symbol tR Power supply cut-off time tOFF Pin Condition Power-on reset Power supply rising time VDD Repetitive power-on reset Min. Max. Unit 0.05 50 ms 1 Fig. 9. Power-on reset 4.5V VDD 0.2V 0.2V tR tOFF The power supply should rise smoothly. – 18 – ms CXP823P24 Supplement Fig. 10. Recommended Oscillation Circuit AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA (i) (ii) EXTAL EXTAL XTAL C1 C2 C1 Manufacturer MURATA MFG CO., LTD XTAL Model C2 fc (MHz) CSA4.19MG 4.19 CSA8.00MTZ 8.00 CSA10.0MTZ 10.00 CST4.19MGW∗ CST8.00MTW∗ CST10.0MTW∗ 4.19 C1 (pF) C2 (pF) Circuit Example (i) 30 30 (ii) 8.00 10.00 4.19 RIVER HC-49/U03 ELETEC CORPORATION 8.00 15 15 10.00 (i) 4.19 KINSEKI LTD. HC-49/U (-S) 8.00 27 27 10.00 ∗ Indicates types with on-chip grounding capacitors (C1 and C2). Product List Optional item Mask CXP823P24Q-1- CXP823P24Q-2- 80 pin plastic QFP 80 pin plastic QFP 80 pin plastic QFP ROM capacity 20K bytes/24K bytes PROM 24K bytes PROM 24K bytes Reset pin pull-up resistor Existent/Non-existent Existent Existent Power-on reset circuit Existent/Non-existent Existent Existent High voltage tolerance pin pull-down resistor Existent/Non-existent Package Non-existent (S0/PD0 to S15/PF7) Existent (T0 to S16) – 19 – Existent (High voltage tolerance pin) CXP823P24 Package Outline Unit: mm 80PIN QFP (PLASTIC) 23.9 ± 0.4 + 0.1 0.15 – 0.05 + 0.4 20.0 – 0.1 64 0.15 41 65 16.3 17.9 ± 0.4 + 0.4 14.0 – 0.1 40 A + 0.2 0.1 – 0.05 25 1 24 0.8 0.2 M + 0.15 0.35 – 0.1 + 0.35 2.75 – 0.15 0° to 10° DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING SONY CODE QFP-80P-L01 LEAD TREATMENT EIAJ CODE QFP080-P-1420 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 1.6g JEDEC CODE – 20 – 0.8 ± 0.2 80