SONY ICX085AK

ICX085AK
Diagonal 11mm (Type 2/3) Progressive Scan CCD Image Sensor with Square Pixel for Color Cameras
Description
The ICX085AK is a diagonal 11mm (Type 2/3)
interline CCD solid-state image sensor with a square
pixel array. Progressive scan allows all pixels
signals to be output independently within
approximately 1/12 second. This chip features an
electronic shutter with variable charge-storage time
which makes it possible to realize full-frame still
image without a mechanical shutter. High resolution
and high color reproductivity are achieved through
the use of R, G, B primary color mosaic filters.
Further, high sensitivity and low dark current are
achieved through the adoption of HAD (HoleAccumulation Diode) sensors.
This chip is suitable for image input applications
such as still cameras which require high resolution.
20 pin DIP (Ceramic)
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
Pin 1
Features
V
• Progressive scan allows individual readout of the
image signals from all pixels.
• High vertical resolution (1024TV-lines) still image
4
without a mechanical shutter.
56
H
• Square pixel unit cell
Pin 11
• Aspect ratio 5:4
• Horizontal drive frequency: 20.25MHz
Optical black position
• Reset gate bias is not adjusted.
• Substrate voltage: 5.5 to 12.5V
(Top View)
• R, G, B primary color mosaic filters on chip
• Continuous variable-speed shutter
• High resolution, high color reproductivity, high sensitivity, low dark current
• Low smear
• Excellent antiblooming characteristics
• Horizontal register: 5V drive
1
3
Device Structure
• Interline CCD image sensor
• Image size:
Diagonal 11mm (Type 2/3)
• Number of effective pixels: 1300 (H) × 1030 (V) approx. 1.3M pixels
• Total number of pixels:
1360 (H) × 1034 (V) approx. 1.4M pixels
• Chip size:
10.0mm (H) × 8.7mm (V)
• Unit cell size:
6.7µm (H) × 6.7µm (V)
• Optical black:
Horizontal (H) direction: Front 4 pixels, rear 56 pixels
Vertical (V) direction:
Front 3 pixels, rear 1 pixel
• Number of dummy bits:
Horizontal 24
Vertical 1
• Substrate material:
Silicon
∗ Wfine CCD is a registered trademark of Sony Corporation.
Represents a CCD adopting progressive scan, primary color filter and square pixel.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E96414D99
ICX085AK
GND
CGG
NC
GND
GND
VL
Vφ1
Vφ2
Vφ3
10
9
8
7
6
5
4
3
2
1
Vertical register
VOUT
Block Diagram and Pin Configuration
(Top View)
G
B
G
B
R
G
R
G
G
B
G
B
R
G
R
G
G
B
G
B
R
G
R
G
Note)
Horizontal register
14
15
16
17
18
VDD
GND
SUB
NC
NC
RG
GND
19
20
Hφ2
13
Hφ1
12
VRD
Note)
11
: Photo sensor
Pin Description
Pin No.
Symbol
Description
Pin No.
Symbol
Description
1
Vφ3
Vertical register transfer clock
11
VRD
Reset drain power supply
2
Vφ2
Vertical register transfer clock
12
VDD
Supply voltage
3
Vφ1
Vertical register transfer clock
13
GND
GND
4
VL
Protective transistor bias
14
SUB
Substrate (overflow drain)
5
GND
GND
15
NC
6
GND
GND
16
NC
7
NC
17
RG
Reset gate clock
18
GND
GND
8
CGG
Output amplifier gate∗1
9
GND
GND
19
Hφ1
Horizontal register transfer clock
10
VOUT
Signal output
20
Hφ2
Horizontal register transfer clock
∗1 DC bias is applied within the CCD, so that this pin should be grounded externally through a capacitance of
1µF or more.
–2–
ICX085AK
Absolute Maximum Ratings
Item
Ratings
Unit
–0.3 to +55
V
VDD, VOUT, VRD, CGG–GND
–0.3 to +18
V
VDD, VOUT, VRD, CGG–SUB
–55 to +9
V
Vφ1, Vφ2, Vφ3–GND
–15 to +16
V
Vφ1, Vφ2, Vφ3–SUB
to +10
V
Voltage difference between vertical clock input pins
to +15
V
Voltage difference between horizontal clock input pins
to +16
V
Hφ1, Hφ2–Vφ3
–16 to +16
V
Hφ1, Hφ2–GND
–10 to +15
V
Hφ1, Hφ2–SUB
–55 to +10
V
VL–SUB
–65 to +0.3
V
Vφ2, Vφ3–VL
–0.3 to +27.5
V
RG–GND
–0.3 to +20.5
V
Vφ1, Hφ1, Hφ2, GND–VL
–0.3 to +17.5
V
Storage temperature
–30 to +80
°C
Operating temperature
–10 to +60
°C
Substrate voltage SUB–GND
Supply voltage
Vertical clock input
voltage
∗1 +24V (Max.) when clock width < 10µs, clock duty factor < 0.1%.
–3–
Remarks
∗1
ICX085AK
Bias Conditions
Item
Symbol
Min.
Typ.
Max.
Unit
Remarks
Supply voltage
VDD
14.55
15.0
15.45
V
Substrate voltage adjustment range
VSUB
5.5
12.5
V
∗1
Protective transistor bias
VL
Typ.
Max.
Unit
Remarks
6
8
mA
∗2
DC Characteristics
Item
Symbol
Supply current
Min.
IDD
∗1 Indications of substrate voltage (VSUB) setting value
The setting value of the substrate voltage is indicated on the back of image sensor by a special code.
Adjust the substrate voltage (VSUB) to the indicated voltage.
VSUB code – two characters indication
↑
↑
Integer portion
Decimal portion
Integer portion of code and optimal setting correspond to each other as follows.
Integer portion of code
A
C
d
E
f
G
h
J
Optimal setting
5
6
7
8
9
10
11
12
<Example> “G5”→ VSUB = 10.5V
∗2 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same supply voltage as the VL
power supply for the V driver should be used.
Clock Voltage Conditions
Typ.
Max. Unit
VVT
14.55
15.0
15.45
V
1
VVH02
–0.05
0
0.05
V
2
VVH1,VVH2,VVH3
–0.2
0
0.05
V
2
VVL1,VVL2,VVL3
–8.0
–7.5
–7.0
V
2
Vφ1, Vφ2, Vφ3
Vertical transfer clock
| VVL1–VVL3 |
voltage
VVHH
6.8
7.5
8.05
V
2
0.1
V
2
0.5
V
2
High-level coupling
VVHL
0.5
V
2
High-level coupling
VVLH
0.5
V
2
Low-level coupling
VVLL
0.5
V
2
Low-level coupling
Readout clock voltage
Horizontal transfer
clock voltage
Symbol
Waveform
diagram
Min.
Item
Substrate clock voltage
VVH = VVH02
VVL = (VVL1 + VVL3)/2
VφH
4.75
5.0
5.25
V
3
VHL
–0.05
0
0.05
V
3
4.5
5.0
5.5
V
4
Input through 0.01µF capacitance
0.8
V
4
Low-level coupling
V
4
V
5
VφRG
Reset gate clock
voltage
Remarks
VRGLH–VRGLL
VRGH
VDD
+0.4
VDD
+0.6
VDD
+0.8
VφSUB
21.5
22.5
23.5
–4–
ICX085AK
Clock Equivalent Circuit Constant
Symbol
Item
Min.
Typ.
Max.
Unit
CφV1
5000
pF
CφV2, CφV3
10000
pF
CφV12
1200
pF
CφV23
100
pF
CφV31
3300
pF
CφH1
82
pF
CφH2
68
pF
Capacitance between horizontal
transfer clocks
CφHH
22
pF
Capacitance between reset gate clock
and GND
CφRG
6
pF
Capacitance between substrate clock
and GND
CφSUB
800
pF
Vertical transfer clock series resistor
R1, R2, R3
30
Ω
Vertical transfer clock ground resistor
RGND
30
Ω
Horizontal transfer clock series resistor
RφH1, RφH2
10
Ω
Reset gate clock series resistor
RφRG
20
Ω
Capacitance between vertical transfer
clock and GND
Capacitance between vertical transfer
clocks
Capacitance between horizontal
transfer clock and GND
Vφ1
R1
R2
CφV12
CφV1
Vφ2
CφV2
RφH1
RφH2
Hφ1
RGND
Cφv31
Remarks
Hφ2
CφHH
CφV3
Cφv23
CφH1
CφH2
R3
Vφ3
Vertical transfer clock equivalent circuit
Horizontal transfer clock equivalent circuit
RφRG
RGφ
CφRG
Reset gate clock equivalent circuit
–5–
ICX085AK
Drive Clock Waveform Conditions
(1) Readout clock waveform
VT
100%
90%
II
II
φM
VVT
φM
2
10%
0%
tr
twh
0V
tf
(2) Vertical transfer clock waveform
Vφ1
VVH1
VVHH
VVH
VVHL
VVLH
VVL01
VVL1
VVL
VVLL
Vφ2
VVH02
VVH2
VVHH
VVH
VVHL
VVLH
VVL2
VVL
VVLL
Vφ3
VVH3
VVHH
VVH
VVHL
VVLH
VVL03
VVL
VVLL
VφV1 = VVH1 – VVL01
VφV2 = VVH02 – VVL2
VφV3 = VVH3 – VVL03
VVH = VVH02
VVL = (VVL01 + VVL03) /2
–6–
ICX085AK
(3) Horizontal transfer clock waveform
Hφ1, Hφ2
tr
twh
tf
90%
twl
VφH
10%
VHL
(4) Reset gate clock waveform
φRG
tr
twh
tf
VRGH
twl
RG waveform
Point A
VφRG
VRGL + 0.5V
VRGLH
VRGL
VRGLL
Hφ1 waveform
2.5V
VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from
Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and
VRGLL.
VRGL = (VRGLH + VRGLL) /2
Assuming VRGH is the minimum value during the interval twh, then:
VφRG = VRGH – VRGL
(5) Substrate clock waveform
φSUB
100%
90%
φM
Vφ SUB
VSUB
10%
0%
tr
–7–
twh
φM
2
tf
ICX085AK
Clock Switching Characteristics
Item
Symbol
VT
Vertical transfer
clock
Vφ1,
Vφ2, Vφ3
Horizontal
transfer clock
Readout clock
During
imaging
twh
twl
tr
tf
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
4.6 5.0
0.5
0.5
52.5
110
Hφ1
15
18
15
19
6
10.6
6
10.6
Hφ2
16
19
15
18
6
10.6
6
10.6
During
Hφ1
parallel-serial
Hφ2
conversion
Reset gate clock
φRG
Substrate clock
φSUB
7
8
37.9
1.8 2.1
0.01
0.01
0.01
0.01
2.5
2.5
0.5
Unit
Remarks
µs
During
readout
ns
∗1
ns
∗2
µs
ns
0.5
µs
During drain
charge
∗1 When vertical transfer clock driver CXD1268M × 2 is used.
∗2 tf ≥ tr – 2ns, and the cross-point voltage (VCR) for the Hφ1 rising side of the Hφ1 and Hφ2 waveforms must be
at least 2.5V.
two
Item
Horizontal transfer clock
Symbol
Hφ1, Hφ2
Min. Typ. Max.
13.0 15.5
Unit
ns
Remarks
∗3
∗3 The overlap period for twh and twl of horizontal transfer clocks Hφ1 and Hφ2 is two.
–8–
ICX085AK
Image Sensor Characteristics
Item
(1/12 second accumulation mode, Ta = 25°C)
Measurement method
mV
1
Min.
Typ.
Sg
890
1100
R
Rr
0.4
0.5
0.55
1
B
Rb
0.4
0.5
0.55
1
Saturation signal
Vsat
400
Smear
Sm
Video signal shading
SHg
G sensitivity
Sensitivity
comparison
Max.
Unit
Symbol
Remarks
Ta = 60°C
mV
2
0.008
%
3
20
%
4
Zone 0 and I
25
%
4
Zone 0 to II'
∆Srg
8
%
5
∆Sbg
8
%
5
Dark signal
Vdt
8
mV
6
Ta = 60°C
Dark signal shading
∆Vdt
4
mV
7
Ta = 60°C
Line crawl G
Lcg
3.8
%
8
Line crawl R
Lcr
3.8
%
8
Line crawl B
Lcb
3.8
%
8
Lag
Lag
0.5
%
9
Uniformity between video
signal channels
0.005
Zone Definition of Video Signal Shading
1300 (H)
10
10
3
V
10
H
8
H
8
Zone 0, I
Zone II, II'
V
10
1030 (V)
3
Ignored region
Effective pixel region
Measurement System
CCD signal output [∗A]
Gr/Gb
CCD
C.D.S
AMP
S/H
Gr/Gb channel signal output [∗B]
R/B
S/H
R/B channel signal output [∗C]
Note) Adjust the amplifier gain so that the gain between [∗A] and [∗B], and between [∗A] and [∗C] equals 1.
–9–
ICX085AK
Image Sensor Characteristics Measurement Method
Measurement conditions
1) In the following measurements, the substrate voltage is set to the value indicated on the device, and the
device drive conditions are at the typical values of the bias and clock voltage conditions.
2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical
black level (OB) is used as the reference for the signal output, which is taken as the value of the Gr/Gb
signal output or the R/B signal output of the measurement system.
Color coding and readout of this image sensor
Gb
B
Gb
B
R
Gr
R
Gr
Gb
B
Gb
B
R
Gr
R
Gr
The primary color filters of this image sensor are arranged in the
layout shown in the figure on the left (Bayer arrangement).
Gr and Gb denote the G signals on the same line as the R signal and
the B signal, respectively.
Horizontal register
Color Coding Diagram
All pixels signals are output successively in a 1/12s period.
The R signal and Gr signal lines and the Gb signal and B signal lines are output successively.
– 10 –
ICX085AK
Definition of standard imaging conditions
1) Standard imaging condition I :
Use a pattern box (luminance 706cd/m2, color temperature of 3200K halogen source ) as a subject.
(Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR
cut filter and image at F5.6. The luminous intensity to the sensor receiving surface at this point is defined
as the standard sensitivity testing luminous intensity.
2) Standard imaging condition II :
Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles.
Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted
to the value indicated in each testing item by the lens diaphragm.
1. G sensitivity, sensitivity comparison
Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of
1/80s, measure the signal outputs (VGr, VGb, VR and VB) at the center of each Gr, Gb, R and B channel
screens, and substitute the values into the following formula.
VG = (VGr + VGb)/2
Sg = VG × 80 [mV]
12
Rr = VR/VG
Rb = VB/VG
2. Saturation signal
Set to standard imaging condition II. After adjusting the luminous intensity to 10 times the intensity with the
average value of the Gr signal output, 150mV, measure the minimum values of the Gr, Gb, R and B signal
outputs.
3. Smear
Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, first adjust the average value
of the Gr signal output to 150mV. Measure the average values of the Gr signal output, Gb signal output, R
signal output and B signal output (Gra, Gba, Ra and Ba), and then adjust the luminous intensity to 500
times the intensity with average value of the Gr signal output, 150mV. After the readout clock is stopped
and the charge drain is executed by the electronic shutter at the respective H blankings, measure the
maximum value (VSm [mV]), independent of the Gr, Gb, R and B signal outputs, and substitute the values
into the following formula.
Sm = VSm ÷
Gra + Gba + Ra + Ba
1
×
× 1 × 100 [%] (1/10V method conversion value)
4
500
10
4. Video signal shading
Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity
so that the average value of the Gr signal output is 150mV. Then measure the maximum (Grmax [mV])
and minimum (Grmin [mV]) values of the Gr signal output and substitute the values into the following
formula.
SHg = (Grmax – Grmin)/150 × 100 [%]
– 11 –
ICX085AK
5. Uniformity between video signal channels
After measuring 4, measure the maximum (Rmax [mV]) and minimum (Rmin [mV]) values of the R signal
and the maximum (Bmax [mV]) and minimum (Bmin [mV]) values of the B signal, and substitute the values
into the following formula.
∆Srg = (Rmax – Rmin)/150 × 100 [%]
∆Sbg = (Bmax – Bmin)/150 × 100 [%]
6. Dark signal
Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature 60°C and
the device in the light-obstructed state, using the horizontal idle transfer level as a reference.
7. Dark signal shading
After measuring 6, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark
signal output and substitute the values into the following formula.
∆Vdt = Vdmax – Vdmin [mV]
8. Line crawl
Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Gr
signal output is 150mV, and then insert R, G, and B filters and measure the difference between G signal
lines (∆Glr, ∆Glg, ∆Glb [mV]) as well as the average value of the G signal output (Gar, Gag, Gab).
Substitute the values into the following formula.
Lci = ∆Gli × 100 [%] (i = r, g, b)
Gai
9. Lag
Adjust the Gr signal output value generated by strobe light to 150mV. After setting the strobe light so that
it strobes with the following timing, measure the residual signal (Vlag). Substitute the value into the
following formula.
Lag = (Vlag/150) × 100 [%]
FLD
SG
Light
Strobe light timing
Gr signal output 150mV
Output
– 12 –
Vlag (Lag)
– 13 –
XH1
RG
XH2
VSUB
XSUB
XV1
XV3
XV2
XSG
5V
–7.5V
15V
22/20V
22/10V
22/16V
1
2
3
4
5
6
7
N.C.
8
9
N.C.
10
10
1
2
N.C.
3
4
N.C. 5
6
7
N.C.
8
9
CXD1267AN
CXD1268M
×2
N.C.
20
N.C.
19
N.C.
18
17
16
15
N.C.
14
N.C.
13
12
N.C.
11
20
19
18
17
N.C.
16
15
14
N.C.
13
12
11
22/16V
1/35V
22/20V
3.3/16V
AC04
AC04
1 2 3 4 5 6 7 8 9 10
1/10V
0.1
ICX085
(BOTTOM VIEW)
Vφ3
Vφ2
Vφ1
VL
GND
GND
NC
CGG
GND
VOUT
0.01
100k
1/20V
20 19 18 17 16 15 14 13 12 11
Hφ2
Hφ1
GND
RG
NC
NC
SUB
GND
VDD
VRD
Drive Circuit
3.3/20V
2SK523
0.01
100k
2.7k
47
0.1
1M
CCD OUT
ICX085AK
ICX085AK
Spectral Sensitivity Characteristics
(Includes lens characteristics, excludes light source characteristics)
1
0.9
R
0.8
B
G
Relative Response
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
400
500
600
Wave Length [nm]
– 14 –
700
– 15 –
V3
V2
V1
SG
HD
Sensor Readout Clock Timing Chart
33.7µs (683 bits)
5.0µs (102 bits)
4.0µs (81 bits)
ICX085AK
– 16 –
CCD OUT
V3
V2
V1
SG
HD
VD
Drive Timing Chart (Vertical Sync)
1030
1031
10
1 2 3 4 5
ICX085AK
20
15
5
1044
1
– 17 –
1616
1
CCD OUT
OPB (56 bits)
1
SUB
1
1
1
19
1
V3
V2
V1
SHD
SHP
RG
H2
H1
19
1
38
1
57
1
57
1
57
1
167
1
42
1
23
137
156
175
326
OPB (4 bits)
65
65
1
CLK
297
232
1
HD
321
24
Drive Timing Chart (Horizontal Sync)
ICX085AK
ICX085AK
Notes on Handling
1) Static charge prevention
CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes.
b) When handling directly use an earth band.
c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.
d) Ionized air is recommended for discharge when handling CCD image sensor.
e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges.
2) Soldering
a) Make sure the package temperature does not exceed 80°C.
b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W
soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently.
c) To dismount an image sensor, do not use a solder suction equipment. When using an electric
desoldering tool, use a thermal controller of the zero cross On/Off type and connect it to ground.
3) Dust and dirt protection
Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and
dirt. Clean glass plates with the following operation as required, and use them.
a) Operate in clean environments (around class 1000 is appropriate).
b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should
dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized
air is recommended.)
c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass.
d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when
moving to a room with great temperature differences.
e) When a protective tape is applied before shipping, just before use remove the tape applied for
electrostatic protection. Do not reuse the tape.
4) Do not expose to strong light (sun rays) for long periods, color filters will be discolored. When high
luminance objects are imaged with the exposure level control by electronic-iris, the luminance of the imageplane may become excessive and discolor of the color filter will possibly be accelerated. In such a case, it is
advisable that taking-lens with the automatic-iris and closing of the shutter during the power-off mode
should be properly arranged. For continuous using under cruel condition exceeding the normal using
condition, consult our company.
5) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or usage
in such conditions.
6) CCD image sensors are precise optical equipment that should not be subject to too much mechanical
shocks.
– 18 –
– 19 –
+ 0.25
2-φ2.50 0
V
H
A
31.0 ± 0.4
27.0 ± 0.3
11
~
2R3
~
8. Planar orientation of the effective image area relative to the bottom “D” is less than 60µm.
9. The thickness of the cover glass is 0.75mm and the refractive index is 1.5.
GOLD PLATING
42 ALLOY
5.9g
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
7. The height from the bottom “D” to the effective image area is 1.46 ± 0.15mm.
6. The angle of rotation relative to the reference line “B” is less than ± 1°.
5. The center of the effective image area, specified relative to the reference hole
is (H, V) = (13.15, 5.0) ± 0.15mm.
4. The bottom “D” is the height reference. (Two points are specified.)
3. A straight line “C” which passes through the center of the reference hole
at right angles to vertical reference line “B” is the reference axis of horizontal direction.
2. A straight line “B” which passes through the centers of the reference hole and
the elongated hole is the reference axis of vertical direction.
Ceramic
M
.0
1. “A” is the center of the effective image sensor area.
+ 0.15
2.00 0 × 2.5
(Elongated Hole)
D
26.0
PACKAGE MATERIAL
0.3
0.46
1.27
1 13.15
0.5 10
26.00 ± 0.25
20
PACKAGE STRUCTURE
2.54
1Pin Index
B
+ 0.15
φ2.00 0
(Reference Hole) 0.35
5.0
20pin DIP (800mil)
0° to 9°
0.25
C
20.2 ± 0.3
1.0
20.32
Unit: mm
3.2 ± 0.3
5.5 ± 0.2
(AT STAND OFF)
Package Outline
ICX085AK