ICX413AQ Diagonal 28.40mm (Type 1.8) Frame Readout CCD Image Sensor with Square Pixel for Color Cameras Description The ICX413AQ is a diagonal 28.40mm (Type 1.8) interline CCD solid-state image sensor with a square pixel array and 6.15M effective pixels. Frame readout allows all pixels' signals to be output independently within approximately 1/3.08 second. Adoption of a design specially suited for frame readout ensures a high saturation signal level. High sensitivity and low dark current are achieved through the adoption of R, G and B primary color mosaic filters and HAD (Hole-Accumulation Diode) sensors. This chip is suitable for applications such as electronic still cameras, etc. 34 pin DIP (Plastic) Pin 1 2 Features • Frame readout mode • High horizontal and vertical resolution • Square pixel • Horizontal drive frequency: 25.0MHz • R, G, B primary color mosaic filters on chip • High sensitivity, low dark current V 4 20 H 50 Pin 18 Optical black position Device Structure (Top View) • Interline CCD image sensor • Optical size: Diagonal 28.40mm (Type 1.8) • Total number of pixels: 3110 (H) × 2030 (V) approx. 6.31M pixels • Number of effective pixels: 3040 (H) × 2024 (V) approx. 6.15M pixels • Number of active pixels: 3032 (H) × 2016 (V) approx. 6.11M pixels • Number of recommended recording pixels: 3000 (H) × 2000 (V) approx. 6M pixels • Chip size: 25.10mm (H) × 17.64mm (V) • Unit cell size: 7.80µm (H) × 7.80µm (V) • Optical black: Horizontal (H) direction: Front 20 pixels, rear 50 pixels Vertical (V) direction: Front 4 pixels, rear 2 pixels • Number of dummy bits: Horizontal 31 Vertical 1 (even fields only) • Substrate material: Silicon ∗ Super HAD CCD is a registered trademark of Sony Corporation. Super HAD CCD is a CCD that drastically improves sensitivity by introducing newly developed semiconductor technology by Sony Corporation into Sony's high-performance HAD (Hole-Accumulation Diode) sensor. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E02120B35 ICX413AQ GND NC Vφ1 NC NC NC Vφ2 GND NC Vφ3 NC Vφ4 NC NC GND VL 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Vertical register VSUB Block Diagram and Pin Configuration (Top View) G B G B R G R G G B G B R G R G G B G B R G R G Note) Horizontal register 28 29 30 31 32 33 GND Hφ1A Hφ2A : Photo sensor 34 GND 27 Hφ2B 26 Hφ1B 25 GND φRG 24 Hφ2C GND 23 Hφ1C VOUT 22 LHφ 21 GND 20 VDD 19 GND 18 VSS Note) Pin Description Pin Symbol No. Description Pin Symbol No. Description 1 VL Protective transistor bias 18 VSS Output amplifier source 2 GND GND 19 VOUT Signal output 3 NC 20 GND GND 4 NC 21 φRG Reset gate clock 5 Vφ4 22 GND GND 6 NC 23 VDD Supply voltage 7 Vφ3 24 GND GND 8 NC 25 LHφ Horizontal register final stage transfer clock 9 GND GND 26 Hφ1C Horizontal register transfer clock 10 Vφ2 Vertical register transfer clock 27 Hφ2C Horizontal register transfer clock 11 NC 28 GND GND 12 NC 29 Hφ1B Horizontal register transfer clock 13 NC 30 Hφ2B Horizontal register transfer clock 14 Vφ1 31 GND GND 15 NC 32 Hφ1A Horizontal register transfer clock 16 GND GND 33 Hφ2A Horizontal register transfer clock 17 VSUB Substrate bias 34 GND GND Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock –2– ICX413AQ Absolute Maximum Ratings Item Against φSUB Ratings Unit VDD, VOUT, φRG – φSUB –40 to +10 V Vφ1, Vφ3 – φSUB –50 to +15 V Vφ2, Vφ4, VL – φSUB –50 to +0.3 V –40 to +0.3 V VDD, VOUT, φRG – GND –0.3 to +18 V Vφ1, Vφ2, Vφ3, Vφ4 – GND –10 to +18 V –10 to +7 V –0.3 to +28 V –0.3 to +15 V to +15 V LHφ, Hφ1α, Hφ2α, GND – φSUB (α = Against GND LHφ, Hφ1α, Hφ2α – GND (α = A, B, C) A, B, C) Vφ1, Vφ3 – VL Against VL Vφ2, Vφ4, LHφ, Hφ1α, Hφ2α, GND – VL (α = A, B, C) Voltage difference between vertical clock input pins Between input clock pins Hφ1α – Hφ2α (α = –7 to +7 V –17 to +17 V Storage temperature –30 to +80 °C Guaranteed temperature of performance –10 to +60 °C Operating temperature –10 to +75 °C A, B, C) Hφ1α, Hφ2α – Vφ4 (α = A, B, C) Remarks ∗1 ∗1 +24V (Max.) when clock width < 10µs, clock duty factor < 0.1%. Bias Conditions Item Symbol Supply voltage VDD Output amplifier source VSS Substrate voltage adjustment range VSUB Min. Typ. Max. Unit 14.55 15.0 15.45 V Remarks Ground with resistance of 750 to 900Ω 8.0 15.0 Protective transistor bias VL ∗1 Reset gate clock φRG ∗2 ∗1 VL setting is the VVL voltage of the vertical clock waveform, or the same voltage as the VL power supply for the V driver should be used. ∗2 Do not apply a DC bias to the reset gate clock pins, because a DC bias is generated within the CCD. DC Characteristics Item Supply current Symbol Min. IDD Typ. 7.0 –3– Max. Unit mA Remarks ICX413AQ Clock Voltage Conditions Item Readout clock voltage Symbol Typ. Max. Unit VVT 14.55 15.0 15.45 V 1 VVH1, VVH2 –0.05 0 0.05 V 2 VVH3, VVH4 –0.2 0 0.05 V 2 VVL1, VVL2, VVL3, VVL4 –8.5 –8.0 –7.5 V 2 VVL = (VVL3 + VVL4)/2 V 2 VφV = VVHn – VVLn (n = 1 to 4) 8.0 VφV Vertical transfer clock voltage Horizontal transfer clock voltage Reset gate clock voltage Substrate clock voltage Remarks VVH = (VVH1 + VVH2)/2 VVH3 – VVH –0.25 0.1 V 2 VVH4 – VVH –0.25 0.1 V 2 VVHH 0.5 V 2 High-level coupling VVHL 0.5 V 2 High-level coupling VVLH 0.5 V 2 Low-level coupling VVLL 0.5 V 2 Low-level coupling VφH 5.75 6.0 7.0 V 3 VHL –0.05 0 0.05 V 3 V 3 3.0 VCR Horizontal final stage transfer clock voltage Waveform diagram Min. Cross-point voltage VLHH 5.75 6.0 7.0 V 4 VLHL –0.05 0 0.05 V 4 VφRG 4.75 5.0 5.25 V 5 VRGLH – VRGLL 0.4 V 5 Low-level coupling VRGL – VRGLm 0.5 V 5 Low-level coupling 24.0 V 6 VφSUB 22.0 23.0 –4– ICX413AQ Clock Equivalent Circuit Constant Symbol Item Min. Typ. Max. Unit Remarks CφV1, CφV3 18000 pF CφV2, CφV4 15000 pF CφV12, CφV34 18000 pF CφV23, CφV41 10000 pF CφV13 6800 pF CφV24 8200 pF Capacitance between horizontal transfer clock and GND CφH1 18 pF CφH2 27 pF Capacitance between horizontal transfer clocks CφHH 221 pF Capacitance between horizontal final stage transfer CφLH clock and GND 8 pF Capacitance between reset gate clock and GND CφRG 6 pF Capacitance between substrate clock and GND CφSUB 2700 pF Vertical transfer clock series resistor R1, R2, R3, R4 18 Ω Vertical transfer clock ground resistor RGND 3.9 Ω Horizontal transfer clock series resistor RφH 2.2 Ω Horizontal final stage transfer clock series resistor RφLH 39 Ω Reset gate clock series resistor RφRG 39 Ω Capacitance between vertical transfer clock and GND Capacitance between vertical transfer clocks Vφ2 Vφ1 CφV12 R1 RφH R2 Hφ2A RφH CφV1 Hφ2B RφH Hφ1C Hφ2C CφV13 CφV4 R4 RφH RφH CφV23 CφV24 CφHH Hφ1B CφV2 CφV41 RφH Hφ1A RGND CφV3 CφH1 CφH2 R3 CφV34 Vφ4 Vφ3 Vertical transfer clock equivalent circuit Horizontal transfer clock equivalent circuit RφRG φRG CφRG Reset gate clock equivalent circuit –5– ICX413AQ Drive Clock Waveform Conditions (1) Readout clock waveform 100% 90% φM VVT φM 2 10% 0% tr twh 0V tf (2) Vertical transfer clock waveform Vφ1 Vφ3 VVH1 VVHH VVH VVHL VVHL VVH3 VVHL VVL1 VVHH VVHH VVHH VVH VVHL VVL3 VVLH VVLH VVLL VVLL VVL VVL Vφ2 Vφ4 VVHH VVHH VVH VVH VVHH VVHH VVHL VVHL VVH2 VVHL VVH4 VVL2 VVHL VVLH VVLH VVLL VVLL VVL VVL4 VVH = (VVH1 + VVH2)/2 VVL = (VVL3 + VVL4)/2 VφV = VVHn – VVLn (n = 1 to 4) –6– VVL ICX413AQ (3) Horizontal transfer clock waveform tr tf twh Hφ2 90% VCR VφH twl VφH 2 10% Hφ1 VHL two Cross-point voltage for the Hφ1 rising side of the horizontal transfer clocks Hφ1 and Hφ2 waveforms is VCR. The overlap period for twh and twl of horizontal transfer clocks Hφ1 and Hφ2 is two. (4) Horizontal final stage transfer clock waveform tr twh tf VLHH 90% VφLH twl 10% VLHL (5) Reset gate clock waveform tr twh tf VRGH RG waveform twl VφRG Point A VRGLH VRGL VRGLL VRGLm VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and VRGLL. VRGL = (VRGLH + VRGLL)/2 Assuming VRGH is the minimum value during the interval with twh, then: VφRG = VRGH – VRGL Negative overshoot level during the falling edge of RG is VRGLm. –7– ICX413AQ (6) Substrate clock waveform 100% 90% φM VφSUB φM 2 10% VSUB 0% tr twh tf Clock Switching Characteristics (Horizontal drive frequency: 25MHz) Symbol Item twh twl tr tf Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit Remarks 1.5 1.5 µs During readout 2 2 µs When using CXD1268M 15 5 5 15 15 5 5 Horizontal final LHφ stage transfer clock 17 17 3 3 ns Reset gate clock φRG 7 2 2 ns Substrate clock φSUB 6 Readout clock VT 7.5 Vertical transfer clock Vφ1, Vφ2, Vφ3, Vφ4 Horizontal transfer clock Hφ1 15 Hφ2 ns µs ∗1 When draining charge ∗1 The phase of horizontal final stage transfer clock amplitude level 50% and horizontal transfer clock Hφ2 amplitude level 50% must be matched. Item Symbol Horizontal transfer clock Hφ1, Hφ2 two Min. Typ. Max. 17 Unit Remarks ns Spectral Sensitivity Characteristics (excludes lens characteristics and light source characteristics) 1.0 G R Relative Response 0.8 B 0.6 0.4 0.2 0 400 450 500 600 550 Wave Length [nm] –8– 650 700 ICX413AQ Image Sensor Characteristics Item Symbol (Ta = 25°C) Min. Typ. Max. Unit Measurement method mV 1 G sensitivity Sg 800 1000 1200 Sensitivity comparison Rr 0.42 0.57 0.72 Rb 0.23 0.38 0.53 Saturation signal Vsat 900 Smear Sm Video signal shading SHg Dark signal Vdt Dark signal shading Remarks 1/30s accumulation 1 mV 2 Ta = 60°C dB 3 Frame readout mode, ∗1 % 4 4 mV 5 Ta = 60°C, 3.08 frame/s ∆Vdt 2 mV 6 Ta = 60°C, 3.08 frame/s, ∗2 Line crawl G Lcg 10 % 7 Line crawl R Lcr 10 % 7 Line crawl B Lcb 10 % 7 Lag Lag 0.5 % 8 –110 –90 20 25 Zone 0 and I Zone 0 to II' ∗1 After closing the mechanical shutter, the smear can be reduced to below the detection limit by performing vertical register sweep operation. ∗2 Excludes vertical dark signal shading caused by vertical register high-speed transfer. Zone Definition of Video Signal Shading 3040 (H) 4 4 4 V 10 H 8 H 8 Zone 0, I Zone II, II' 2024 (V) 4 Ignored region Effective pixel region V 10 Measurement System CCD signal output [∗A] CCD C.D.S AMP S/H Gr/Gb channel signal output [∗B] S/H R/B channel signal output [∗C] Note) Adjust the amplifier gain so that the gain between [∗A] and [∗B], and between [∗A] and [∗C] equals 1. –9– ICX413AQ Image Sensor Characteristics Measurement Method Measurement conditions (1) In the following measurements, the device drive conditions are at the typical values of the bias and clock voltage conditions, and the frame readout mode is used. (2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical black level (OB) is used as the reference for the signal output, which is taken as the value of the Gr/Gb signal output or the R/B signal output of the measurement system. Color coding of this image sensor & Readout B2 B1 Gb B Gb B R Gr R Gr Gb B Gb B R Gr R Gr A2 A1 The primary color filters of this image sensor are arranged in the layout shown in the figure on the left (Bayer arrangement). Gr and Gb denote the G signals on the same line as the R signal and the B signal, respectively. For frame readout, the A1 and A2 lines are output as signals in the A field, and the B1 and B2 lines in the B field. Horizontal register Color Coding Diagram – 10 – ICX413AQ Definition of standard imaging conditions (1) Standard imaging condition I: Use a pattern box (luminance: 706cd/m2, color temperature of 3200K halogen source) as a subject. (Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter and image at F5.6. The luminous intensity to the sensor receiving surface at this point is defined as the standard sensitivity testing luminous intensity. (2) Standard imaging condition II: Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles. Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted to the value indicated in each testing item by the lens diaphragm. 1. G sensitivity, sensitivity comparison Set to the standard imaging condition I. After setting the electronic shutter mode with a shutter speed of 1/100s, measure the signal outputs (VGr, VGb, VR and VB) at the center of each Gr, Gb, R and B channel screen, and substitute the values into the following formulas. VG = (VGr + VGb)/2 Sg = VG × 100 [mV] 30 Rr = VR/VG Rb = VB/VG 2. Saturation signal Set to the standard imaging condition II: After adjusting the luminous intensity to 20 times the intensity with the average value of the Gr signal output, 150mV, measure the minimum values of the Gr, Gb, R and B signal outputs. 3. Smear Set to the standard imaging condition II. With the lens diaphragm at F5.6 to F8, first adjust the average value of the Gr signal output to 150mV. Measure the average values of the Gr signal output, Gb signal output, R signal output and B signal output (Gra, Gba, Ra, Ba), and then adjust the luminous intensity to 500 times the intensity with the average value of the Gr signal output, 150mV. After the readout clock is stopped and the charge drain is executed by the electronic shutter at the respective H blankings, measure the maximum value (Vsm [mV]) independent of the Gr, Gb, R and B signal outputs, and substitute the values into the following formula. Sm = 20 × log Vsm ÷ Gra + Gba + Ra + Ba × 1 × 1 10 4 500 ( 4. ) [dB] (1/10V method conversion value) Video signal shading Set to the standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjusting the luminous intensity so that the average value of the Gr signal output is 150mV. Then measure the maximum value (Grmax [mV]) and minimum value (Grmin [mV]) of the Gr signal output and substitute the values into the following formula. SHg = (Grmax – Grmin)/150 × 100 [%] – 11 – ICX413AQ 5. Dark signal Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature of 60°C and the device in the light-obstructed state, using the horizontal idle transfer level as a reference. 6. Dark signal shading After measuring 5, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark signal output and substitute the values into the following formula. ∆Vdt = Vdmax – Vdmin [mV] 7. Line crawl Set to the standard imaging condition II. Adjusting the luminous intensity so that the average value of the Gr signal output is 150mV, and then insert R, G and B filters and measure the difference between G signal lines (∆Glr, ∆Glg, ∆Glb [mV]) as well as the average value of the G signal output (Gar, Gag, Gab). Substitute the values into the following formula. Lci = ∆Gli × 100 [%] (i = r, g, b) Gai 8. Lag Adjust the Gr channel output generated by the strobe light to 150mV. After setting the strobe light so that it strobes with the following timing, measure the residual signal amount (Vlag). Substitute the value into the following formula. Lag = (Vlag/150) × 100 [%] VD V1 Light Strobe light timing Gr sinal ouitput 150mV Output – 12 – Vlag (lag) – 13 – CCD OUT Mechanical shutter VSUB V4 V3 V2 V1 HD OPEN 1 2 3 CLOSE "c" "a" 138 139 1 3 1 3 5 7 9 VD Exposure period 1149 All pixel output period 2017 2019 2021 2023 1155 "d" "b" Frame Readout Mode 1227 2 4 2 4 6 8 10 1222 1264 135 10 Drive Timing Chart (Vertical Sync Accumulation Time Control by Mechanical Shutter) ICX413AQ 2018 2020 2022 2024 2241 1153 – 14 – V4 V3 V2 V1 H2 H1 60 60 #1 60 60 60 60 #2 60 60 60 60 #3 60 60 60 60 #4 60 60 "c": 135H/"d": 68H Frame Readout Mode 534 3621 1 54 Vertical Sync "c" Enlarged, "d" Enlarged Drive Timing Chart (Vertical Sync) 60 "c": #2030 "d": #1015 60 60 60 ICX413AQ 534 3621 1 54 – 15 – V4 V3 V2 V1 "b" Enlarged V4 V3 V2 V1 H1 3621 1 55 "a" Enlarged Drive Timing Chart (Vertical Sync "a" Enlarged, "b" Enlarged) 1800 2040 2100 2100 2040 2100 2040 2340 ICX413AQ 1 55 3621 – 16 – SUB V4 V3 V2 V1 H2 H1 1 3621 Ignored pixel 4 bits 60 60 60 60 60 60 60 60 Ignored pixel 4 bits 31 1 20 50 1 Drive Timing Chart (Horizontal Sync) ICX413AQ 480 1 ICX413AQ Notes on Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensors. e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges. 2) Soldering a) Make sure the package temperature does not exceed 80°C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a 30W soldering iron with a ground wire and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering tool, use a thermal controller of the zero-cross On/Off type and connect it to ground. 3) Dust and dirt protection Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and dirt. Clean glass plates with the following operations as required, and use them. a) Operate in clean environments (around class 1000 is appropriate). b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. e) When a protective tape is applied before shipping, just before use remove the tape applied for electrostatic protection. Do not reuse the tape. 4) Do not expose to strong light (sun rays) for long periods, as color filters will be discolored. When high luminous objects are imaged with the exposure level controlled by the electronic iris, the luminance of the image-plane may become excessive and discoloring of the color filter will possibly be accelerated. In such a case, it is advisable that taking-lens with the automatic-iris and closing of the shutter during the power-off mode should be properly arranged. For continuous using under cruel condition exceeding the normal using condition, consult our company. 5) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. 6) CCD image sensors are precise optical equipment that should not be subject to too much mechanical shocks. – 17 – 0.77 3.0 – 18 – GOLD PLATING 42 ALLOY 7.00g AS-Z4(E) LEAD MATERIAL PACKAGE MASS DRAWING NUMBER B' A ~ 17 LEAD TREATMENT 0.46 1.778 35.2 ± 0.2 36.4 37.2 ± 0.15 H 18 Plastic, Metal 1 V R0.8 18.6 ± 0.3 34 PACKAGE MATERIAL B 1.50 ~ ~ 23.3 ± 0.2 24.6 0.77 3.0 D 26.25 –+ 00.4 17 C ~ 25.00 19.00 Metal part ~ ~ 1 1 10. Metal part at the bottom of a package is sticking out 0.1mm. from the surrounding plastic part. 9. The notches on the bottom of the package are used only for directional index, they must not be used for reference of fixing. 8. The thickness of the cover glass is 0.7mm, and the refractive index is 1.5. 7. The tilt of the effective image area relative to the bottom "C" is less than 150µm. 6. The height from the bottom "C" to the effective image area is 1.40 ± 0.15mm. The height from the top of the cover glass "D" to the effective image area is 1.20 ± 0.15mm. 5. The rotation angle of the effective image area relative to H and V is ± 1˚. 4. The center of the effective image area relative to "B" and "B'" is ( H, V ) = ( 18.6, 12.7 ) ± 0.03mm 3. The metal area "C" of the package bottom, and the top of the cover glass "D" are the height reference. 2. The two points "B" of the package are the horizontal reference. The point "B'" of the package is the vertical reference. 1. "A" is the center of the effective image area. 1.20 ± 0.15 0.70 ± 0.10 0.80 1.90 ± 0.15 2.60 ± 0.30 2.25 ± 0.15 ˚ 17.60 34 Pin DIP 3 Unit: mm 10 1.4 ± 0.2 25.4 ± 0.15 12.7 ± 0.3 to 11.60 0˚ 5.0 ± 0.2 1.50 0 5. -φ 0. ± Package Outline ICX413AQ Sony Corporation