SN74LVC573 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS SCAS300A – JANUARY 1993 – REVISED NOVEMBER 1994 • • • • EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages DB, DW, OR PW PACKAGE (TOP VIEW) OE 1D 2D 3D 4D 5D 6D 7D 8D GND description 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q LE This octal transparent D-type latch is designed for 2.7-V to 3.6-V VCC operation. The SN74LVC573 features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without the need for interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN74LVC573 is characterized for operation from – 40°C to 85°C. FUNCTION TABLE (each latch) INPUTS OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z EPIC is a trademark of Texas Instruments Incorporated. Copyright 1994, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74LVC573 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS SCAS300A – JANUARY 1993 – REVISED NOVEMBER 1994 logic symbol† OE LE 1D 2D 3D 4D 5D 6D 7D 8D 1 11 2 logic diagram (positive logic) EN OE C1 1D 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 LE 1 11 1Q C1 2Q 3Q 1D 2 19 1Q 1D 4Q 5Q 6Q 7Q To Seven Other Channels 8Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 100 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DB package . . . . . . . . . . . . . . . . . 0.6 W DW package . . . . . . . . . . . . . . . . . 1.6 W PW package . . . . . . . . . . . . . . . . . 0.7 W Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. This value is limited to 4.6 V maximum. 2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74LVC573 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS SCAS300A – JANUARY 1993 – REVISED NOVEMBER 1994 recommended operating conditions (see Note 3) MIN MAX 2.7 3.6 VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 0 VO Output voltage 0 High-level input voltage VCC = 2.7 V to 3.6 V VCC = 2.7 V to 3.6 V IOH High level output current High-level VCC = 2.7 V VCC = 3 V IOL Low level output current Low-level VCC = 2.7 V VCC = 3 V ∆t /∆v Input transition rise or fall rate 2 V V 0.8 V VCC VCC V – 12 12 – 24 24 TA Operating free-air temperature NOTE 3: Unused or floating inputs must be held high or low. UNIT V mA mA 0 10 ns / V – 40 85 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER IOH = – 100 µA VOH MIN to MAX VCC – 0.2 2.2 2.7 V IOH = – 12 mA IOH = – 24 mA IOL = 100 µA VOL TA = – 40°C to 85°C MIN MAX VCC† TEST CONDITIONS 3V 2.4 3V 2 UNIT V MIN to MAX 0.2 V IOL = 12 mA IOL = 24 mA 2.7 V 0.4 3V 0.55 II IOZ VI = VCC or GND VO = VCC or GND 3.6 V ±5 µA 3.6 V ±10 µA ICC VI = VCC or GND, IO = 0 VCC = 3 V to 3.6 V, One input at VCC – 0.6 V, Other inputs at VCC or GND 3.6 V 20 µA 500 µA VI = VCC or GND VO = VCC or GND 3.3 V pF 3.3 V pF nICC Ci Co † For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions. timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 3.3 V ± 0.3 V MIN MAX VCC = 2.7 V MIN UNIT MAX tw tsu Pulse duration, LE high 4 5 ns Setup time, data before LE↓ 2 3 ns th Hold time, data after LE↓ 2 3 ns POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74LVC573 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS SCAS300A – JANUARY 1993 – REVISED NOVEMBER 1994 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) D tpd d VCC = 3.3 V ± 0.3 V MIN TYP MAX TO (OUTPUT) Q LE VCC = 2.7 V MIN MAX 1.5 4.2 8 1.5 9 1.5 5 9 1.5 10 UNIT ns ten OE Q 1.5 4 8.5 1.5 9.5 ns tdis OE Q 1.5 3.7 7.5 1.5 8.5 ns operating characteristics, VCC = 3.3 V, TA = 25°C PARAMETER Cpd d 4 Power dissipation capacitance TEST CONDITIONS Outputs enabled Outputs disabled POST OFFICE BOX 655303 CL = 50 pF, pF • DALLAS, TEXAS 75265 f = 10 MHz TYP 20 3.5 UNIT pF SN74LVC573 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS SCAS300A – JANUARY 1993 – REVISED NOVEMBER 1994 PARAMETER MEASUREMENT INFORMATION 6V 500 Ω From Output Under Test S1 Open TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND GND CL = 50 pF (see Note A) 500 Ω LOAD CIRCUIT FOR OUTPUTS 2.7 V 1.5 V Timing Input 0V tw tsu 2.7 V th 2.7 V Input 1.5 V 1.5 V 0V 1.5 V Data Input 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.5 V Input 1.5 V 0V 1.5 V 1.5 V VOL VOH Output 1.5 V 1.5 V 0V 1.5 V VOL tPLZ Output Waveform 1 S1 at 6 V (see Note C) tPLH tPHL 1.5 V tPZL VOH Output 2.7 V Output Control tPHL tPLH 1.5 V Output Waveform 2 S1 at GND (see Note C) 1.5 V tPZH VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 3V VOL + 0.3 V VOL tPHZ 1.5 V VOH – 0.3 V VOH [0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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