74ACT11373
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS015B – JUNE 1987 – REVISED APRIL 1996
D
D
D
D
D
D
D
D
D
D
DB, DW, OR NT PACKAGE
(TOP VIEW)
Eight Latches in a Single Package
3-State Bus Driving True Outputs
Full Parallel Access for Loading
Buffered Input and Output-Enable Pins
Inputs Are TTL-Voltage Compatible
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
EPICt (Enhanced-Performance Implanted
CMOS) 1-mm Process
500-mA Typical Latch-Up Immunity at
125°C
Package Options Include Plastic
Small-Outline (DW) and Shrink
Small-Outline (DB) Packages, and Standard
Plastic 300-mil DIPs (NT)
1Q
2Q
3Q
4Q
GND
GND
GND
GND
5Q
6Q
7Q
8Q
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
OE
1D
2D
3D
4D
VCC
VCC
5D
6D
7D
8D
LE
description
This 8-bit latch features 3-state outputs designed specifically for driving highly-capacitive or relatively
low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers.
The eight latches of the 74ACT11373 are transparent D-type latches. While the latch-enable (LE) input is high,
the Q outputs follow the data (D) inputs. When the enable is taken low, the Q outputs are latched at the levels
that were set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impendance third state and increased drive provide the capability to drive
the bus lines in a bus-organized system without need for interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are off.
The 74ACT11373 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each latch)
INPUTS
OE
LE
D
OUTPUT
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
74ACT11373
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS015B – JUNE 1987 – REVISED APRIL 1996
logic symbol†
OE
LE
1D
2D
3D
4D
5D
6D
7D
8D
24
13
23
22
EN
C1
1
1D
1Q
2
2Q
21
3
20
4
17
9
16
10
15
11
14
12
3Q
4Q
5Q
6Q
7Q
8Q
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
OE
LE
1D
2D
3D
4D
5D
6D
24
13
23
22
21
20
17
16
C1
C1
7D
8D
2
14
2
1D
C1
3
1D
C1
4
1D
C1
9
1D
C1
10
1D
C1
15
1
1D
11
1D
C1
1D
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12
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
74ACT11373
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS015B – JUNE 1987 – REVISED APRIL 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DB package . . . . . . . . . . . . . . . . . . 0.65 W
DW package . . . . . . . . . . . . . . . . . . 1.7 W
NT package . . . . . . . . . . . . . . . . . . . 1.3 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils,
except for the NT package, which has a trace length of zero.
recommended operating conditions
MIN
MAX
4.5
5.5
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
0
VO
IOH
Output voltage
0
High-level input voltage
2
UNIT
V
V
0.8
V
VCC
VCC
V
High-level output current
–24
mA
IOL
Dt/Dv
Low-level output current
24
mA
0
10
ns/V
TA
Operating free-air temperature
–40
85
°C
Input transition rise or fall rate
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V
3
74ACT11373
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS015B – JUNE 1987 – REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
4.5 V
IOH = –50
50 mA
VOH
24 mA
IOH = –24
IOH = –75 mA{
IOZ
II
IOL = 24 mA
IOL = 75 mA{
VO = VCC or GND
ICC
VI = VCC or GND
VI = VCC or GND,
DICC}
One input at 3.4 V,
Ci
TA = 25°C
TYP
MAX
MIN
4.4
4.4
5.5 V
5.4
5.4
4.5 V
3.94
3.8
5.5 V
4.94
MAX
UNIT
V
4.8
5.5 V
IOL = 50 mA
VOL
MIN
3.85
4.5 V
0.1
5.5 V
0.1
0.1
0.1
4.5 V
0.36
0.44
5.5 V
0.36
0.44
5.5 V
V
1.65
5.5 V
±0.5
±5
mA
5.5 V
±0.1
±1
mA
IO = 0
5.5 V
8
80
mA
Other inputs at GND or VCC
5.5 V
0.9
1
mA
VI = VCC or GND
VO = VCC or GND
5V
4
pF
Co
5V
10
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
pF
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
tw
tsu
Pulse duration, LE high
th
MIN
MAX
UNIT
5
5
ns
Setup time, data before LE↓
3.5
3.5
ns
Hold time, data LE↓
3.5
3.5
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
4
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
D
Q
tPLH
tPHL
LE
Any Q
tPZH
tPZL
OE
Any Q
tPHZ
tPLZ
OE
Any Q
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MIN
TA = 25°C
TYP
MAX
MIN
MAX
1.5
7.5
10.3
1.5
11.8
1.5
6.5
9.3
1.5
10
1.5
8.5
11.3
1.5
13
1.5
8.5
10.9
1.5
12.2
1.5
7
10.7
1.5
12.5
1.5
7.5
10.9
1.5
12
1.5
10
12.1
1.5
12.2
1.5
7.5
9.5
1.5
10.1
UNIT
ns
ns
ns
ns
74ACT11373
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS015B – JUNE 1987 – REVISED APRIL 1996
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
d
TEST CONDITIONS
Outputs enabled
Power dissipation capacitance per latch
pF
CL = 50 pF,
Outputs disabled
TYP
f = 1 MHz
65
54
UNIT
pF
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
3V
Timing Input
1.5 V
0V
tw
tsu
3V
Input
1.5 V
th
1.5 V
3V
1.5 V
1.5 V
Data Input
0V
0V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
3V
Input
1.5 V
1.5 V
0V
tPHL
tPLH
In-Phase
Output
50% VCC
50% VCC
0V
tPZL
VOH
50% VCC
VOL
Output
Waveform 2
S1 at GND
(see Note B)
[ VCC
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
tPHL
Out-of-Phase
Output
VOH
50% VCC
VOL
3V
1.5 V
1.5 V
50% VCC
VOL
tPHZ
tPZH
VOLTAGE WAVEFORMS
20% VCC
50% VCC
80% VCC
VOH
[0V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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