TI SN74LVC16373DL

SN74LVC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS315B – NOVEMBER 1993 – REVISED JULY 1995
D
D
D
D
D
D
D
DGG OR DL PACKAGE
(TOP VIEW)
Member of the Texas Instruments
Widebus  Family
EPIC  (Enhanced-Performance Implanted
CMOS) Submicron Process
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
description
This 16-bit transparent D-type latch is designed
for 2.7-V to 3.6-V VCC operation.
The SN74LVC16373 is particularly suitable for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers. It
can be used as two 8-bit latches or one 16-bit
latch. When the latch-enable (LE) input is high, the
Q outputs follow the data (D) inputs. When LE is
taken low, the Q outputs are latched at the levels
set up at the D inputs.
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1LE
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2LE
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus
lines without need for interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74LVC16373 is characterized for operation from – 40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright  1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
SN74LVC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS315B – NOVEMBER 1993 – REVISED JULY 1995
FUNCTION TABLE
(each 8-bit section)
INPUTS
OE
LE
D
OUTPUT
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
logic symbol†
1OE
1LE
2OE
2LE
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
1
48
24
25
47
logic diagram (positive logic)
1OE
1EN
C3
1LE
C1
C4
3D
1D1
2
1
3
44
5
43
6
41
8
40
9
38
11
37
12
36
13
33
48
2EN
46
35
1
4D
2
14
16
32
17
30
19
29
20
27
22
26
23
47
1Q1
1Q1
1Q2
1Q3
1Q4
To Seven Other Channels
1Q5
1Q6
1Q7
2OE
1Q8
2Q1
2LE
24
25
2Q2
2Q3
C1
2D1
36
1D
2Q4
2Q5
2Q6
2Q7
To Seven Other Channels
2Q8
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
2
2
1D
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13
2Q1
SN74LVC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS315B – NOVEMBER 1993 – REVISED JULY 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 100 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 3): DGG package . . . . . . . . . . . . . . . 0.85 W
DL package . . . . . . . . . . . . . . . . . . 1.2 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology
Data Book, literature number SCBD002B.
recommended operating conditions (see Note 4)
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
VO
Output voltage
High-level input voltage
VCC = 2.7 V to 3.6 V
VCC = 2.7 V to 3.6 V
Input voltage
MIN
MAX
2.7
3.6
2
0
0
IOH
High level output current
High-level
VCC = 2.7 V
VCC = 3 V
IOL
Low level output current
Low-level
VCC = 2.7 V
VCC = 3 V
∆t /∆V
Input transition rise or fall rate
TA
Operating free-air temperature
NOTE 4: Unused control inputs must be held high or low to prevent them from floating.
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UNIT
V
V
0.8
V
VCC
VCC
V
– 12
12
– 24
24
V
mA
mA
0
10
ns / V
– 40
85
°C
3
SN74LVC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS315B – NOVEMBER 1993 – REVISED JULY 1995
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VCC†
MIN to MAX
TEST CONDITIONS
IOH = – 100 µA
2.7
IOH = – 12 mA
VOH
IOH = – 24 mA
IOL = 100 µA
VOL
II
II(hold)
I(h ld)
Data inputs
IOZ
ICC
Ci
MAX
VCC – 0.2
2.2
3
2.4
3
2
0.2
2.7
0.4
3
0.55
VI = VCC or GND
VI = 0.8 V
3.6
±5
75
3
VI = 2 V
VO = VCC or GND
IO = 0
Other inputs at VCC or GND
UNIT
V
MIN to MAX
VI = VCC or GND
VO = VCC or GND
Co
TYP‡
IOL = 12 mA
IOL = 24 mA
VI = VCC or GND,
One input at VCC – 0.6 V,
nICC
MIN
V
µA
µA
–75
3.6
± 10
µA
3.6
40
µA
500
µA
3 V to 3.6 V
3.3
3.5
pF
3.3
7
pF
† For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions.
‡ All typical values are at VCC = 3.3 V, TA = 25°C.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
MIN
MIN
MAX
UNIT
MAX
tw
tsu
Pulse duration, LE high
4
4
ns
Setup time, data before LE↓
2
2
ns
th
Hold time, data after LE↓
2
2
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
tpd
FROM
(INPUT)
D
TO
(OUTPUT)
Q
LE
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
MIN
MAX
MIN
1.5
7
8
2
8
9
UNIT
MAX
ns
ten
OE
Q
1.5
8
9
ns
tdis
OE
Q
1.5
7
8
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
d
4
Power dissipation capacitance per latch
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Outputs disabled
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pF
CL = 50 pF,
f = 10 MHz
TYP
20
4
UNIT
pF
SN74LVC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS315B – NOVEMBER 1993 – REVISED JULY 1995
PARAMETER MEASUREMENT INFORMATION
6V
500 Ω
From Output
Under Test
S1
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
2.7 V
LOAD CIRCUIT FOR OUTPUTS
1.5 V
Timing Input
0V
tw
tsu
2.7 V
1.5 V
Input
1.5 V
th
2.7 V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
1.5 V
Input
1.5 V
0V
VOH
1.5 V
Output
1.5 V
VOL
VOH
Output
1.5 V
1.5 V
0V
1.5 V
VOL
tPLZ
Output
Waveform 1
S1 at 6 V
(see Note B)
tPLH
tPHL
1.5 V
tPZL
tPHL
tPLH
2.7 V
Output
Control
Output
Waveform 2
S1 at GND
(see Note B)
1.5 V
tPZH
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
3V
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH – 0.3 V
VOH
[0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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Copyright  1998, Texas Instruments Incorporated