1 Megabit Serial Flash SST45LF010 Data Sheet SST45LF0101Mb Serial Architecture Interface flash memory FEATURES: • • • • Single 3.0-3.6V Read and Write Operations Serial Interface Architecture Byte Serial Read with Single Command Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention • Low Power Consumption – Active Current: 10 mA (typical) – Standby Current: 10 µA (typical) • Sector or Chip-Erase Capability – Uniform 4 KByte sectors • Fast Erase and Byte-Program – Chip-Erase Time: 70 ms (typical) – Sector-Erase Time: 18 ms (typical) – Byte-Program Time: 14 µs (typical) • Automatic Write Timing – Internal VPP Generation • End-of-Write Detection – Software Status • 10 MHz Max Clock Frequency • Hardware Reset Pin (RST#) – Resets the device to Standby Mode • CMOS I/O Compatibility • Hardware Data Protection (WP#) – Protects and unprotects the device from Write operation • Packages Available – 8-lead SOIC (4.9mm x 6mm) – 8-contact WSON PRODUCT DESCRIPTION The SST45LF010 is a 1 Mbit serial flash memory manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The 1 Mbit of memory is organized as 32 sectors of 4096 Bytes. The flash memory uses a 3wire serial interface and a chip enable to select and sequentially access its data. The serial interface consists of; serial data input (SI), serial data output (SO), serial clock (SCK), and chip enable (CE#). A write protect (WP#) inhibits the entire memory from write operation and a hardware reset pin (RST#) resets the device to standby mode. Read The SST45LF010 device is offered in both 8-lead SOIC and 8-contact WSON packages. See Figure 1 for the pinouts. Sector/Chip-Erase Operation Device Operation The SST45LF010 uses bus cycles of 8 bits each for commands, data, and addresses to execute operations. The operation instructions are listed in Table 3. All instructions are synchronized off a high to low transition of CE#. The first low to high transition on SCK will initiate the instruction sequence. Inputs will be accepted on the rising edge of SCK starting with the most significant bit. Any low to high transition on CE# before the input instruction completes will terminate any instruction in progress and return the device to the standby mode. ©2001 Silicon Storage Technology, Inc. S71128-03-000 4/01 372 1 The Read operation outputs the data in order from the initial accessed address. While SCK is input, the address will be incremented automatically until end (top) of the address space (1FFFFH), then the internal address pointer automatically increments to beginning (bottom) of the address space (00000H), and data out stream will continue. The read data stream is continuous through all addresses until terminated by a low to high transition on CE#. The Sector-Erase operation clears all bits in the selected sector to FFH. The Chip-Erase instruction clears all bits in the device to FFH. Byte-Program Operation The Byte-Program operation programs the bits in the selected byte to the desired data. The selected byte must be in the erased state (FFH) when initiating a Program operation. The data is input from bit 7 to bit 0 in order. Software Status Operation The Status operation determines if an Erase or Program operation is in progress. If bit 0 is at a “0” an Erase or Program operation is in progress, the device is busy. If bit 0 is at a “1” the device is ready for any valid operation. The status read is continuous with ongoing clock cycles until terminated by a low to high transition on CE#. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 1 Megabit Serial Flash SST45LF010 Data Sheet Reset TABLE 1: PRODUCT IDENTIFICATION Reset will terminate any operation, e.g., Read, Erase and Program, in progress. It is activated by a high to low transition on the RST# pin. The device will remain in reset condition as long as RST# is low. Minimum reset time is 10 µs. See Figure 14 for reset timing diagram. RST# is internally pulled-up and could remain unconnected during normal operation. After reset, the device is in standby mode, a high to low transition on CE# is required to start the next operation. Byte Data Manufacturer’s ID 0000H BFH Device ID 0001H 42H T1.2 372 Write Protect The WP# pin provides inadvertent write protection. The WP# pin must be held high for any Erase or Program operation. The WP# pin is “Don’t Care” for all other operations. In typical use, the WP# pin is connected to VSS with a standard pull-down resistor. WP# is then driven high whenever an Erase or Program operation is required. If the WP# pin is tied to VDD with a pull-up resistor, then all operations may occur and the write protection feature is disabled. The WP# pin has an internal pull-up and could remain unconnected when not used. An internal power-on reset circuit protects against accidental data writes. Applying a logic level low to RST# during the power-on process then changing to a logic level high when VDD has reached the correct voltage level will provide additional protection against accidental writes during power on. Read SST ID/Read Device ID The Read SST ID and Read Device ID operations read the JEDEC assigned manufacturer identification and the manufacturer assigned device identification IDs. These IDs may be used to determine the actual device resident in the system. FUNCTIONAL BLOCK DIAGRAM SuperFlash Memory X - Decoder Address Buffers and Latches Y - Decoder I/O Buffers and Data Latches Control Logic Serial Interface CE# SCK SI SO ©2001 Silicon Storage Technology, Inc. WP# RST# 372 ILL B1.4 S71128-03-000 4/01 2 372 1 Megabit Serial Flash SST45LF010 Data Sheet WP# 1 VDD 2 8 RST# WP# 1 7 VSS VDD 2 Top View 8 RST# 7 VSS Top View CE# 3 6 SO CE# 3 6 SO SCK 4 5 SI SCK 4 5 SI 372 ILL F01a.2 372 ILL F01.6 8-LEAD SOIC 8-CONTACT WSON FIGURE 1: PIN ASSIGNMENTS TABLE 2: PIN DESCRIPTION Symbol Pin Name Functions SCK Serial Clock To provide the timing of the serial interface. Commands, addresses, or input data are latched on the rising edge of the clock input, while output data is shifted out on the falling edge of the clock input. SI Serial Data Input To transfer commands, addresses, or data serially into the device. Inputs are latched on the rising edge of the serial clock. SO Serial Data Output To transfer data serially out of the device. Data is shifted out on the falling edge of the serial clock. CE# Chip Enable The device is enabled by a high to low transition on CE#. WP# Write Protect To protect the device from unintentional Write (Erase or Program) operations. When WP# is low, all Erase and Program commands are ignored. When WP# is high, the device may be erased or programmed. This pin has an internal pull-up and could remain unconnected when not used. RST# Reset A high to low transition on RST# will terminate any operation in progress and reset the internal logic to the standby mode. The device will remain in the reset condition as long as the RST# is low. Operations may only occur when RST# is high. This pin has an internal pull-up and could remain unconnected when not used. VDD Power Supply To provide power supply (3.0-3.6V). VSS Ground T2.5 372 ©2001 Silicon Storage Technology, Inc. S71128-03-000 4/01 3 372 1 Megabit Serial Flash SST45LF010 Data Sheet TABLE 3: DEVICE OPERATION INSTRUCTIONS1 Bus Cycle2 1 2 3 4 Cycle Type/ Operation3,4 SIN SOUT SIN SOUT SIN SOUT SIN Read FFH Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Sector-Erase5 20H Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z X 5 SOUT 6 7 SIN SOUT SIN SOUT SIN SOUT Hi-Z X Hi-Z X Hi-Z X DOUT Hi-Z D0H Hi-Z X Hi-Z X Hi-Z Chip-Erase 60H Hi-Z X Hi-Z X Hi-Z X Hi-Z D0H Hi-Z X Hi-Z X Hi-Z Byte-Program 10H Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z DIN Hi-Z X Hi-Z X Hi-Z X Note6 X Note6 X Note6 X Note6 ID Addr7 Hi-Z X DOUT7 X Note8 X Status Reg. 9FH X X DOUT X Note6 Read-ID 90H Hi-Z 00H Hi-Z 00H Hi-Z Note8 T3.10 372 1. 2. 3. 4. 5. 6. 7. 8. For SST45LF010, A23-A17 are “Don’t Care.” One bus cycle is eight clock periods Operation: SIN=Serial In, SOUT=Serial Out X=Dummy cycles (Don’t Care) A16-A12 are used to determine sector address, A11-A8 are “Don’t Care.” The status read is continuous with ongoing clock cycles until terminated by a low to high transition on CE#. Manufacturer’s ID=BFH, is read with A0 =0 and Device ID = 42H, is read with A0 =1; All other address bits are 0 The data output is arbitrary. TABLE 4: DEVICE OPERATION TABLE Operation SI SO Read X DOUT Sector-Erase X X Chip-Erase CE#1 WP# RST# Low X High Low High High X X Low High High DIN X Low High High Software-Status X DOUT Low X High Reset2 X X X X Low Byte-Program Read SST ID X DOUT Low X High Read Device ID X DOUT Low X High T4.6 372 1. A high to low transition on CE# will be required to start any device operation except for Reset. 2. The RST# low will return the device to standby and terminate any Erase or Program operation in progress. ©2001 Silicon Storage Technology, Inc. S71128-03-000 4/01 4 372 1 Megabit Serial Flash SST45LF010 Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD+1.0V Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA 1. Outputs shorted for no more than one second. No more than one output shorted at a time. OPERATING RANGE AC CONDITIONS Range Commercial Ambient Temp VDD 0°C to +70°C 3.3V±0.3V OF TEST Input Rise/Fall Time . . . . . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF See Figures 2 and 3 TABLE 5: DC OPERATING CHARACTERISTICS VDD = 3.0-3.6V Limits Symbol Parameter IDD Power Supply Current Min Max Units 20 mA Test Conditions f=10 MHz Read CE#=VIL, VDD=VDD Max Program and Erase 30 mA CE#=VIL, VDD=VDD Max ISB Standby Current 15 µA CE#=VIHC, VDD=VDD Max ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max ILO Output Leakage Current 1 µA VOUT =GND to VDD, VDD=VDD Max 360 µA WP#, RST#=GND 0.8 V VDD=VDD Min Current1 IIL Input Low VIL Input Low Voltage VIH Input High Voltage 0.7 VDD V VDD=VDD Max VIHC Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max VOL Output Low Voltage V IOL=100 µA, VDD=VDD Min VOH Output High Voltage V IOH=-100 µA, VDD=VDD Min 0.2 VDD-0.2 T5.1 372 1. This parameter only applies to WP# and RST# pins. ©2001 Silicon Storage Technology, Inc. S71128-03-000 4/01 5 372 1 Megabit Serial Flash SST45LF010 Data Sheet TABLE 6: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open) Parameter Description COUT1 Output Pin Capacitance CIN 1 Input Capacitance Test Condition Maximum VOUT = 0V 12 pF VIN = 0V 6 pF T6.1 372 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 7: RELIABILITY CHARACTERISTICS Symbol NEND 1 Parameter Minimum Specification Units Endurance 10,000 Cycles JEDEC Standard A117 100 Years JEDEC Standard A103 100 + IDD mA TDR1 Data Retention ILTH1 Latch Up Test Method JEDEC Standard 78 T7.1 372 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 8: AC OPERATING CHARACTERISTICS, VDD = 3.0-3.6V Limits Symbol Parameter FCLK Serial Clock Frequency TSCKH Serial Clock High Time TSCKL TCES Min Max Units 10 MHz 45 ns Serial Clock Low Time 45 ns CE# Setup Time 250 ns TCEH CE# Hold Time 250 ns TCPH CE# High Time 250 ns TCHZ CE# High to High-Z Output TCLZ SCK Low to Low-Z Output TRLZ RST# Low to High-Z Output TDS Data In Setup Time 20 TDH Data In Hold Time 20 ns TOH Output Hold from SCK Change 0 ns TV Output Valid from SCK TWPS Write Protect Setup Time 10 TWPH Write Protect Hold Time 10 TSE Sector-Erase 25 ms TSCE Chip-Erase 100 ms TBP Byte-Program 20 µs TRST Reset Pulse Width TREC Reset Recovery Time TPURST Reset Time After Power-Up 25 0 ns 25 ns ns 35 ns ns ns 10 µs 1 10 ns µs µs T8.2 372 ©2001 Silicon Storage Technology, Inc. S71128-03-000 4/01 6 372 1 Megabit Serial Flash SST45LF010 Data Sheet VIHT INPUT VIT REFERENCE POINTS VOT OUTPUT VILT 372 ILL F02.2 AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns. Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test FIGURE 2: AC INPUT/OUTPUT REFERENCE WAVEFORMS TO TESTER TO DUT CL 372 ILL F03.2 FIGURE 3: A TEST LOAD EXAMPLE ©2001 Silicon Storage Technology, Inc. S71128-03-000 4/01 7 372 1 Megabit Serial Flash SST45LF010 Data Sheet WP# TCPH CE# TSCKH TSCKL TCES TCEH SCK TDS SI SO TDH DATA VALID HIGH-Z HIGH-Z 372 ILL F04.6 FIGURE 4: SERIAL INPUT TIMING DIAGRAM (INACTIVE SERIAL CLOCK LOW) WP# CE# TSCKH TSCKL TCEH SCK TCHZ TOH TCLZ DATA VALID SO TV SI 372 ILL F05.6 FIGURE 5: SERIAL OUTPUT TIMING DIAGRAM (INACTIVE SERIAL CLOCK LOW) ©2001 Silicon Storage Technology, Inc. S71128-03-000 4/01 8 372 1 Megabit Serial Flash SST45LF010 Data Sheet TWPS TWPH WP# CE# TSE 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 47 39 40 SCK 20H SI ADD. ADD. D0H X SELF-TIMED SECTORERASE CYCLE X HIGH IMPEDANCE SO 372 ILL F06.7 FIGURE 6: SECTOR-ERASE TIMING DIAGRAM TWPS TWPH WP# CE# TSCE 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 SCK SI 60H SO X X X D0H SELF-TIMED CHIPERASE CYCLE X HIGH IMPEDANCE 372 ILL F07.10 FIGURE 7: CHIP-ERASE TIMING DIAGRAM ©2001 Silicon Storage Technology, Inc. S71128-03-000 4/01 9 372 1 Megabit Serial Flash SST45LF010 Data Sheet TWPS TWPH WP# CE# 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 SCK 10H SI ADD. ADD. Din ADD. MSB TBP SELF-TIMED BYTEPROGRAM CYCLE X LSB HIGH IMPEDANCE SO 372 ILL F08.8 FIGURE 8: BYTE-PROGRAM TIMING DIAGRAM WP# CE# 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 48 55 56 63 64 71 SCK SI FFH SO ADD. ADD. HIGH IMPEDANCE ADD. X X N Dout N+1 Dout N+2 Dout MSB MSB MSB 372 ILL F10.6 FIGURE 9: READ TIMING DIAGRAM ©2001 Silicon Storage Technology, Inc. S71128-03-000 4/01 10 372 1 Megabit Serial Flash SST45LF010 Data Sheet WP# CE# 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 48 55 56 63 64 71 SCK 90H SI 00H ADD1 00H HIGH IMPEDANCE SO Dout1 MSB LSB 372 ILL F19.4 Note: 1. SST Manufacturer's ID = BFH is read with A0=0 SST45LF010 Device ID = 42H is read with A0=1 FIGURE 10: READ-ID TIMING DIAGRAM WP# CE# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 23 24 31 SCK SI SO 9FH HIGH IMPEDANCE DATA MSB DATA MSB DATA MSB 372 ILL F11.5 FIGURE 11: SOFTWARE-STATUS TIMING DIAGRAM ©2001 Silicon Storage Technology, Inc. S71128-03-000 4/01 11 372 1 Megabit Serial Flash SST45LF010 Data Sheet CE# TREC TCES ... SCK TRST RESET# SO ... SI ... HIGH IMPEDANCE TRLZ HIGH IMPEDANCE 372 ILL F20.4 FIGURE 12: RESET TIMING DIAGRAM (INACTIVE CLOCK POLARITY LOW) VDD TPURST RESET# TREC CE# 372 ILL F13.3 FIGURE 13: POWER-ON RESET TIMING DIAGRAM TWPS TWPH WP# TCPH CE# TCES TCEH SCK 372 ILL F14.1 FIGURE 14: WRITE PROTECT TIMING DIAGRAM ©2001 Silicon Storage Technology, Inc. S71128-03-000 4/01 12 372 1 Megabit Serial Flash SST45LF010 Data Sheet Device Speed SST45LFxxx - XXX Suffix1 - XX Suffix2 - XX Package Modifier A = 8 leads Package Type S = SOIC Q = WSON Temperature Range C = Commercial = 0°C to +70°C Minimum Endurance 4 = 10,000 cycles Operating Frequency 10 = 10 MHz Device Density 010 = 1 Megabit Voltage L = 3.0-3.6V SST45LF010 Valid combinations SST45LF010-10-4C-SA Example: SST45LF010-10-4C-QA Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ©2001 Silicon Storage Technology, Inc. S71128-03-000 4/01 13 372 1 Megabit Serial Flash SST45LF010 Data Sheet PACKAGING DIAGRAMS Pin #1 Identifier Side View Top View 7˚ 4 places .51 .33 5.0 4.8 1.27 BSC End View 45˚ 4.00 3.80 7˚ 4 places 0.25 0.10 6.20 5.80 1.75 1.35 0.25 0.19 0˚ Note: 1. Complies with JEDEC publication 95 MS-012 AA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (±.05) mm. 4. Maximum allowable mold flash is 0.15 mm at the package ends and 0.25 mm between leads. 1.27 0.40 8˚ 08.soic-SA-ILL.5 8-LEAD SMALL OUTLINE INTEGRATED CIRCUIT PACKAGE (SOIC) SST PACKAGE CODE: SA Pin #1 Corner Bottom View Side View Top View Pin #1 .19 .25 1.27 BSC 4.00 5.00 BSC .076 3.40 .35 .48 .05 Max 6.00 BSC .70 .80 Note: 1. All linear dimensions are in millimeters (min/max). .50 .75 Cross Section 8-wson-5x6-QA-ILL.4 .70 .80 8-CONTACT ULTRA-THIN SMALL OUTLINE NO-LEAD PACKAGE (WSON) SST PACKAGE CODE: QA Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 www.SuperFlash.com or www.ssti.com ©2001 Silicon Storage Technology, Inc. S71128-03-000 4/01 14 372