TI SN74LV240DW

SN54LV240, SN74LV240
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS193B – FEBRUARY 1993 – REVISED APRIL 1996
D
D
D
D
SN54LV240 . . . J OR W PACKAGE
SN74LV240 . . . DB, DW, OR PW PACKAGE
(TOP VIEW)
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
SN54LV240 . . . FK PACKAGE
(TOP VIEW)
2OE
D
EPIC  (Enhanced-Performance Implanted
CMOS) 2-µ Process
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2 V at VCC, TA = 25°C
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW),
Ceramic Flat (W) Packages, Chip Carriers
(FK), and (J) 300-mil DIPs
2Y4
1A1
1OE
VCC
D
description
1A2
2Y3
1A3
2Y2
1A4
These octal buffers/drivers are designed for 2.7-V
to 5.5-V VCC operation.
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
1Y1
2A4
1Y2
2A3
1Y3
2Y1
GND
2A1
1Y4
2A2
The ’LV240 are designed specifically to improve
both the performance and density of 3-state
memory address drivers, clock drivers, and
bus-oriented receivers and transmitters.
4
The ’LV240 are organized as two 4-bit buffers/line
drivers with separate output-enable (OE) inputs.
When OE is low, the device passes data from the
A inputs to the Y outputs. When OE is high, the
outputs are in the high-impedance state.
The SN74LV240 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54LV240 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74LV240 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each buffer)
INPUTS
OE
A
OUTPUT
Y
L
H
L
L
L
H
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright  1996, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54LV240, SN74LV240
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS193B – FEBRUARY 1993 – REVISED APRIL 1996
logic symbol†
1OE
1A1
1A2
1A3
1A4
1
logic diagram (positive logic)
1
1OE
EN
2
18
4
16
6
14
8
12
1Y1
2
18
4
16
1A1
1Y2
1Y3
1A2
14
1Y3
1A3
2OE
EN
8
2A1
2A2
2A3
2A4
11
9
13
7
15
5
17
3
1Y2
1Y4
6
19
1Y1
12
1Y4
1A4
2Y1
2Y2
2Y3
19
2OE
2Y4
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for DB, DW, J, PW, and W packages.
11
9
13
7
15
5
17
3
2Y1
2A1
2A2
2Y2
2Y3
2A3
2A4
2Y4
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 35 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 70 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 3): DB package . . . . . . . . . . . . . . . . . . . 0.6 W
DW package . . . . . . . . . . . . . . . . . . 1.6 W
PW package . . . . . . . . . . . . . . . . . . . 0.7 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 7 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54LV240, SN74LV240
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS193B – FEBRUARY 1993 – REVISED APRIL 1996
recommended operating conditions (see Note 4)
SN54LV240
VCC
Supply voltage
MAX
MIN
MAX
2.7
5.5
2.7
5.5
VIH
High level input voltage
High-level
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VIL
Low level input voltage
Low-level
VCC = 2.7 V to 3.6 V
VCC = 2.7 V to 3.6 V
VI
VO
Input voltage
0
Output voltage
0
IOH
High level output current
High-level
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
IOL
Low level output current
Low-level
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
∆t /∆v
Input transition rise or fall rate
TA
Operating free-air temperature
NOTE 4: Unused inputs must be held high or low to prevent them from floating.
SN74LV240
MIN
2
2
3.15
3.15
0.8
0.8
1.65
0
0
V
V
1.65
VCC
VCC
UNIT
VCC
VCC
–8
–8
–16
–16
8
8
16
16
V
V
V
mA
mA
0
100
0
100
ns / V
–55
125
–40
85
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VOH
VOL
TEST CONDITIONS
VCC†
IOH = – 100 µA
IOH = – 8 mA
MIN to MAX
IOH = – 16 mA
IOL = 100 µA
4.5 V
3V
SN54LV240
MIN
TYP
II
VI = VCC or GND
IOZ
VO = VCC or GND
ICC
VI = VCC or GND,
GND
nICC
One input at VCC – 0.6 V,
Other inputs at VCC or GND
Ci
VI = VCC or GND
Co
VO = VCC or GND
IO = 0
MIN
TYP
VCC – 0.2
2.4
VCC – 0.2
2.4
3.6
3.6
MIN to MAX
IOL = 8 mA
IOL = 16 mA
SN74LV240
MAX
MAX
UNIT
V
0.2
0.2
3V
0.4
0.4
4.5 V
0.55
0.55
3.6 V
±1
±1
5.5 V
±1
±1
3.6 V
±5
±5
5.5 V
±5
±5
3.6 V
20
20
5.5 V
20
20
3 V to 3.6 V
500
500
3.3 V
3
3
5V
3
3
3.3 V
8
8
5V
8
8
V
µA
µA
µA
µA
pF
pF
† For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN54LV240, SN74LV240
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS193B – FEBRUARY 1993 – REVISED APRIL 1996
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
SN54LV240
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
7
13
9
16
18
ns
ten
OE
Y
11
18
14
24
28
ns
tdis
OE
Y
12
23
14
24
25
ns
PARAMETER
VCC = 5 V ± 0.5 V
MIN
TYP
MAX
VCC = 3.3 V ± 0.3 V
MIN
TYP
MAX
VCC = 2.7 V
MIN
MAX
UNIT
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
SN74LV240
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
ten
OE
tdis
OE
VCC = 5 V ± 0.5 V
MIN
TYP
MAX
VCC = 3.3 V ± 0.3 V
MIN
TYP
MAX
VCC = 2.7 V
MIN
MAX
UNIT
7
13
9
16
18
ns
Y
11
18
14
24
28
ns
Y
12
23
14
24
25
ns
operating characteristics, VCC = 3.3 V, TA = 25°C
PARAMETER
TEST CONDITIONS
Outputs enabled
Cpd
Power dissi
dissipation
ation ca
capacitance
acitance per
er buffer/driver
Outputs disabled
Outputs enabled
33V
3.3
CL = 50 pF
F,
Outputs disabled
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303
VCC
• DALLAS, TEXAS 75265
f = 10 MHz
5V
TYP
UNIT
45
2.5
78
3
pF
F
SN54LV240, SN74LV240
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS193B – FEBRUARY 1993 – REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
S1
1 kΩ
From Output
Under Test
Vz
Open
GND
CL = 50 pF
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
Vz
GND
1 kΩ
WAVEFORM
CONDITION
Vm
Vi
Vz
LOAD CIRCUIT
VCC = 4.5 V
to 5.5 V
0.5 × VCC
VCC
2 × VCC
VCC = 2.7 V
to 3.6 V
1.5 V
2.7 V
6V
Vi
Vm
Timing Input
0V
tw
tsu
Vi
Input
Vm
th
Vi
Vm
Vm
Data Input
Vm
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Vi
Vm
Input
0V
VOH
Vm
Output
Vm
VOL
Output
VOH
Vm
0V
Vm
VOL
tPLZ
Output
Waveform 1
S1 at Vz
(see Note B)
tPLH
tPHL
Vm
Vm
tPZL
tPHL
tPLH
Vi
Output
Control
Vm
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Vm
tPZH
0.5 × Vz
VOL + 0.3 V
VOL
tPHZ
Vm
VOH – 0.3 V
VOH
[0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jun-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
SN74LV240DBLE
OBSOLETE
SSOP
DB
20
TBD
Call TI
Call TI
SN74LV240DW
OBSOLETE
SOIC
DW
20
TBD
Call TI
Call TI
SN74LV240DWR
OBSOLETE
SOIC
DW
20
TBD
Call TI
Call TI
SN74LV240PWLE
OBSOLETE
TSSOP
PW
20
TBD
Call TI
Call TI
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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