54ACT16623, 74ACT16623 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS152A – JANUARY 1991 – REVISED APRIL 1996 D D D D D D Members of the Texas Instruments Widebus Family Inputs are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-µm Process Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Packages Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings description The ’ACT16623 are 16-bit transceivers designed for asynchronous two-way communication between data buses. The control-function implementation allows for maximum flexibility in timing. These devices can be used as two 8-bit transceivers or one 16-bit transceiver. They allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the output-enable (OEBA and OEAB) inputs. The output-enable inputs can be used to disable the device so that the buses are effectively isolated. 54ACT16623 . . . WD PACKAGE 75ACT16623 . . . DL PACKAGE (TOP VIEW) 1OEAB 1B1 1B2 GND 1B3 1B4 VCC 1B5 1B6 GND 1B7 1B8 2B1 2B2 GND 2B3 2B4 VCC 2B5 2B6 GND 2B7 2B8 2OEAB 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1OEBA 1A1 1A2 GND 1A3 1A4 VCC 1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 VCC 2A5 2A6 GND 2A7 2A8 2OEBA The dual-enable configuration gives the bus transceiver the capability to store data by simultaneously enabling OEBA and OEAB. Each output reinforces its input in this transceiver configuration. When both control inputs are enabled and all other data sources to the two sets of bus lines are at high impedance, the bus lines remain at their last states. The 74ACT16623 is packaged in TI’s shrink small-outline package, which provides twice the functionality of standard small-outline packages in the same printed-circuit-board area. The 54ACT16623 is characterized for operation over the full military temperature range of –55°C to 125°C. The 74ACT16623 is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated. Copyright 1996, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 54ACT16623, 74ACT16623 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS152A – JANUARY 1991 – REVISED APRIL 1996 FUNCTION TABLE (each 8-bit section) INPUTS OPERATION OEBA OEAB L L B data to A bus H H A data to B bus H L Isolation H B data to A bus, A data to B bus L logic symbol† 1OEBA 1OEAB 2OEBA 2OEAB 1A1 48 1 25 24 47 EN1 EN2 EN3 EN4 1 1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 3 44 5 43 6 41 8 40 9 38 11 37 12 36 13 3 2A3 2A4 2A5 2A6 2A7 2A8 1 35 14 33 16 32 17 30 19 29 20 27 22 26 23 POST OFFICE BOX 655303 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 4 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2 1B1 2 46 1 2A2 2 1 • DALLAS, TEXAS 75265 2B2 2B3 2B4 2B5 2B6 2B7 2B8 54ACT16623, 74ACT16623 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS152A – JANUARY 1991 – REVISED APRIL 1996 logic diagram (positive logic) 1OEBA 1OEAB 1A1 48 2OEBA 1 2OEAB 25 24 36 47 2A1 2 13 1B1 2B1 To Seven Other Channels To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±400 mA Maximum power package dissipation at TA = 55°C (in still air) (see Note 2): DL package . . . . . . . . . . . 1.2 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. recommended operating conditions (see Note 3) 54ACT16623 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 VCC VIH Supply voltage (see Note 4) VIL VI Low-level input voltage Input voltage 0 VO IOH Output voltage 0 High-level output current IOL ∆t/∆v Low-level output current High-level input voltage 74ACT16623 2 2 0.8 Input transition rise or fall rate 0 UNIT V V 0.8 V VCC VCC V –24 –24 mA 24 24 mA 10 ns/V 85 °C VCC VCC 10 0 0 0 TA Operating free-air temperature –55 125 –40 NOTES: 3. Unused inputs should be connected to VCC through a pullup resistor of approximately 5 kΩ or greater. 4. All VCC and GND pins must be connected to the proper power supply. V PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 54ACT16623, 74ACT16623 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS152A – JANUARY 1991 – REVISED APRIL 1996 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 4.5 V IOH = –50 50 µA VOH 24 mA IOH = –24 IOH = –75 mA† TA = 25°C TYP MAX MIN 74ACT16623 MAX MIN 4.4 4.4 5.5 V 5.4 5.4 5.4 4.5 V 3.94 3.8 3.8 5.5 V 4.94 4.5 V IOL = 24 mA 54ACT16623 4.4 5.5 V IOL = 50 µA VOL MIN 4.8 4.8 3.85 3.85 0.1 0.1 MAX UNIT V 0.1 5.5 V 0.1 0.1 0.1 4.5 V 0.36 0.44 0.44 5.5 V 0.36 0.44 0.44 1.65 1.65 ±1 ±1 µA V II Control inputs IOL = 75 mA† VI = VCC or GND IOZ ICC A or B ports VO = VCC or GND 5.5 V ±0.5 ±5 ±5 µA VI = VCC or GND, IO = 0 One input at 3.4 V, Other inputs at VCC or GND 5.5 V 8 80 80 µA 5.5 V 0.9 1 1 mA ∆ICC‡ Ci Control inputs Cio A or B ports VI = VCC or GND VO = VCC or GND 5.5 V 5.5 V ±0.1 5V 4.5 pF 5V 16 pF † Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. ‡ For I/O ports, the parameter IOZ includes the input leakage current. switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A or B B or A tPZH tPZL OEBA A tPHZ tPLZ OEBA A tPZH tPZL OEAB B tPHZ tPLZ OEAB B MIN TA = 25°C TYP MAX 54ACT16623 74ACT16623 MIN MAX MIN MAX 4.2 7.3 9.5 4.2 10.4 4.2 10.4 3.1 7.3 9.5 3.1 10.3 3.1 10.3 2.7 6.8 8.8 2.7 9.5 2.7 9.5 3.5 8.2 10.2 3.5 11.1 3.5 11.1 6 9.6 11.3 6 12 6 12 5.3 8.6 10.3 5.3 10.7 5.3 10.7 4.1 6.9 8.7 4.1 9.3 4.1 9.3 5.1 7.9 9.7 5.1 10.6 5.1 10.6 5.1 8.2 10.2 5.1 10.4 5.1 10.4 4.4 7.4 9.3 4.4 9.5 4.4 9.5 UNIT ns ns ns ns ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd d Power dissipation capacitance per transceiver TEST CONDITIONS Outputs enabled Outputs disabled PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CL = 50 pF, pF f = 1 MHz TYP 56 11 UNIT pF 54ACT16623, 74ACT16623 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS152A – JANUARY 1991 – REVISED APRIL 1996 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 500 Ω From Output Under Test Open GND LOAD CIRCUIT Output Control (low-level enabling) 3V 1.5 V 1.5 V 0V tPLH tPHL VOH Output S1 Open 2 × VCC GND 500 Ω CL = 50 pF (see Note A) Input TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 50% VCC 50% VCC VOL 3V 0V tPZL [ VCC tPLZ Output Waveform 1 S1 at 2 × VCC (see Note B) Output Waveform 2 S1 at GND (see Note B) 1.5 V 1.5 V 50% VCC VOL tPHZ tPZH VOLTAGE WAVEFORMS 20% VCC 50% VCC 80% VCC VOH [0V VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 24-Jun-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 74ACT16623DL ACTIVE SSOP DL 48 74ACT16623DLR ACTIVE SSOP DL 48 25 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. 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