TI SN74ALVCH162721

SN74ALVCH162721
3.3-V 20-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES055E – DECEMBER 1995 – REVISED JUNE 1999
D
D
D
D
D
D
D
DGG OR DL PACKAGE
(TOP VIEW)
Member of the Texas Instruments
Widebus  Family
EPIC  (Enhanced-Performance Implanted
CMOS) Submicron Process
Output Ports Have Equivalent 26-Ω Series
Resistors, So No External Resistors Are
Required
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
OE
Q1
Q2
GND
Q3
Q4
VCC
Q5
Q6
Q7
GND
Q8
Q9
Q10
Q11
Q12
Q13
GND
Q14
Q15
Q16
VCC
Q17
Q18
GND
Q19
Q20
NC
NOTE: For tape and reel order entry:
The DGGR package is abbreviated to GR.
description
This 20-bit flip-flop is designed for low-voltage
1.65-V to 3.6-V VCC operation.
The 20 flip-flops of the SN74ALVCH162721 are
edge-triggered D-type flip-flops with qualified
clock storage. On the positive transition of the
clock (CLK) input, the device provides true data at
the Q outputs if the clock-enable (CLKEN) input is
low. If CLKEN is high, no data is stored.
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
CLK
D1
D2
GND
D3
D4
VCC
D5
D6
D7
GND
D8
D9
D10
D11
D12
D13
GND
D14
D15
D16
VCC
D17
D18
GND
D19
D20
CLKEN
A buffered output-enable (OE) input places the 20
NC – No internal connection
outputs in either a normal logic state (high or low
level) or the high-impedance state. In the
high-impedance state, the outputs neither load
nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive
bus lines without interface or pullup components. OE does not affect the internal operation of the flip-flops. Old
data can be retained or new data can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω resistors to reduce overshoot and
undershoot.
The SN74ALVCH162721 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright  1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
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1
SN74ALVCH162721
3.3-V 20-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES055E – DECEMBER 1995 – REVISED JUNE 1999
FUNCTION TABLE
(each flip-flop)
INPUTS
D
OUTPUT
Q
X
X
Q0
↑
H
H
OE
CLKEN
CLK
L
H
L
L
L
L
↑
L
L
L
L
L or H
X
Q0
H
X
X
X
Z
logic diagram (positive logic)
1
OE
56
CLK
29
CE
CLKEN
C1
D1
55
1D
2
Q1
To 19 Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
2
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SN74ALVCH162721
3.3-V 20-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES055E – DECEMBER 1995 – REVISED JUNE 1999
recommended operating conditions (see Note 4)
VCC
Supply voltage
VIH
High-level input voltage
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
MIN
MAX
1.65
3.6
2
0.35 × VCC
VI
VO
Input voltage
0
Output voltage
0
IOL
∆t/∆v
0.7
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
Low level output current
Low-level
V
1.7
Low-level input voltage
High level output current
High-level
V
0.8
VCC
VCC
VCC = 1.65 V
VCC = 2.3 V
–2
VCC = 2.7 V
VCC = 3 V
–8
–6
V
V
mA
–12
VCC = 1.65 V
VCC = 2.3 V
2
VCC = 2.7 V
VCC = 3 V
8
Input transition rise or fall rate
V
0.65 × VCC
VIL
IOH
UNIT
6
mA
12
10
ns/V
TA
Operating free-air temperature
–40
85
°C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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3
SN74ALVCH162721
3.3-V 20-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES055E – DECEMBER 1995 – REVISED JUNE 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.65 V to 3.6 V
IOH = –100 µA
IOH = –2 mA
IOH = –4 mA
VOH
6 mA
IOH = –6
II(hold)
(
)
2.3 V
1.9
2.3 V
1.7
MAX
2.4
2
3V
2
IOL = 100 µA
IOL = 2 mA
1.65 V to 3.6 V
0.2
1.65 V
0.45
IOL = 6 mA
VI = VCC or GND
VI = 0.58 V
2.3 V
0.4
2.3 V
0.55
3V
0.55
2.7 V
0.6
3V
0.8
±5
3.6 V
1.65 V
25
VI = 1.07 V
VI = 0.7 V
1.65 V
–25
2.3 V
45
VI = 1.7 V
VI = 0.8 V
2.3 V
–45
3V
75
3V
–75
IOZ
ICC
VO = VCC or GND
VI = VCC or GND,
∆ICC
Ci
One input at VCC – 0.6 V,
IO = 0
Other inputs at VCC or GND
VI = VCC or GND
VO = VCC or GND
UNIT
V
3V
VI = 2 V
VI = 0 to 3.6 V‡
Co
1.65 V
VCC–0.2
1.2
2.7 V
IOL = 8 mA
IOL = 12 mA
II
TYP†
IOH = –8 mA
IOH = –12 mA
IOL = 4 mA
VOL
MIN
V
µA
µA
3.6 V
±500
3.6 V
±10
µA
3.6 V
40
µA
3 V to 3.6 V
750
µA
3.3 V
3.5
3.3 V
7
pF
pF
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 1 through 3)
VCC = 1.8 V
MIN
fclock
tw
Clock frequency
Set p time
Setup
th
Hold time
MIN
MIN
150
MAX
VCC = 3.3 V
± 0.3 V
MIN
150
3.3
3.3
3.3
§
4
3.6
3.1
CLKEN before CLK↑
§
3.4
3.1
2.7
Data after CLK↑
§
0
0
0
CLKEN after CLK↑
§
0
0
0
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UNIT
MAX
150
Data before CLK↑
§ This information was not available at the time of publication.
4
MAX
VCC = 2.7 V
§
Pulse duration, CLK high or low
tsu
MAX
§
VCC = 2.5 V
± 0.2 V
MHz
ns
ns
ns
SN74ALVCH162721
3.3-V 20-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES055E – DECEMBER 1995 – REVISED JUNE 1999
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
FROM
(INPUT)
PARAMETER
fmax
tpd
CLK
ten
OE
VCC = 1.8 V
TO
(OUTPUT)
MIN
†
TYP
VCC = 2.5 V
± 0.2 V
MIN
MAX
150
VCC = 2.7 V
MIN
MAX
150
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
150
MHz
Q
†
1
6.7
6.2
1
5.3
ns
Q
†
1
7.2
7
1
5.8
ns
†
1
6.3
5.4
1
5
ns
tdis
Q
OE
† This information was not available at the time of publication.
operating characteristics, TA = 25°C
PARAMETER
Cpd
d
Power dissipation
capacitance
TEST CONDITIONS
Outputs enabled
Outputs disabled
CL = 50 pF,
pF
VCC = 1.8 V
TYP
†
f = 10 MHz
†
VCC = 2.5 V
TYP
VCC = 3.3 V
TYP
55
59
46
49
UNIT
pF
† This information was not available at the time of publication.
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5
SN74ALVCH162721
3.3-V 20-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES055E – DECEMBER 1995 – REVISED JUNE 1999
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V
2 × VCC
S1
1 kΩ
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
1 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
6
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SN74ALVCH162721
3.3-V 20-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES055E – DECEMBER 1995 – REVISED JUNE 1999
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
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SN74ALVCH162721
3.3-V 20-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES055E – DECEMBER 1995 – REVISED JUNE 1999
PARAMETER MEASUREMENT INFORMATION
VCC = 2.7 V AND 3.3 V ± 0.3 V
6V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
LOAD CIRCUIT
tw
2.7 V
2.7 V
Timing
Input
1.5 V
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V
0V
tPLH
Output
Output
Control
(low-level
enabling)
2.7 V
1.5 V
1.5 V
0V
tPZL
2.7 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
th
2.7 V
Data
Input
1.5 V
0V
0V
tsu
Input
1.5 V
Input
Output
Waveform 1
S1 at 6 V
(see Note B)
3V
1.5 V
VOL + 0.3 V
tPZH
tPHL
VOH
1.5 V
tPLZ
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Output
Waveform 2
S1 at GND
(see Note B)
VOL
tPHZ
1.5 V
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
8
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Copyright  1999, Texas Instruments Incorporated