HV20420 HV20620 Low Charge Injection 8-Channel High Voltage Analog Switch Ordering Information Package Options VPP – VNN 28-pin plastic DIP 28-lead plastic chip carrier Die 200V HV20420P HV20420PJ HV20420X 200V – HV20620PJ – Features General Description ■ HVCMOS technology for high performance Not recommended for new designs. Please use HV202 instead. ■ Low charge injection This device is a low charge injection 8-channel high-voltage analog switch integrated circuit (IC) intended for use in applications requiring high voltage switching controlled by low voltage control signals, such as ultrasound imaging and printers. Input data is shifted into an 8-bit shift register which can then be retained in an 8-bit latch. To reduce any possible clock feedthrough noise, Latch Enable Bar (LE) should be left high until all bits are clocked in. Using HVCMOS technology, this switch combines high voltage bilateral DMOS switches and low power CMOS logic to provide efficient control of high voltage analog signals. ® ■ Very low quiescent power dissipation – 10µA ■ Output On-resistance typically 22 ohms ■ Low parasitic capacitances ■ DC to 10MHz analog signal frequency ■ -60dB typical output off isolation at 5MHz ■ CMOS logic circuitry for low power ■ Excellent noise immunity This IC is suitable for various combinations of high voltage supplies, e.g., VPP/VNN : +50V/–150V, or +100V/–100V. ■ On-chip shift register, latch and clear logic circuitry ■ Flexible high voltage supplies The specifications for the HV204 and HV206 are identical except that the pinouts in the 28-lead plastic chip carrier are different. ■ Surface mount package available Absolute Maximum Ratings* VDD Logic power supply voltage VPP - VNN Supply voltage VPP Positive high voltage supply VNN Negative high voltage supply Logic input voltages Analog Signal Range Peak analog signal current/channel Storage temperature Power dissipation -0.5V to +18V 220V -0.5V to VNN +200V +0.5V to -200V -0.5V to VDD +0.3V VNN to VPP 3.0A -65°C to +150°C 1.2W * Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. 13-32 HV20420/HV20620 Electrical Characteristics DC Characteristics (over recommended operating conditions unless otherwise noted) 0°C Characteristics Small Signal Switch (ON) Resistance Sym min RONS Small Signal Switch (ON) Resistance Matching ∆RONS Large Signal Switch (ON) Resistance RONL Switch Off Leakage Per Switch ISOL +70°C +25°C max 30 min typ 26 max 32 min max 35 25 22 27 32 25 22 27 30 18 18 20 23 20 5.0 20 20 15 Units Test Conditions ISIG = 5mA VPP = + 50V, ISIG = 200mA VNN = -150V ohms ISIG = 5mA VPP = +100V, ISIG = 200mA VNN = -100V % ohms ISW = 5mA, VPP = +100V, VNN = -100V VSIG = VPP - 10V, ISIG = 1.0A 5.0 1.0 10 15 µA VSIG = VPP - 10V to VNN +10V DC Offset Switch Off 300 100 300 300 mV RL = 100KΩ DC Offset Switch On 500 100 500 500 mV RL = 100KΩ Pos. HV Supply Current IPPQ 10 50 µA ALL SWs OFF Neg. HV Supply Current INNQ -10 -50 µA ALL SWs OFF Pos. HV Supply Current IPPQ 10 50 µA ALL SWs ON ISW = 5mA Neg. HV Supply Current INNQ -10 -50 µA ALL SWs ON ISW = 5mA 3.0 2.0 Switch Output Peak Current Output Switch Frequency 3.0 50 fSW 8.1 IPP Supply Current 2.0 IPP A KHz 8.8 VSIG duty cycle ≤ 0.1% Duty Cycle = 50% VPP = +50V, VNN = -150V 10.0 5.0 6.3 6.9 mA VPP = +100V, VNN = -100V 8.1 8.8 10.0 6.3 6.9 mA VPP = +100V, VNN = -100V 6.0 6.0 mA fCLK = 3MHz 10 10 µA VPP = +50V, VNN = -150V 50KHz Output Switching Frequency with no load INN Supply Current INN 5.0 Logic Supply Average Current IDD 6.0 Logic Supply Quiescent Current IDDQ 10 Data Out Source Current ISOR 0.45 0.45 0.70 0.40 mA VOUT = VDD - 0.7V Data Out Sink Current ISINK 0.45 0.45 0.70 0.40 mA VOUT = 0.7V Logic Input Capacitance CIN 4.0 10 10 13-33 10 pF 13 HV20420/HV20620 Electrical Characteristics AC Characteristics (over operating conditions VDD = 15V, unless otherwise noted) 0°C Characteristics Sym Time to Turn Off VSIG* min max min tSIG(OFF) +25°C typ max min +70°C max 0 Units Test Condition ns Set Up Time Before LE Rises tSD 150 150 150 ns Time Width of LE tWLE 150 150 150 ns Clock Delay Time to Data Out tDO Time Width of CL tWCL 150 150 Set Up Time Data to Clock tSU 15 15 Hold Time Data from Clock tH 35 35 175 175 8.0 190 ns 150 ns 20 ns 35 ns Clock Freq fCLK 5.0 5.0 5.0 MHz 50% duty cycle fDATA = fCLK/2 Turn On Time tON 5.0 5.0 5.0 µs VSIG = VPP - 10V Turn Off Time tOFF 5.0 5.0 5.0 µs VSIG = VPP - 10V Maximum VSIG Slew Rate dv/dt VPP = +50V VNN = -150V 13 13 Off Isolation V/ns -30 -30 -33 -30 dB f = 5.0 MHz, 1KΩ//15pF load -45 -45 -60 -45 dB f = 5MHz, 50Ω load -60 -60 -70 -60 dB f = 5MHz, 50Ω load 300 mA 300ns pulse width, 2.0% duty cycle KO Switch Crosstalk KCR Output Switch Isolation Diode Current VPP = +100V VNN = -100V 300 IID 300 Off Capacitance SW to GND CSG(OFF) 5.0 17 5.0 12 17 5.0 17 pF 0V, 1MHz On Capacitance SW to GND CSG(ON) 25 50 25 38 50 25 50 pF 0V, 1MHz Output Voltage Spike +VSPK mV VPP = +100V VNN = -100V RL = 50Ω 150 150 -VSPK *Time required for analog signal to turn off before output switch turns off. Operating Conditions* Symbol Parameter Value VDD voltage1,3 10.0V to 15.5 V VPP Logic power supply Positive high voltage supply1,3 50V to VNN+ 200V supply1,3 VNN Negative high voltage VIH High-level input voltage VIL Low-level input voltage -100V to -150V VDD -2V to VDD 0V to 2.0V peak2 VSIG Analog signal voltage peak to TA Operating free air-temperature VNN +10V to VPP -10V 0°C to 70°C Notes: 1 Power up/down sequence is arbitrary except GND must be powered-up first and powered-down last. 2 VSIG must be VNN ≤ VSIG ≤ VPP or floating during power up/down transistion. 3 Rise and fall times of power supplies VDD, VPP, and VNN should not be less than 1.0msec. 13-34 HV20420/HV20620 Truth Table D0 D1 D2 D3 D4 D5 D6 D7 LE CL SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 L L L L L L L L L L L L L L L L L H OFF ON L H X X L L L L L L L L L L L L L L L L H X L H L H L H L H L H L H L H X X X X X X X X X X X X X X Notes: 1. The eight switches operate independently. 2. Serial data is clocked in on the L→ H transition CLK. OFF ON 3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data flows through the latch. OFF ON OFF ON 4. DOUT is high when switch 7 is on. OFF ON 5. Shift register clocking has no effect on the switch states if LE is H. OFF ON 6. The clear input overrides all other inputs. OFF ON OFF ON HOLD PREVIOUS STATE OFF OFF OFF OFF OFF OFF OFF OFF Test Circuits VPP –10V VPP –10 RL ISOL 10KΩ VOUT VOUT 100KΩ VNN +10 VPP VPP VDD VNN VNN GND 15V RL VPP VPP VDD VNN VNN GND Switch OFF Leakage 15V VPP VPP VDD VNN VNN GND DC Offset ON/OFF 15V 13 TON /TOFF Test Circuit +VSPK VIN = 10 VP–P @5MHz VIN = 10 VP–P @5MHz VOUT –VSPK 50Ω 50Ω VOUT NC RL 50Ω 1K VPP VPP VDD VNN VNN GND KO = 20Log 15V VPP VPP VDD VNN VNN GND VOUT VIN OFF Isolation 15V VPP VPP VDD VNN VNN GND KCR = 20Log Output Voltage Spike 13-35 VOUT VIN Crosstalk 15V HV20420/HV20620 Logic Timing Waveforms DN – 1 DN DATA IN 50% LE 50% DN + 1 50% 50% tWLE tSD 50% CLOCK 50% tSU th tDO DATA OUT 50% tOFF VOUT (TYP) OFF tON 90% 10% ON 50% CLR 50% tWCL Logic Diagram LATCHES LEVEL SHIFTERS OUTPUT SWITCHES DIN D LE CL SW0 CLK D LE CL SW1 D LE CL SW2 D LE CL SW3 D LE CL SW4 D LE CL SW5 D LE CL SW6 D LE CL SW7 8 BIT SHIFT REGISTER DOUT VNN VPP CL VDD LE 13-36 HV20420/HV20620 Pin Configurations HV204 28-Pin DIP Pin Function 1 SW3 2 SW3 3 SW2 4 SW2 5 SW1 6 SW1 7 SW0 8 SW0 9 N/C 10 VPP 11 N/C 12 VNN 13 GND 14 VDD Pin 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Function N/C DIN CLK LE CL DOUT SW7 SW7 SW6 SW6 SW5 SW5 SW4 SW4 Package Outlines HV204 28-Pin J-Lead Pin Function 1 SW3 2 SW3 3 SW2 4 SW2 5 SW1 6 SW1 7 SW0 8 SW0 9 N/C 10 VPP 11 N/C 12 VNN 13 GND 14 VDD Pin 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Function N/C DIN CLK LE CL DOUT SW7 SW7 SW6 SW6 SW5 SW5 SW4 SW4 1 28 2 27 3 26 4 25 5 24 23 6 7 HV204 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 top view 28-pin DIP 25 HV206 28-Pin J-Lead Pin Function 1 SW3 2 SW3 3 SW2 4 SW2 5 SW1 6 SW1 7 SW0 8 SW0 9 N/C 10 VPP 11 N/C 12 VNN 13 N/C 14 GND Pin 15 16 17 18 19 20 21 22 23 24 25 26 27 28 24 23 22 21 20 19 26 Function VDD DIN CLK LE CL DOUT SW7 SW7 SW6 SW6 SW5 SW5 SW4 SW4 27 18 HV204, HV206 17 28 16 1 15 2 14 3 13 4 12 5 6 7 8 9 10 top view 28-pin J-Lead Package 13-37 11 13