HV220/HV20220/HV20320 Low Charge Injection 8-Channel High Voltage Analog Switches Features General Description These devices are low charge injection 8-channel high-voltage analog switch integrated circuits (ICs) intended for use in applications requiring high voltage switching controlled by low voltage control signals, such as ultrasound imaging and printers. Input data is shifted into an 8-bit shift register which can then be retained in an 8-bit latch. To reduce any possible clock feed-through noise, Latch Enable Bar (LE) should be left high until all bits are clocked in. Using HVCMOS technology, these switches combine high voltage bilateral DMOS switches and low power CMOS logic to provide efficient control of high voltage analog signals. HVCMOS® technology for high performance Very low quiescent power dissipation – 10µA Output on-resistance typically 22 ohms Low parasitic capacitances DC to 10MHz analog signal frequency -60dB typical output off isolation at 5MHz CMOS logic circuitry for low power Excellent noise immunity On-chip shift register, latch and clear logic circuitry Flexible high voltage supplies These ICs are suitable for various combinations of high voltage supplies, e.g., VPP/VNN : +50V/–150V, or +100V/–100V.B Applications Medical ultrasound imaging Piezoelectric transducer drivers Block Diagram LATCHES LEVEL SHIFTERS OUTPUT SWITCHES D LE CL SW0 D LE CL SW1 D LE CL SW2 D LE CL SW3 D LE CL SW4 D LE CL SW5 D LE CL SW6 D LE CL SW7 DIN CLK 8-Bit Shift Register DOUT VDD LE CL V NN V PP HV220/HV20220/HV20320 Ordering Information Package Options Device 28-Lead PLCC 48-Lead LQFP/TQFP (1.4mm) - - HV220 HV20220 HV20320 HV220GA HV220GA-G HV20220PJ HV20220FG HV20220PJ-G HV20220FG-G HV20320PJ - HV20320PJ-G 25-Ball fpBGA - -G indicates the part is RoHS compliant (‘Green’) Product Marking Absolute Maximum Ratings Parameter Value VDD logic power supply voltage -0.5V to +15V Top Marking YYWW YY = Year Sealed WW = Week Sealed LLLLLLLLL L = Lot Number Bottom Marking C = Country of Origin* A = Assembler ID* = “Green” Packaging CCCCCCCC HV20220FG VPP - VNN supply voltage 220V VPP positive high voltage supply -0.5V to VNN +200V VNN negative high voltage supply +0.5V to -200V Logic input voltages -0.5V to VDD +0.3V Analog signal range VNN to VPP Peak analog signal current/channel AAA HV20220 FG 3.0A -65OC to +150OC Storage temperature Power dissipation: 28-Lead PLCC 48-Lead LQFP/ TQFP(1.4mm) 25-Ball fpBGA *May be part of top marking Top Marking YY = Year Sealed WW = Week Sealed L = Lot Number Bottom Marking C = Country of Origin* A = Assembler ID* = “Green” Packaging CCCCCCCCCCC YYWW 1.2W 1.0W 1.0W Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. HV20220PJ LLLLLLLLLL AAA *May be part of top marking HV20220 PJ Operating Conditions Top Marking Symbol Parameter Value VDD Logic power supply voltage 1,3 4.5V to 13.2V VPP positive high voltage supply 1,3 40V to VNN +200V 1,3 VNN negative high voltage supply VIH High level input voltage VDD -1.5V to VDD VIL Low-level input voltage 0V to 1.5V VSIG Analog signal voltage peak-to-peak VNN +10V to VPP -10V 2 Operating free air temperature 0OC to 70OC TA -40V to -160V Notes: 1. Power up/down sequence is arbtrary except GND must be powered -up first and powered down last. 2. VSIG must be VNN ≤ VSIG ≤ VPP or floating during power up/down transition. 3. Rise and fall times of power supplies VDD, VPP, and VNN should not be less than 1.0msec. 2 YY = Year Sealed WW = Week Sealed L = Lot Number Bottom Marking C = Country of Origin* A = Assembler ID* = “Green” Packaging CCCCCCCCCCC YYWW HV20320PJ LLLLLLLLLL AAA *May be part of top marking HV20320 PJ Top Marking YYWW HV220GA LLLLLLLLL YY = Year Sealed WW = Week Sealed L = Lot Number = “Green” Packaging HV20220 GA HV220/HV20220/HV20320 DC Electrical Characteristics (Over operating conditions unless otherwise specified ) 0OC Sym +25OC +70OC Parameter Units Conditions Min Max Min Typ Max Min Max - 30 - 26 38 - 48 ISIG = 5mA - 25 - 22 27 - 32 ISIG = 200mA - 25 - 22 27 - 30 - 18 - 18 24 - 27 - 23 - 20 25 - 30 ISIG = 5mA - 22 - 16 25 - 27 ISIG = 200mA Small signal switch on-resistance matching - 20 - 5.0 20 - 20 % ISIG = 5.0mA, VPP = +100V, VNN = - 100V RONL Large signal switch on-resistance - - - 15 - - - Ω VSIG = VPP -10V, ISIG = 1.0A ISOL Switch off leakage per switch - 5.0 - 1.0 10 - 15 μA VSIG = VPP -10V, VNN +10V DC offset switch off - 300 - 100 300 - 300 mV RL = 100Ω DC offset switch on - 500 - 100 500 - 500 mV RL = 100kΩ IPPQ Quiescent VPP supply current - - - 10 50 - - μA All switches off INNQ Quiescent VNN supply current - - - -10 -50 - - μA All switches off IPPQ Quiescent VPP supply current - - - 10 50 - - μA All switches on, ISW = 5.0mA INNQ Quiescent VNN supply current - - - -10 -50 - - μA All switches on, ISW = 5.0mA ISW Switch output peak current - 3.0 - 3.0 2.0 - 2.0 A VSIG duty cycly < 0.1% fSW Output switching frequency - - - - 50 - - kHz - 6.5 - - 7.0 - 8.0 - 4.0 - - 5.0 - 5.5 RONS ΔRONS VOS IPP INN Small signal switch on-resistance Supply current Supply curent Ω ISIG = 5mA ISIG = 200mA VPP = +40V VNN = -160V VPP = +100V VNN = -100V VPP = +160V VNN = -40V Duty cycle = 50% VPP = +40V VNN = -160V mA VPP = +100V VNN = -100V - 4.0 - - 5.0 - 5.5 VPP = +160V VNN = -40V - 6.5 - - 7.0 - 8.0 VPP = +40V VNN = -160V - 4.0 - - 5.0 - 5.5 - 4.0 - - 5.0 - 5.5 mA VPP = +100V VNN = -100V All output switches are turning On and Off at 50kHz with no load VPP = +160V VNN = -40V IDD Logic supply average current - 4.0 - - 4.0 - 4.0 mA fCLK = 5.0MHz, VDD = 5.0V IDDQ Logic supply Quiescent current - 10 - - 10 - 10 μA --- ISOR Data out source current 0.45 - 0.45 0.70 - 0.40 - mA VOUT = VDD -0.7V ISINK Data out sink current 0.45 - 0.45 0.70 - 0.40 - mA VOUT = 0.7V CIN Logic input capacitance - 10 - - 10 - 10 pF --- 3 HV220/HV20220/HV20320 AC Electrical Characteristics (Over recommended operating conditions: VDD = 5.0V, unless otherwise specified) 0OC Sym +25OC +70OC Parameter Units Min Max Min Typ Max Min Conditions Max tSD Set up time before LE rises 150 150 150 ns --- tWLE Time width of LE 150 150 150 ns --- tDO Clock delay time to data out ns --- tWCL Time width of CL 150 150 150 ns --- tSU Set up time data to clock 15 15 20 ns --- tH Hold time data from clock 35 35 35 ns --- 150 150 8.0 150 fCLK Clock frequency 5.0 5.0 5.0 MHz tR, tF Clock rise and fall times 50 50 50 ns --- tON Turn on time 5.0 5.0 5.0 μs VSIG = VPP -10V, RLOAD = 10kΩ tOFF Turn off time 5.0 5.0 5.0 μs VSIG = VPP -10V, RLOAD = 10kΩ 20 20 20 20 20 20 20 20 20 dv/dt Maximun VSIG slew rate KO Off isolation KCR Switch crosstalk -30 -30 -58 -58 -60 -60 -33 -30 -70 VPP = +160V, VNN = -40V V/ns -60 VPP = +100V, VNN = -100V VPP = +40V, VNN = -160V dB -58 50% Duty cycle, fDATA= fCLK/2 f = 5.0MHz, 1kΩ/15pF load f = 5.0MHz, 50Ω load dB f = 5.0MHz, 50Ω load 300 mA 300ns pulse width, 2.0% duty cycle IID Output switch isolation diode current CSG(OFF) Off capacitance SW to GND 5.0 17 5.0 12 17 5.0 17 pF 0V, f = 1.0MHz CSG(ON) On capacitance SW to GND 25 50 25 38 50 25 50 pF 0V, f = 1.0MHz +VSPK - - - - 150 - - -VSPK - - - - 150 - - - - - - 150 - - - - - - 150 - - +VSPK - - - - 150 - - -VSPK - - - - 150 - - - - - 820 - - - - - - 600 - - - - - - 350 - - - +VSPK -VSPK QC Output voltage spike Charge injection 300 300 4 VPP = +40V, VNN = -160V, RLOAD = 50Ω mV VPP = +100V, VNN = -100V, RLOAD = 50Ω VPP = +160V, VNN = -40V, RLOAD = 50Ω VPP = +40V, VNN = -160V, VSIG = 0V pC VPP = +100V, VNN = -100V, VSIG = 0V VPP = +160V, VNN = -40V, VSIG = 0V HV220/HV20220/HV20320 Truth Table D0 D1 D2 D3 D4 D5 D6 D7 LE CLR SW0 SW1 SW2 SW3 SW4 SW5 L L L Off H L L On L L L Off H L L On L L L Off H L L On L L L Off H L L On L L L Off H L L On L L L Off H L L On L L L Off H L L On L L L Off H L L On X X X X X X X X H L Hold Previous State X X X X X X X X X H All Switches Off SW6 SW7 Notes: 1. The eight switches operate independently. 2. Serial data is clocked in on the L to H transition of the CLK. 3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data flow through the latch. 4. DOUT is high when data in the shift register 7 is high. 5. Shift register clocking has no effect on the switch states if LE is high. 6. The CLR clear input overrides all other inputs. Logic Timing Waveforms DN+1 D DATA IN DN-1 N 50% 50% LE 50% 50% t WLE t SD CLOCK 50% t 50% t SU t DATA OUT DD 50% t VOUT OFF t ON OFF 90% (TYP) 10% ON 50% CLR h 50% t WCL 5 HV220/HV20220/HV20320 Test Circuits VPP -10V VPP -10V RL ISOL 10KΩ VOUT VOUT 100KΩ VNN +10V VPP VPP VDD VNN VNN GND 5V RL VPP VPP VDD VNN VNN GND Switch OFF Leakage 5V VPP VPP VDD VNN VNN GND DC Offset ON/OFF 5V TON /TOFF Test Circuit VIN = 10 VP-P @5MHz VIN = 10 VP-P @5MHz VSIG IID VOUT 50Ω NC VNN RL 50Ω VPP VPP VDD VNN VNN GND KO = 20Log 5V VPP VPP VDD VNN VNN GND 5V VPP VPP VDD VNN VNN GND VOUT VIN KCR = 20Log Isolation Diode Current OFF Isolation VOUT Crosstalk +VSPK VOUT VOUT -V SPK 1000pF 50Ω VSIG 1KΩ VPP VPP VDD VNN VNN GND 5V RL VPP VPP VDD VNN VNN GND Q = 1000pF x VOUT Charge Injection Output Voltage Spike 6 VOUT VIN 5V 5V HV220/HV20220/HV20320 Typical Performance Curves IDD vs Clock Frequency VDD = 5.0V, VPP/VNN = ±100V, TA = 0°C to 70°C Off-Isolation vs. Signal Voltage Frequency VDD = 5.0V, VPP/VNN = ±100V -80.0 3.0 -75.0 Off-Isolation (dB) IDD Current (mA) TA = 70°C 2.0 1.0 -70.0 -65.0 -60.0 TA = 0°C -55.0 -50.0 0.0 10 1000 100 1.0 10000 10.0 CLK Frequency (KHz) Signal Voltage Frequency (MHz) RON vs. Ambient Temperature TA RON vs. VPP/VNN VDD = 5.0V, VPP/VNN = ±100V VDD = 5.0V 40.0 50.0 TA = 125°C ISW = 5mA 40.0 RON (ohms) @5mA RON (ohms) 30.0 20.0 ISW = 200mA 10.0 TA = 85°C 30.0 TA = 25°C 20.0 TA = 0°C 10.0 0 0 -50 -25 0 25 50 75 100 125 150 Ambient Temperature (oC) VPP 40V 60V 80V 100V 120V 140V 160V VNN -160V -140V -120V -100V -80V -60V -40V TDO vs. Ambient Temperature TA IPP/INN vs. Output Switching Frequency VPP/VNN = ±100V VDD = 5.0V, VPP/VNN = ±100V 5 100 TA = 0oC IPP/INN Average Current (mA) VDD = 5.0V TDO (ns) 80 60 VDD = 13.5V 40 20 0 TA = 25oC 4 TA = 70oC TA = 125oC 3 2 1 0 -50 -25 0 25 50 75 100 0 125 25 50 75 100 125 Output Switching Frequency (KHz) Ambient Temp TA (°C) 7 150 HV220/HV20220/HV20320 Pin Description (HV220GA) Pin Description (48-Lead FG) Ball Location Function Pin Function Pin Function A3 SW1 1 SW5 25 VNN B2 SW2 2 N/C 26 N/C B3 SW1 3 SW4 27 N/C B4 SW0 B5 SW0 4 N/C 28 GND B6 VNN 5 SW4 29 VDD C1 SW3 6 N/C 30 N/C C2 SW3 7 N/C 31 N/C C3 SW2 8 SW3 32 N/C C4 VPP 9 N/C 33 DIN C5 GND 10 SW3 34 CLK C6 DIN 11 N/C 35 LE C7 VDD 12 SW2 36 CLR D1 SW4 13 N/C 37 DOUT D2 SW4 14 SW2 38 N/C D3 SW5 D4 SW7 15 N/C 39 SW7 D5 LE 16 SW1 40 N/C D6 CLK 17 N/C 41 SW7 E2 SW5 18 SW1 42 N/C E3 SW6 19 N/C 43 SW6 E4 SW7 20 SW0 44 N/C E5 DOUT 21 N/C 45 SW6 E6 CLR 22 SW0 46 N/C F3 SW6 23 N/C 47 SW5 24 VPP 48 N/C Pin Description (HV20320PJ) Pin Description (HV20220PJ) Pin Function Pin Function Pin Function Pin Function 1 SW3 15 N/C 1 SW3 15 N/C 2 SW3 16 DIN 2 SW3 16 DIN 3 SW2 17 CLK 3 SW2 17 CLK 4 SW2 18 LE 4 SW2 18 LE 5 SW1 19 CL 5 SW1 19 CL 6 SW1 20 DOUT 6 SW1 20 DOUT 7 SW0 21 SW7 7 SW0 21 SW7 8 SW0 22 SW7 8 SW0 22 SW7 9 N/C 23 SW6 9 VPP 23 SW6 10 VPP 24 SW6 10 VNN 24 SW6 11 N/C 25 SW5 11 N/C 25 SW5 12 VNN 26 SW5 12 GND 26 SW5 13 GND 27 SW4 13 VDD 27 SW4 14 VDD 28 SW4 14 N/C 28 SW4 8 HV220/HV20220/HV20320 48-Lead LQFP Package Outline (FG) 7x7mm body, 1.4mm height (min), 0.50mm pitch D D1 E E1 Note 1 (Index Area D1/4 x E1/4) Gauge Plane L2 48 L 1 Seating Plane θ L1 b e Top View View B View B A A2 Seating Plane A1 Side View Note 1: A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier may be either a mold, or an embedded metal or marked feature. Symbol MIN Dimension (mm) A A1 A2 b D D1 E E1 1.40 0.05 1.35 0.17 8.80 6.80 8.80 6.80 NOM - - 1.40 0.22 9.00 7.00 9.00 7.00 MAX 1.60 0.15 1.45 0.27 9.20 7.20 9.20 7.20 JEDEC Registration MS-026, Variation BBC, Issue D, Jan. 2001. Drawings not to scale. 9 e L L1 L2 1.00 REF 0.25 BSC 0O 0.45 0.50 BSC 0.60 0.75 θ 3.5O 7O HV220/HV20220/HV20320 HV220GA 25-Ball fpBGA (GA) Top View Bottom View Enlarged Side View Note: All dimensions are in millimeters 10 HV220/HV20220/HV20320 28-Lead PLCC Package Outline (PJ) .048/.042 x 45O D D1 1 4 .056/.042 x 45O 28 .150 MAX 26 Note 1 (Index Area) .075 MAX E1 E .020 MAX 3 Places Top View View B b1 A Base Plane A1 A2 .020 MIN Seating Plane e b Side View View B Note 1: A Pin 1 identifier must be located in the index area indicated.The Pin 1 identifier may be either a mold, or an embedded metal or marked feature. Symbol Dimension (inches) A A1 A2 b D D1 E E1 MIN .165 .090 .062 .013 .485 .450 .485 .450 NOM .172 .105 - - .490 .453 .490 .453 MAX .180 .120 .083 .021 .495 .456 .495 .456 e .050 BSC JEDEC Registration MS-018, Variation AB, Issue A, June, 1993. Drawings not to scale. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP - HV220_HV20220_HV20320 C073107 11