HV230/232 HV230/HV232 Low Charge Injection 8-Channel High Voltage Analog Switches with Bleed Resistors Features ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ General Description ® HVCMOS technology for high performance Very low quiescent power dissipation – 10µA Output On-resistance typically 22 ohms Integrated bleed resistors on the outputs Low parasitic capacitances DC to 10MHz analog signal frequency -60dB typical output off isolation at 5MHz CMOS logic circuitry for low power Excellent noise immunity On-chip shift register, latch and clear logic circuitry Flexible high voltage supplies The Supertex HV230 and HV232 are low charge injection 8-channel high-voltage analog switch integrated circuits (ICs) with bleed resistors. These devices can be used in applications requiring high voltage switching controlled by low voltage control signals, such as ultrasound imaging and printers. The bleed resistors eliminate voltage built up on capacitive loads such as piezoelectric transducers. Input data is shifted into an 8-bit shift register which can then be retained in an 8-bit latch. To reduce any possible clock feed-through noise, Latch Enable Bar (LE) should be left high until all bits are clocked in. Using HVCMOS technology, this switch combines high voltage bilateral DMOS switches and low power CMOS logic to provide efficient control of high voltage analog signals. Applications ❏ ❏ These ICs are suitable for various combinations of high voltage supplies, e.g., VPP/VNN : +50V/–150V, or +100V/–100V. Medical ultrasound imaging Piezoelectric transducer drivers Block Diagram LEVEL SHIFTERS LATCHES OUTPUT SWITCHES D LE CL SW0 D LE CL SW1 D LE CL SW2 D LE CL SW3 D LE CL SW4 D LE CL SW5 D LE CL SW6 D LE CL SW7 DIN CLK 8 BIT SHIFT REGISTER DOUT VDD LE CL V NN V PP 1 RGND NR032505 NR011705 HV230/232 Absolute Maximum Ratings* VDD Logic power supply voltage -0.5V to +15V VPP - VNN Supply voltage 220V VPP Positive high voltage supply -0.5V to VNN +200V VNN Negative high voltage supply Logic input voltages +0.5V to -200V -0.5V to VDD +0.3V Analog Signal Range VNN to VPP Peak analog signal current/channel Storage temperature 3.0A -65°C to +150°C Power dissipation: 28-lead PLCC 48-lead TQFP 26-lead TAPP 26-lead µ-BGA 1.2W 1.0W 1.0W 1.0W * Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Operating Conditions* Symbol VDD VPP Parameter Logic power supply Value voltage1, 3 Positive high voltage 4.5V to 13.2V supply1, 3 40V to VNN+ 200V supply1, 3 VNN Negative high voltage VIH High-level input voltage VDD -1.5V to VDD VIL Low-level input voltage 0V to 1.5V Analog signal voltage peak to peak VNN +10V to VPP -10V2 Operating free air-temperature 0°C to 70°C VSIG TA -40V to -160V Notes: 1 Power up/down sequence is arbitrary except GND must be powered-up first and powered-down last. 2 VSIG must be VNN - VSIG - VPP or floating during power up/down transistion. 3 Rise and fall times of power supplies VDD, VPP, and VNN should not be less than 1.0msec. Ordering Information Package Options 28-Lead plastic chip carrier HV232PJ - 48-Lead TQFP 26-lead TAPP 26-lead µ-BGA Die VPP - VNN HV232FG - HV232GA HV232X 200V - HV230TA - - 200V 2 NR032505 HV230/232 Truth Table D0 D1 D2 D3 D4 D5 D6 D7 LE CL SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 L L L L L L L L L L L L L L L L L H OFF ON L H X X L L L L L L L L L L L L L L L L H X L H L H L H L H L H L H L H X X X X X X X X X X X X X X OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON HOLD PREVIOUS STATE OFF OFF OFF OFF OFF OFF OFF OFF Notes: 1. The eight switches operate independently. 2. Serial data is clocked in on the L to H transition CLK. 3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data flows through the latch. 4. DOUT is high when data in shift register 7 is high. 5. Shift register clocking has no effect on the switch states if LE is H. 6. The clear input overrides all other inputs. 3 NR032505 HV230/232 Electrical Characteristics DC Characteristics (over recommended operating conditions unless otherwise noted) Characteristics Small Signal Switch (ON) Resistance Sym 0°C min max RONS Small Signal Switch (ON) Resistance Matching ∆RONS Large Signal Switch (ON) Resistance RONL Output Switch Shunt Resistance RINT Switch Off Leakage Per Switch ISOL +25°C typ* max 30 26 38 48 ISIG = 5mA 25 22 27 32 ISIG = 200mA VNN = -160V 25 22 27 30 18 18 24 27 ISIG = 200mA VNN = -100V 23 20 25 30 ISIG = 5mA 22 16 25 27 ISIG = 200mA VNN = -40V 20 5.0 20 20 min +70°C min max 15 20 Units Ω Test Conditions ISIG = 5mA VPP = 40V, VPP = 100V, VPP = 160V, % ISW = 5mA, VPP = 100V, VNN = -100V Ω VSIG = VPP - 10V, ISIG = 1A KΩ Output switch to RGND IRINT = 0.5mA 15 µA VSIG = VPP - 10V 300 300 mV No Load 100 500 500 mV No Load 35 50 5.0 1.0 10 DC Offset Switch Off 300 100 DC Offset Switch On 500 Pos. HV Supply Current IPPQ 10 50 µA ALL SWs OFF Neg. HV Supply Current INNQ -10 -50 µA ALL SWs OFF Pos. HV Supply Current IPPQ 10 50 µA ALL SWs ON, ISW = 5mA Neg. HV Supply Current INNQ -10 -50 µA ALL SWs ON, ISW = 5mA 3.0 2.0 A VSIG duty cycle - 0.1% Switch Output Peak Current Output Switch Frequency IPP Supply Current INN Supply Current 3.0 2.0 50 fSW IPP INN KHz Duty Cycle = 50% 6.5 7.0 8.0 VPP = 40V, VNN = -160V 4.0 5.0 5.5 4.0 5.0 5.5 VPP = 160V, VNN = -40V 6.5 7.0 8.0 VPP = 40V, VNN = -160V 4.0 5.0 5.5 4.0 5.0 5.5 mA mA VPP = 100V, VNN = -100V 50KHz Output Switching Frequency with no load VPP = 100V, VNN = -100V VPP = 160V, VNN = -40V Logic Supply Average Current IDD 4.0 4.0 4.0 mA Logic Supply Quiescent Current IDDQ 10 10 10 µA Data Out Source Current ISOR 0.45 0.45 0.70 0.40 mA VOUT = VDD - 0.7V Data Out Sink Current ISINK 0.45 0.45 0.70 0.40 mA VOUT = 0.7V Logic Input Capacitance CIN 10 10 10 fCLK = 5MHz, VDD = 5.0V pF *Typical values only for HV232 4 NR032505 HV230/232 Electrical Characteristics AC Characteristics (over operating conditions VDD = 5V, unless otherwise noted) Characteristics Sym 0°C min +25°C max min Set Up Time Before LE Rises tSD 150 Time Width of LE tWLE 150 Clock Delay Time to Data Out tDO 55 Time Width of CL tWCL 150 150 Set Up Time Data to Clock tSU 15 15 Hold Time Data from Clock th 35 35 typ* +70°C max 150 max 150 150 150 min 150 70 ns 150 150 8.0 Test Conditions ns 150 60 Units ns ns 20 ns 35 ns Clock Freq fCLK 5.0 5.0 5.0 MHz Clock Rise and Fall Times tr, tf 1.0 1.0 1.0 µs Turn On Time tON 5.0 5.0 5.0 µs VSIG = VPP -10V, RL = 10KΩ Turn Off Time tOFF 5.0 5.0 5.0 µs VSIG = VPP -10V, RL = 10KΩ 20 20 20 20 20 20 20 20 20 Maximum VSIG Slew Rate Off Isolation Switch Crosstalk Output Switch Isolation Diode Current dv/dt KO KCR -30 -30 -58 -58 -60 -60 -33 -70 300 IID 50% duty cycle fDATA = fCLK/2 VPP = 160V, VNN = -40V V/ns VPP = 100V, VNN = -100V VPP = 40V, VNN = -160V -30 dB f = 5MHz, 1KΩ//15pF load -58 dB f = 5MHz, 50Ω load -60 dB f = 5MHz, 50Ω load 300 mA 300ns pulse width, 2.0% duty cycle 300 Off Capacitance SW to GND CSG(OFF) 5.0 17 5.0 12 17 5.0 17 pF 0V, 1MHz On Capacitance SW to GND CSG(ON) 25 50 25 38 50 25 50 pF 0V, 1MHz *Typical values only for HV232 Electrical Characteristics AC Characteristics (over operating conditions VDD = 5V, unless otherwise noted) Characteristics Output Voltage Spike Sym +25°C min Units typ* max +VSPK 150 -VSPK 150 +VSPK 150 -VSPK 150 +VSPK 150 -VSPK 150 mV Test Conditions VPP = 40V, VNN = -160V, RL = 50Ω VPP = 100V, VNN = -100V, RL = 50Ω VPP = 160V, VNN = -40V, RL = 50Ω *Typical values only for HV232 5 NR032505 HV230/232 Test Circuits VPP –10V VPP –10V RL ISOL 10KΩ VOUT VOUT Open Open RGND RGND VPP VNN RGND VPP VDD VNN GND 5V VPP VPP VDD VNN VNN GND 5V VPP VPP VDD VNN VNN GND TON /TOFF Test Circuit DC Offset ON/OFF Switch OFF Leakage 5V VIN = 10 VP–P @5MHz VIN = 10 VP–P @5MHz VSIG IID VOUT 50Ω NC VNN RL 50Ω RGND RGND RGND VPP VPP VNN VNN VDD VPP 5V VNN GND KO = 20Log VPP 5V VDD VNN VDD VPP VPP VNN VNN GND GND VOUT VIN KCR = 20Log OFF Isolation Isolation Diode Current ∆VOUT 5V VOUT VIN Crosstalk +VSPK VOUT VOUT –VSPK 1000pF 50Ω RGND VSIG 1KΩ RGND VPP VPP VDD VNN VNN GND 5V RL VPP VPP VDD VNN VNN GND 5V Q = 1000pF x ∆VOUT Charge Injection Output Voltage Spike 6 NR032505 HV230/232 Logic Timing Waveforms DN-1 DN+1 DN DATA IN 50% 50% LE 50% 50% t WLE t SD CLOCK 50% 50% t t SU t DATA OUT DD 50% t VOUT OFF (TYP) h t ON OFF 90% 10% ON 50% CLR 50% t WCL Block Diagram LATCHES LEVEL SHIFTERS OUTPUT SWITCHES D LE CL SW0 D LE CL SW1 D LE CL SW2 D LE CL SW3 D LE CL SW4 D LE CL SW5 D LE CL SW6 D LE CL SW7 DIN CLK 8 BIT SHIFT REGISTER DOUT VDD LE CL V NN V PP RGND 7 NR032505 Pin Configurations HV232 28-Pin J-Lead Pin Function 1 SW3 2 SW3 3 SW2 4 SW2 5 SW1 6 SW1 7 SW0 8 SW0 9 N/C 10 VPP 11 RGND 12 VNN 13 GND 14 VDD HV232 48-Pin TQFP Pin Function 1 SW5 2 N/C 3 SW4 4 N/C 5 SW4 6 N/C 7 N/C 8 SW3 9 N/C 10 SW3 11 N/C 12 SW2 13 N/C 14 SW2 15 N/C 16 SW1 17 N/C 18 SW1 19 N/C 20 SW0 21 N/C 22 SW0 23 N/C 24 VPP Pin 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 HV230/232 Package Outlines 25 Function N/C DIN CLK LE CL DOUT SW7 SW7 SW6 SW6 SW5 SW5 SW4 SW4 24 23 22 21 20 19 26 18 27 17 28 16 1 15 2 14 3 13 4 12 5 6 7 8 9 10 11 Top View 28-Pin J-Lead Package Function VNN N/C RGND GND VDD N/C N/C N/C DIN CLK LE CLR DOUT N/C SW7 N/C SW7 N/C SW6 N/C SW6 N/C SW5 N/C Pin 1 Pin 12 Top View 48-Pin TQFP 8 NR032505 HV230/232 HV232GA Package Outline (µ-BGA) 6.00 ± 0.05 0.65 9 8 7 6 5 4 3 2 1 1 2.675 A B C E F 3 4 5 6 7 8 9 B 0.325 D AXIS "Y" 2 A C DIE 4.09 5.350 ± 0.05 DIE 4.65 A1 CORNER INDEX SIYYWW HV232GA AAAAAAA 3.00 D E F 0.65 G G H H LOT # DATUM AXIS "X" Notes: 1. Dimensioning and tolerance per ASME Y14.5M-1994. 2. Do not subject part to ultrasonic cleaning or intense UV. 3. Contact ball position per JESD 95-1, SPP-010. 4. Units are in millimeters. 0.323 ± 0.03 0.05 0.243 ± 0.03 0.99 ± 0.05 Polyimide Tape Adhesive Die Elastomer Seal 4 Sides/Edges Elastomer Lead ENLARGED VIEW 9 NR032505 HV230/232 µ-BGA Function Table Ball Location Function A4 SW1 C3 SW2 C4 SW1 C5 SW0 C6 VPP C7 VNN D1 SW3 D3 SW3 D4 SW2 D5 SW0 D6 RGND D7 GND D9 VDD E1 SW4 E3 SW4 E4 SW5 E5 SW7 E6 LE E7 CLK E9 DIN F3 SW5 F4 SW6 F5 SW7 F6 DOUT F7 CLR H4 SW6 10 NR032505 Pin Configuration HV230/232 Pad Diagram Pin # Function Pin # Function 1 SW4 14 VDD 2 SW3 15 DIN 10 9 8 7 6 5 4 3 11 3 SW3 16 CLK 12 4 SW2 17 LE bar 13 5 SW2 18 CLR 14 6 SW1 19 DOUT 15 7 SW1 20 SW7 8 SW0 21 SW7 9 S W0 22 S W6 17 10 V PP 23 SW6 18 11 VNN 24 SW5 12 RGND 25 SW5 13 GND 26 SW4 2 HV230TA (Top View) 16 1 19 20 21 22 23 24 25 26 Pad connections are on the backside of the package Package Dimensions 6.00 ± 0.10 1.050 0.400 0.100 ± 0.05 0.725 0.925 pin 2 0.650 6.00 ± 0.10 0.35 ± 0.05 4.150 pin 1 0.925 0.725 0.35 ± 0.05 0.389 4.550 1.061 Bottom View Dimensions are in mm 0.750 ± 0.05 0.025 ± 0.025 Side View Dimensions are in mm Doc.# DSFP-HV230_HV232 NR032505 11 8 NR011705