TMT T221160A

tm
TE
CH
T221160A
64K x 16 DYNAMIC RAM
DRAM
FAST PAGE MODE
FEATURES
• High speed access time : 25/30/35/40 ns
• Industry-standard x 16 pinouts and timing
functions.
• Single 5V (±10%) power supply.
• All device pins are TTL- compatible.
• 256-cycle refresh in 4ms.
• Refresh modes: RAS only, CAS BEFORE
RAS (CBR) and HIDDEN.
• Conventional FAST PAGE MODE access cycle.
• BYTE WRITE and BYTE READ access cycles.
PIN ASSIGNMENT ( Top View )
PART NUMBER EXAMPLES
PART NUMBER
T221160A-30J
ACCESS TIME
30ns
PACKAGE
SOJ
T221160A-30S
30ns
TSOP-II
T221160A-35J
35ns
35ns
SOJ
TSOP-II
T221160A-35S
GENERAL DESCRIPTION
The T221160A is a randomly accessed solid state
memory containing 1,048,551 bits organized in a
x16 configuration. The T221160A has both BYTE
WRITE and WORD WRITE access cycles via two
V cc
1
40
V ss
I/01
2
39
I/016
I/02
3
38
I/015
I/03
4
37
I/014
I/04
5
36
I/013
V cc
6
35
V ss
I/05
7
34
I/012
I/06
8
33
I/011
I/07
9
32
I/010
I/08
10
31
I/09
NC
11
30
NC
NC
12
29
CASL
WE
13
28
CASH
R AS
14
27
OE
NC
15
26
NC
A0
16
25
A7
A1
17
24
A6
A2
18
23
A5
A3
19
22
A4
V cc
20
21
VSS
V cc
1
40
V ss
I/01
2
39
I/01 6
I/02
3
38
I/01 5
I/03
4
37
I/01 4
I/04
5
36
I/01 3
V cc
6
35
V ss
I/05
7
34
I/01 2
I/06
8
33
I/01 1
I/07
9
32
I/01 0
I/08
10
31
I/09
NC
11
30
NC
NC
12
29
CA SL
WE
13
28
CA SH
RAS
14
27
OE
NC
15
26
NC
A0
16
25
A7
A1
17
24
A6
A2
18
23
A5
A3
19
22
A4
V cc
20
21
V SS
SO J
CAS pins. It offers Fast Page mode operation
T S O P (II)
The T221160A CAS function and timing are
determined by the first CAS to transition low and
by the last to transition back high. Use only one of
the two CAS and leave the other staying high
during WRITE will result in a BYTE WRITE.
CASL transiting low in a WRITE cycle will write
data into the lower byte (IO1~IO8), and CASH
transiting low will write data into the upper byte
(IO9~16).
Taiwan Memory Technology, Inc. reserves the right P. 1
to change products or specifications without notice.
Publication Date: FEB. 2002
Revision:A
tm
TE
CH
T221160A
FUNCTIONAL BLOCK DIAGRAM
WE
CASL
CONTROL
LOGIC
CAS
CASH
DATA-IN BUFFER
DQ01
.
.
16
NO.2 CLOCK
GENERATOR
DQ16
DATAOUT
BUFFER
COLUM N.
ADDRESS
BUFFER
8
8
A0
COLUM N
DECODER
OE
16
256
A1
8
REFRESH
CONTROLLER
A2
8
SENSE AM PLIFIERS
VO GATING
A3
A4
REFRESH
COUNTER
A5
256 x 16
A6
A7
8
ROW .
ADDRESS
BUFFERS(8)
8
ROW
DECODER
8
256
256 x 256 x 16
M EM ORY
ARRA
Y
Vcc
NO.1 CLOCK
GENERATOR
RAS
Vss
PIN DESCRIPTIONS
PIN NO.
SYM.
TYPE
DESCRIPTION
16~19,22~25
A0-A7
Input
Address Input
14
RAS
Input
Row Address Strobe
28
CASH
Input
Column Address Strobe /Upper Byte Control
29
CASL
Input
Column Address Strobe /Lower Byte Control
13
WE
Input
Write Enable
27
OE
Input
Output Enable
2~5,6~10,31~34,36~39
I/O1 - I/O16
1,6,20
Vcc
Supply
Power, 5V
21,35,40
Vss
Ground
Ground
11,12,15,30
NC
-
Input/ Output Data Input/ Output
Taiwan Memory Technology, Inc. reserves the right P. 2
to change products or specifications without notice.
No Connect
Publication Date: FEB. 2002
Revision:A
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TE
CH
T221160A
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any pin Relative to VSS… … -1V to 7V
Operating Temperature, Ta (ambient)..0°C to +70°C
Storage Temperature (plastic)….... -55°C to +150°C
Power Dissipation ...............................…......... 1.0W
Short Circuit Output Current...................….... 50mA
*Stresses greater than those listed under "Absolute
Maximum Ratings" may cause permanent damage
to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
reliability.
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED
OPERATING CONDITIONS
(0°C ≤ Ta ≤ 70°C; VCC = 5V ± 10 % unless otherwise noted)
DESCRIPTION
CONDITIONS
Supply Voltage
Supply Voltage
Input High (Logic) voltage
Input Low (Logic) voltage
Input Leakage Current
0V ≤ VIN ≤ 7V
0V ≤ VOUT≤ 7V
Output Leakage Current
Output(s) disabled
Output High Voltage
IOH = -5 mA
Output Low Voltage
IOL = 4.2 mA
SYM.
Vcc
Vss
VIH
VIL
ILI
MIN
4.5
0
2.4
-1.0
-10
MAX
5.5
0
Vcc+1
0.8
10
UNITS
V
V
V
V
uA
ILO
-10
10
uA
VOH
VOL
2.4
-
0.4
V
V
NOTES
1
1
1
Note: 1.All Voltages referenced to Vss
Taiwan Memory Technology, Inc. reserves the right P. 3
to change products or specifications without notice.
Publication Date: FEB. 2002
Revision:A
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CH
T221160A
DC CHARACTERISTICS
(Ta = 0 to 70°C, Vcc = 5V ±10%, Vss = 0V)
Parameter
-25
Symbol
-30
-35
-40
Unit
Test Condition
120 mA
RAS , CAS cycling
tRC=min
Min Max Min Max Min Max Min Max
Operating Current
Icc1
-
170
-
150
-
130
-
Standby Current
TTL interface,
Icc2
Standby Current
-
4
-
4
-
4
-
Icc3
-
2
-
2
-
2
-
Icc4
-
170
-
150
-
130
-
RAS -only refresh
Current
Icc5
-
170
-
150
-
130
-
CAS Before RAS
Refresh Current
Icc6
-
170
-
150
-
130
-
Fast Page Mode Current
Note:
4
2
mA RAS , CAS =VIH,
mA
DOUT=High-Z
CMOS interface,
RAS , CAS > Vcc-0.2V
RAS =VIL, CAS
120 mA cycling, t = min
PC
CAS =VIH, RAS
120 mA cycling, t = min
RC
120 mA
RAS , CAS cycling,
tRC= min
Icc depends on output load condition when the device is selected.
Icc max is specified at the output open condition, Icc is specified as an average current.
CAPACITANCE
(Ta =25°C, Vcc =5V, f = 1M HZ)
Parameter
Input Capacitance
(address)
Input Capacitance
( RAS , CAS , WE , OE )
Output Capacitance
(data-in/out)
Symbol
Typ
Max
Unit
CI1
-
5
pF
CI2
-
7
pF
CI/O
-
10
pF
Taiwan Memory Technology, Inc. reserves the right P. 4
to change products or specifications without notice.
Publication Date: FEB. 2002
Revision:A
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CH
T221160A
AC CHARACTERISTICS (note 1,2,3) (Ta = 0 to 70°C)
AC TEST CONDITIONS:
Vcc=5V ±10%, input pulse level = 0 to 3V
Input rise and fall times: 2ns
Output Load: 2TTL gate + CL (50pF)
AC CHARACTERISTICS
PARAMETER
Read or Write Cycle Time
Read-Modify-Write Cycle Time
Fast-Page-Mode Read or Write Cycle Time
Fast-Page-Mode Read-Write Cycle Time
SYM
Access Time From RAS
tRC
tRWC
tPC
tPCM
tRAC
Access Time From CAS
Access Time From OE
Access Time From Column Address
-25
-30
-35
-40
UNIT Notes
MIN MAX MIN MAX MIN MAX MIN MAX
43
65
15
37
55
85
20
42
65
95
23
49
75
105
25
52
25
30
35
40
ns
ns
ns
ns
ns 4
tCAC
7
8
9
10
ns 5
7
12
14
8
16
18
9
18
20
10
20
22
ns 13
Access Time From CAS Precharge
tOAC
tAA
tACP
RAS Pulse Width
tRAS
ns 8
ns
RAS Hold Time
25 10K 30 10K 35 10K 40 10K ns
tRASC 25 100K 30 100K 35 100K 40 100K ns
ns
tRSH
7
8
9
10
RAS Precharge Time
tRP
15
CAS Pulse Width
tCAS
4
CAS Hold Time
tCSH
21
26
CAS Precharge Time
tCP
tRCD
3
3
10
tCRP
tASR
tRAH
tRAD
tASC
tCAH
3
0
5
8
0
4
tAR
22
26
30
34
Column Address to RAS Lead Time
Read Command Setup Time
tRAL
tRCS
Read Command Hold Time Reference to CAS tRCH
12
0
0
14
0
0
16
0
0
18
0
0
ns
Read Command Hold Time Reference to RAS tRRH
0
0
0
0
ns 9
CAS to Output in Low-Z
tCLZ
3
3
3
3
ns
Output Buffer Turn-off Delay From CAS or
RAS
tOFF1
3
RAS Pulse Width
RAS to CAS Delay Time
CAS to RAS Precharge Time
Row Address Setup Time
Row Address Hold Time
RAS to Column Address Delay Time
Column Address Setup Time
Column Address Hold Time
Column Address Hold Time (Reference to
RAS )
Taiwan Memory Technology, Inc. reserves the right P. 5
to change products or specifications without notice.
20
10K
17
13
15
6
10
3
0
5
8
0
4
3
23
10K
21
14
15
ns
25
10K 10 10K ns
ns
30
35
ns
4
5
8
10
3
0
5
8
0
4
3
25
16
15
10
5
0
5
8
0
5
3
29
ns 7
ns
18
ns
ns
ns 8
ns
ns
ns
ns 14
ns 9,14
15
ns 10,16
Publication Date: FEB. 2002
Revision:A
tm
TE
CH
T221160A
AC CHARACTERISTICS (continued)
AC CHARACTERISTICS
PARAMETER
-25
-30
-35
-40
SYM MIN MAX MIN MAX MIN MAX MIN MAX UNIT Notes
Output Buffer Turn-off OE to
Write Command Setup Time
tOFF2
-
6
tWCS
0
0
0
0
ns
Write Command Hold Time
tWCH
4
4
4
6
ns
Write Command Hold Time (Reference
to RAS )
Write Command Pulse Width
tWCR
22
26
30
34
ns
tWP
4
4
4
6
ns
Write Command to RAS Lead Time
tRWL
5
6
7
9
ns
Write Command to CAS Lead Time
tCWL
5
6
7
8
ns
Data-in Setup Time
tDS
0
0
0
0
ns
Data-in Hold Time
tDH
4
4
4
5
ns
Data-in Hold Time (Reference to RAS )
tDHR
22
26
30
34
ns
RAS to WE Delay Time
tRWD
34
46
51
56
ns
Column Address to WE Delay Time
tAWD
21
29
31
35
ns
CAS to WE Delay Time
tCWD
17
24
25
27
ns
Transition Time (rise or fall)
tT
1.5
Refresh Period (256 cycles)
tREF
RAS to CAS Precharge Time
tRPC
10
10
10
10
ns
CAS Setup Time (CBR REFRESH)
tCSR
5
10
10
10
ns
CAS Hold Time (CBR REFRESH)
tCHR
7
10
10
10
ns
OE Hold Time From WE During ReadModify-Write Cycle
tOEH
4
4
4
5
ns
OE Setup Prior to RAS During Hidden
Refresh Cycle
tORD
0
0
0
0
ns
50
-
1.5
4
Taiwan Memory Technology, Inc. reserves the right P. 6
to change products or specifications without notice.
8
50
-
2.5
4
8
50
-
2.5
4
8
ns
50
ns
4
ms
16
11,14
14
14
14
14
12
12
11
11
11
2,3
6
6
15
Publication Date: FEB. 2002
Revision:A
tm
TE
CH
Notes:
1. An initial pause of 200us is required after
power-up followed by eight RAS refresh
cycles ( RAS only or CBR) before proper
device operation is assured. The eight RAS
cycle wake-ups should be repeated any time
the tREF refresh requirement is exceeded.
T221160A
11. tWCS, tRWD, tAWD and tCWD are
restrictive operating parameters in LATE
WRITE and READ-MODIFY-WRITE cycles
only. If tWCS ≥ tWCS(min), the cycle is an
EARLY WRITE cycle and the data output will
remain an open circuit throughout the entire
cycle. If tRWD ≥ tRWD(min), tAWD ≥
tAWD(min) and tCWD ≥ tCWD(min), the
2. VIH(2.4V) and VIL(0.8V) are reference levels
for measuring timing of input signals.
Transition times are measured between
VIH(2.4V) and VIL(0.8V).
cycle is READ-WRITE and the data output
will contain data read from the selected cell. If
neither of the above conditions is met, the state
of I/O (at access time and until CAS and
RAS or OE go back to VIH) is indeterminate.
OE held high and WE taken low after CAS
goes low result in a LATE WRITE ( OE controlled) cycle.
3. In addition to meet the transition rate
specification, all input signals must transit
between VIH and VIL in a monotonic manner.
4. Assume that tRCD < tRCD(max). If tRCD is
greater than the maximum recommended value
shown in this table, tRAC will increase by the
amount that tRCD exceeds the value shown.
6. Enables on-chip refresh and address counters.
12. These parameters are referenced to CAS
leading edge in EARLY WRITE cycles and
WE leading edge in LATE WRITE or READMODIFY-WRITE cycles.
7. Operation within the tRCD(max) limit ensures
that tRAC(max) can be met. tRCD(max) is
specified as a reference point only; if tRCD is
greater than the specified tRCD(max) limit,
access time is controlled by tCAC.
13. During a READ cycle, if OE is low then
taken HIGH before CAS goes high, I/O goes
open, if OE is tied permanently low, a LATE
WRITE
or
READ-MODIFY-WRITE
operation is not possible.
8. Operation within the tRAD limit ensures that
tRAC(max) can be met. tRAD(max) is
specified as a reference point only; if tRAD is
greater than the specified tRAD(max) limit,
access time is controlled by tAA.
14. WRITE command is defined as WE going
low.
5. Assume that tRCD ≥ tRCD(max) .
9. Either tRCH or tRRH must be satisfied for a
READ cycle.
10. tOFF1(max) defines the time at which the
output achieves the open circuit condition; it is
not a reference to VOH or VOL.
15. LATE WRITE and READ-MODIFY-WRITE
cycles must have both tOFF2 and tOEH met
( OE high during WRITE cycle) in order to
ensure that the output buffers will be open
during the WRITE cycles.
16. The I/Os open during READ cycles once
tOFF1 or tOFF2 occur.
Taiwan Memory Technology, Inc. reserves the right P. 7
to change products or specifications without notice.
Publication Date: FEB. 2002
Revision:A
tm
TE
CH
T221160A
READ CYCLE
t
RC
t
t
RAS
VIH
RAS VIL
t
CRP
t
t
CSH
t
RSH
t
CRP
t
RRH
t
RCD
VIH
CAS VIL
CAS
t
AR
t
t
RAD
t
t
ASR
VIH
ADDR VIL
t
RAH
ROW
RAL
t
ASC
CAH
COLUMN
ROW
t
RCS
WE
RP
t
RCH
VIH
VIL
t
AA
NOTE1
t
t
RAC
OFF1
t
CAC
t
CLZ
VIOH
I/O
VIOL
OPEN
VAILD DATA
t
OAC
OPEN
t
OFF2
VIH
OE
VIL
EARLY WRITE CYCLE
tRC
tRAS
tRP
VIH
RAS VIL
tCSH
tRSH
tCRP
RAS
tRCD
VIH
VIL
tCAS
tAR
t
t
ASR
VIH
ADDR VIL
tCRP
RAD
t
RAH
t
RAL
t
t
ASC
ROW
CSH
COLUMN
ROW
tCWL
tRWL
t
WCR
tWCS
VIH
WE VIL
tWP
tDHR
tDS
VIOH
VIOL
VIH
OE
VIL
I/O
tWCH
tDH
VAILD DATA
DON'T CARE
UNDEFINED
Note: tOFF1 is referenced from the rising edge of RAS or CAS , whichever occurs last.
Taiwan Memory Technology, Inc. reserves the right P. 8
to change products or specifications without notice.
Publication Date: FEB. 2002
Revision:A
tm
TE
CH
T221160A
READ WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE CYCLES)
t
RWC
t
t
RP
RAS
VIH
RAS VIL
t
CSH
tRSH
t
t
CRP
RCD
VIH
VIL
CAS
t
t
CAS
CRP
t
AR
t
t
RAD
tASR
VIH
ADDR VIL
RAL
tRAH
tASC
ROW
tCAH
COLUMN
ROW
t
t
t
t
RWD
t
RCS
CWL
CWD
RWL
tAWD
VIH
WE VIL
tWP
t
AA
t
RAC
t
t
CAC
t
DS
DH
tCLZ
VIOH
I/O VIOL
VAILD D
VAILD DOUT
t
t
t
OFF2
OAC
IN
OEH
VIH
OE VIL
FAST-PAGE-MODE READ CYCLE
t
RA S
V
V
IL
t
t
CR P
IL
t
t
V
V
t
CSH
t
RC D
t
CA S
t
PC
t
CP
t
CA S
t
CP
t
CR P
RSH
t
CA S
CPN
IH
t
A D D R
RP
IH
t
V
CA S
V
t
RA SC
A SR
t
A R
t
RA D
t
RA H
A SC
t
t
CA H
t
A SC
t
CA H
t
A SC
RA L
CA H
IH
IL
R O W
C O L U M N
C O L U M N
C O L U M N
R O W
t
t
W E
V
V
t
RC S
IH
t
t
IL
t
A A
t
t
V
I/O
V
O E
t
RA C
t
CA C
CLZ
t
V
V
t
t
O FF1
t
O A C
t
O FF2
CA C
t
O FF1
CLZ
CLZ
V A IL D
D AT A
O PE N
A A
A C P
A C P
CA C
t
IO H
IO L
t
O FF1
RC H
A A
t
t
RR H
V A IL D
D AT A
t
O A C
t
O FF2
V A IL D
D AT A
t
O A C
t
O PE N
O FF2
IH
IL
D O N 'T C A R E
U N D E F IN E D
Note: 1. tOFF1 is referenced from the rising edge of RAS or CAS , whichever occurs last.
2. tPC can be measured from falling edge of CAS to falling edge of CAS , or from rising edge of
CAS to rising edge of CAS . Both measurements must meet the tPC specification.
Taiwan Memory Technology, Inc. reserves the right P. 9
to change products or specifications without notice.
Publication Date: FEB. 2002
Revision:A
tm
TE
CH
T221160A
FAST-PAGE-MODE EARLY-WRITE CYCLE
t
VIH
RAS VIL
t
t
CSH
t
t
CRP
VIH
CAS VIL
t
RCD
t
t
CAS, CLCH
t
RASC
RP
t
PC
CP
t
t
CAS, CLCH
t
t
t
CAH
t
t
CP
CRP
RSH
t
t
CAS, CLCH
t
CPN
t
AR
tRAD
t
VIH
ADDR VIL
tRAL
t
ASR
t
RAH
t
ASC
ROW
CAH
ASC
COLUMN
t
tWCS
VIH
WE VIL
t
t
tWCH
tWCS
ROW
CWL
tWCH
t
WP
t
WP
WP
t
RWL
DHR
t
DS
tWCS
CAH
COLUMN
CWL
WCR
t
VIOH
I/O VIOL
t
tWCH
t
t
COLUMN
CWL
t
ASC
t
DH
VALID DATA
t
DS
t
DH
VALID DATA
t
DS
DH
VALID DATA
VIH
OE VIL
FAST-PAGE-MODE READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE CYCLES)
tRASC
RAS VIH
VIL
tCSH
tCRP
CAS
tRP
tRCD
VIH
VIL
tPCM
tCAS,tCLCH
tCP
tCP
tCAS,tCLCH
tCPN
tAR
tRAD
tASR
VIH
ADDR VIL
tCRP
tRSH
tCAS,tCLCH
tRAL
tRAH
tASC
ROW
tCAH
tASC
COLUMN
tCAH
tASC
COLUMN
tCAH
COLUMN
ROW
tRWD
tRCS
tRWL
tCWL
tAWD
tCWL
tWP
tAWD
tCWD
tCWL
tWP
tWP
tCWD
tCWD
VIH
WE VIL
tAA
tAA
tDS
VIOH
VIOL
tDH
tACP
tCAC
tCLZ
I/O
VAILD
D IN
tACP
tOAC
tDS
tCAC
tCLZ
VAILD
D OUT
tOFF2
tDH
tDS
tCAC
tCLZ
VAILD
D OUT
tOAC
OE
tAA
tDH
tRAC
VAILD
D IN
VAILD
D OUT
tOFF2
tOAC
VAILD
D IN
tOFF2
tOEH
VIH
VIL
DON'T CARE
UNDEFINED
Note: tPC can be measured from falling edge to falling edge of CAS , or from rising edge to rising edge of
CAS . Both measurements must meet the tPC specification.
Taiwan Memory Technology, Inc. reserves the right P. 10
to change products or specifications without notice.
Publication Date:FEB. 2002
Revision:A
tm
TE
CH
T221160A
FAST-PAGE-MODE READ-EARLY-WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
t
RAS
V IH
V IL
t
t
CSH
t
t
CAS
t
CRP
V IH
V IL
t
t
t
ADDR
V IH
V IL
A SR
t
t
RASC
t
RCD
PC
CAS
t
t
t
CP
RAH
t
A SC
ROW
t
CAH
COLUM N
t
A SC
t
CAH
COLUM N
CRP
t
CP
t
t
t
t
CAC
OPE
N
t
WCS
WCH
AA
O FF1
t
CAC
CLZ
V A IL D
D A T A (A )
t
ROW
ACP
RAC
t
RAL
CAH
RCH
t
AA
A SC
t
COLUM N
RCS
t
t
OE
CP
t
t
V IH
V IL
V IO H
V IO L
CAS
t
RSH
t
CAS
AR
t
I /O
t
RAD
t
WE
PC
RP
t
t
DS
t
DH
O FF1
V A IL D
D A T A (B )
V A IL D
D A T A IN
OAC
V IH
V IL
RAS ONLY REFRESH CYCLE
(ADDR=A0-A7 ; OE , WE =DON‘T CARE)
t
RC
tRAS
tRP
VIH
RAS VIL
tCRP
CAS
tRPC
VIH
VIL
tASR
VIH
ADDR VIL
tRAH
ROW
ROW
tOFF
I/O
VOH
VOL
OPEN
DON'T CARE
UNDEFINED
Note1:Do not drive data prior to tristate.
Taiwan Memory Technology, Inc. reserves the right P. 11
to change products or specifications without notice.
Publication Date:FEB. 2002
Revision:A
tm
TE
CH
T221160A
CBR REFRESH CYCLE
(A0-A7 ; OE =DON‘T CARE)
t
RC
t
RAS
VIH
VIL
t
RP
t
RAS
tRPC
tCPN
CAS
t
RAS
RP
tCSR
tCHR
tRPC
tCSR
tCHR
VIH
VIL
tOFF
I/O
WE
OPEN
VIH
VIL
HIDDEN REFRESH CYCLE
( WE =HIGH ; OE =LOW)
(R E A D )
t
t
R A S
V
V
C A S
t
C R P
t
R C D
t
IL
IH
A S R
t
R A H
t
R S H
t
t
A S C
R O W
t
R P
C H R
R A L
C O L U M N
IL
N O T E 1
t
t
IO H
A A
R A C
t
C A C
O F F 1
C L Z
V A IL D
O P E N
D A T A
O P E N
IO L
t
V
V
t
C A H
t
O E
R C
R A S
A R
R A D
t
V
I/O
V
R P
IH
t
V
V
R A S
t
IL
t
A D D R
t
t
IH
t
V
V
(R E F R E S H )
R C
t
IH
O A C
t
O F F 2
O R D
IL
D O N 'T C A R E
U N D E F IN E D
Note: 1. tOFF1 is referenced from the rising edge of RAS or CAS , whichever occurs last.
Taiwan Memory Technology, Inc. reserves the right P. 12
to change products or specifications without notice.
Publication Date: FEB. 2002
Revision:A
tm
TE
CH
T221160A
PACKAGE DIMENSIONS
40-LEAD SOJ DRAM (400 mil)
A
40
21
B
1
20
G
K
H
L
I
D
C
F
Seating
Plane
y
10¢X(MAX
)
J
E
SYMBOL
A
DIMENSIONS IN INCHES
1.025±0.010
DIMENSIONS IN MM
26.035±0.254
B
0.400±0.005
10.160±0.127
C
0.045(MAX)
1.143(MAX)
D
0.050±0.006
1.27±0.152
E
0.019±0.003
0.483±0.08
F
0.026±0.003
0.661±0.080
G
0.440±0.010
11.176±0.254
H
0.011±0.003
0.280±0.080
I
0.025(MIN)
0.635(MIN)
J
0.364±0.020
9.246±0.508
K
0.047±0.006
1.194±0.152
L
0.150(MAX)
3.810(MAX)
y
0.004(MAX)
0.102(MAX)
Taiwan Memory Technology, Inc. reserves the right P. 13
to change products or specifications without notice.
Publication Date: FEB. 2002
Revision:A
tm
TE
CH
T221160A
PACKAGE DIMENSIONS
40-LEAD TSOP II DRAM (400 mil)
D
40
21
E E1
1
20
e
b
A
θ
A2
A1
y
L
L1
S E A T IN G P L A N E
SYMBOL
A
DIMENSIONS IN INCHES
0.047(max)
DIMENSIONS IN MM
1.20(max)
A1
0.004±0.002
0.10±0.05
A2
0.039±0.002
1.00±0.05
b
0.014(typ.)
0.35(typ.)
e
0.0315(typ.)
0.80typ.)
D
0.725±0.004
18.41±0.10
E
0.463±0.008
11.76±0.20
E1
0.400±0.004
10.16±0.10
L1
0.031
0.80
L
0.020±0.004
0.500±0.10
y
0.004(max)
0.10(max)
θ
0°~5°
0°~5°
Taiwan Memory Technology, Inc. reserves the right P. 14
to change products or specifications without notice.
Publication Date: FEB. 2002
Revision:A