HITACHI HM514400B

ADE-203-269A (Z)
HM514400B/BL Series
HM514400C/CL Series
1,048,576-word × 4-bit Dynamic Random Access Memory
Rev. 1.0
Nov. 29, 1994
The Hitachi HM514400B/BL, HM514400C/CL
are CMOS dynamic RAM organized 1,048,576word × 4-bit. HM514400B/BL, HM514400C/CL
have realized higher density, higher performance
and various functions by employing 0.8 µm CMOS
process technology and some new CMOS circuit
design technologies. The HM514400B/BL,
HM514400C/CL offer Fast Page Mode as a high
speed access mode. Multiplexed address input
permits the HM514400B/BL, HM514400C/CL to
be packaged in standard 300-mil 26-pin plastic
SOJ, standard 400-mil 20-pin plastic ZIP and 26pin plastic TSOP II.
Features
• Single 5 V (±10%)
• High speed
— Access time
60 ns/70 ns/80 ns (max)
• Low power dissipation
— Active mode
605 mW/550 mW/495 mW (max)
— Standby mode 11 mW (max)
0.55 mW (max) (L-version)
• Fast page mode capability
• 1024 refresh cycles : 16 ms
1024 refresh cycles : 128 ms (L-version)
• 3 variations of refresh
— RAS-only refresh
— CAS-before-RAS refresh
— Hidden refresh
• Test function
• Battery back up operation
— HM514400BL Series (L-version)
— HM514400CL Series (L-version)
HM514400B/BL, HM514400C/CL Series
Ordering Information
Type No.
Access
time
Package
Type No.
Access
time
Package
HM514400BS-6
HM514400BS-7
HM514400BS-8
60 ns
70 ns
80 ns
300-mil 26-pin
plastic SOJ
(CP-26/20D)
HM514400CZ-6
HM514400CZ-7
HM514400CZ-8
60 ns
70 ns
80 ns
400-mil 20-pin
plastic ZIP
(ZP-20)
HM514400BLS-6
HM514400BLS-7
HM514400BLS-8
60 ns
70 ns
80 ns
HM514400CLZ-6
HM514400CLZ-7
HM514400CLZ-8
60 ns
70 ns
80 ns
HM514400CS-6
HM514400CS-7
HM514400CS-8
60 ns
70 ns
80 ns
HM514400BTT-6
HM514400BTT-7
HM514400BTT-8
60 ns
70 ns
80 ns
HM514400CLS-6
HM514400CLS-7
HM514400CLS-8
60 ns
70 ns
80 ns
HM514400BLTT-6
HM514400BLTT-7
HM514400BLTT-8
60 ns
70 ns
80 ns
HM514400BZ-6
HM514400BZ-7
HM514400BZ-8
60 ns
70 ns
80 ns
HM514400CTT-6
HM514400CTT-7
HM514400CTT-8
60 ns
70 ns
80 ns
HM514400BLZ-6
HM514400BLZ-7
HM514400BLZ-8
60 ns
70 ns
80 ns
HM514400CLTT-6
HM514400CLTT-7
HM514400CLTT-8
60 ns
70 ns
80 ns
2
400-mil 20-pin
plastic ZIP
(ZP-20)
26-pin
plastic TSOPII
(TTP-26/20D)
HM514400B/BL, HM514400C/CL Series
Pin Arrangement
HM514400BS/BLS Series
HM514400CS/CLS Series
HM514400BZ/BLZ Series
HM514400CZ/CLZ Series
1 OE
I/O1 1
26 VSS
CAS 2
I/O2 2
25 I/O4
I/O4 4
WE 3
24 I/O3
RAS 4
23 CAS
3 I/O3
5 VSS
I/O1 6
7 I/O2
WE 8
A9 5
22 OE
9 RAS
A9 10
11 A0
A0 9
18 A8
A1 12
13 A2
A1 10
17 A7
A3 14
A2 11
16 A6
A4 16
A3 12
15 A5
A6 18
VCC 13
14 A4
A8 20
15 VCC
17 A5
(Top view)
19 A7
(Bottom view)
HM514400BTT/BLTT Series
HM514400CTT/CLTT Series
I/O1 1
26 VSS
I/O2 2
25 I/O4
WE 3
24 I/O3
RAS 4
23 CAS
A9
5
22 OE
A0
9
18 A8
A1 10
17 A7
A2 11
16 A6
A3 12
15 A5
VCC 13
14 A4
(Top view)
3
HM514400B/BL, HM514400C/CL Series
Pin Description
Pin name
Function
A0 to A9
Address input
A0 to A9
Refresh address input
I/O1 to I/O4
Data-in/Data-out
RAS
Row address strobe
CAS
Column address strobe
WE
Read/Write enable
OE
Output enable
VCC
Power (+5 V)
VSS
Ground
4
Row
Driver
Row
Driver
256 k Memory Array Mat
Row
Driver
Row
Driver
Row Address Buffer
CAS Control
Circuit
WE Control
Circuit
OE Control
Circuit
Row
Driver
Row
Driver
Row
Driver
Row
Driver
256 k Memory Array Mat
OE
256 k Memory Array Mat
WE
I/O Bus & Column Decoder
256 k Memory Array Mat
Row
Driver
256 k Memory Array Mat
CAS
I/O Bus & Column Decoder
256 k Memory Array Mat
Row Decoder & Peripheral Circuit
Row
Driver
256 k Memory Array Mat
I/O Bus & Column Decoder
256 k Memory Array Mat
Row
Driver
I/O Bus & Column Decoder
Row
Driver
256 k Memory Array Mat
Row
Driver
256 k Memory Array Mat
Row
Driver
I/O Bus & Column Decoder
256 k Memory Array Mat
RAS
I/O Bus & Column Decoder
Row
Driver
256 k Memory Array Mat
Row
Driver
256 k Memory Array Mat
I/O Bus & Column Decoder
256 k Memory Array Mat
RAS Control
Circuit
256 k Memory Array Mat
I/O Bus & Column Decoder
256 k Memory Array Mat
HM514400B/BL, HM514400C/CL Series
Block Diagram
I/O1
I/O2
I/O3
I/O4
I/O1 Buffer
I/O2 Buffer
I/O3 Buffer
I/O4 Buffer
Column Address Buffer
Address A0–A9
5
HM514400B/BL, HM514400C/CL Series
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Voltage on any pin relative to VSS
VT
–1.0 to +7.0
V
Supply voltage relative to VSS
VCC
–1.0 to +7.0
V
Short circuit output current
Iout
50
mA
Power dissipation
PT
1.0
W
Operating temperature
Topr
0 to +70
°C
Storage temperature
Tstg
–55 to +125
°C
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
VSS
0
0
0
V
VCC
4.5
5.0
5.5
V
1
Input high voltage
VIH
2.4
—
6.5
V
1
Input low voltage
VIL
–1.0
—
0.8
V
1
Note:
6
1. All voltage referred to VSS.
Note
HM514400B/BL, HM514400C/CL Series
DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V)
HM514400B/BL, HM514400C/CL
-6
-7
-8
Parameter
Symbol
Min Max Min Max Min Max Unit Test conditions
Operating current
ICC1
—
110 —
100 —
90
mA
RAS, CAS cycling
tRC = min
Standby current
ICC2
—
2
—
2
—
2
mA
TTL interface
RAS, CAS = VIH
Dout = High-Z
—
1
—
1
—
1
mA
CMOS interface
RAS, CAS
≥ VCC – 0.2 V
Dout = High-Z
Notes
1, 2
Standby current
(L-version)
ICC2
—
100 —
100 —
100 µA
CMOS interface
4
RAS, CAS =VIH
WE, OE, Address and
Din = VIH or VIL
Dout = High-Z
RAS-only
refresh current
ICC3
—
110 —
100 —
90
mA
tRC = min
Standby current
ICC5
—
5
5
5
mA
RAS = VIH, CAS = VIL 1
Dout = enable
CAS-before-RAS
refresh current
ICC6
—
110 —
100 —
90
mA
tRC = min
Fast page mode
current
ICC7
—
110 —
100 —
90
mA
tPC = min
1, 3
Battery back up
current
(Standby with
CBR refresh)
(L-version)
ICC10
—
200 —
200 —
200 µA
tRC = 125 µs
tRAS ≤ 1 µs
WE = VIH, CAS = VIL
OE, Address and
Din = VIH or VIL
Dout = High-Z
4
Input leakage current
ILI
–10 10
–10 10
–10 10
µA
0 V ≤ Vin ≤ 7 V
Output leakage
current
ILO
–10 10
–10 10
–10 10
µA
0 V ≤ Vout ≤ 7 V
Dout = disable
Output high voltage
VOH
2.4
VCC 2.4
VCC 2.4
VCC V
High Iout = –5 mA
Output low voltage
VOL
0
0.4
0.4
0.4
Low Iout = 4.2 mA
—
0
—
0
V
2
Notes: 1. ICC depends on output load condition when the device is selected. ICC max is specified at the
output open condition.
2. Address can be changed twice or less while RAS = VIL.
3. Address can be changed once or less while CAS = VIH.
4. VCC – 0.2 V ≤ VIH ≤ 6.5 V and 0 V ≤ VIL ≤ 0.2 V.
7
HM514400B/BL, HM514400C/CL Series
Capacitance (Ta = 25°C, VCC = 5 V ± 10%)
Parameter
Symbol
Typ
Max
Unit
Notes
Input capacitance (Address)
CI1
—
5
pF
1
Input capacitance (Clocks)
CI2
—
7
pF
1
Output capacitance
(Data-in, Data-out)
CI/O
—
7
pF
1, 2
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. CAS = VIH to disable Dout.
AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V) *1, *14, *15, *16
Test Conditions
• Input rise and fall times : 5 ns
• Input timing reference levels : 0.8 V, 2.4 V
• Output load : 2 TTL gate + CL (100 pF) (Including scope and jig)
8
HM514400B/BL, HM514400C/CL Series
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
HM514400B/BL, HM514400C/CL
-6
-7
-8
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Random read or write cycle time
tRC
110
—
130
—
150
—
ns
RAS precharge time
tRP
40
—
50
—
60
—
ns
RAS pulse width
tRAS
60
10000 70
10000 80
10000 ns
19
CAS pulse width
tCAS
15
10000 20
10000 20
10000 ns
20
Row address setup time
tASR
0
—
0
—
0
—
ns
Row address hold time
tRAH
10
—
10
—
10
—
ns
Column address setup time
tASC
0
—
0
—
0
—
ns
Column address hold time
tCAH
15
—
15
—
15
—
ns
RAS to CAS delay time
tRCD
20
45
20
50
20
60
ns
8
RAS to column address delay time
tRAD
15
30
15
35
15
40
ns
9
RAS hold time
tRSH
15
—
20
—
20
—
ns
CAS hold time
tCSH
60
—
70
—
80
—
ns
CAS to RAS precharge time
tCRP
10
—
10
—
10
—
ns
OE to Din delay time
tODD
15
—
20
—
20
—
ns
OE delay time from Din
tDZO
0
—
0
—
0
—
ns
CAS setup time from Din
tDZC
0
—
0
—
0
—
ns
Transition time (rise and fall)
tT
3
50
3
50
3
50
ns
Refresh period
tREF
—
16
—
16
—
16
ms
Refresh period (L-version)
tREF
—
128
—
128
—
128
ms
7
9
HM514400B/BL, HM514400C/CL Series
Read Cycle
HM514400B/BL, HM514400C/CL
-6
-7
-8
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Access time from RAS
tRAC
—
60
—
70
—
80
ns
2, 3, 17
Access time from CAS
tCAC
—
15
—
20
—
20
ns
3, 4, 13,
17
Access time from address
tAA
—
30
—
35
—
40
ns
3, 5, 13,
17
Access time from OE
tOAC
—
15
—
20
—
20
ns
3, 17
Read command setup time
tRCS
0
—
0
—
0
—
ns
Read command hold time to CAS
tRCH
0
—
0
—
0
—
ns
18
Read command hold time to RAS
tRRH
0
—
0
—
0
—
ns
18
Column address to RAS lead time
tRAL
30
—
35
—
40
—
ns
Output buffer turn-off time
tOFF1
0
15
0
20
0
20
ns
6
Output buffer turn-off time to OE
tOFF2
0
15
0
20
0
20
ns
6
CAS to Din delay time
tCDD
15
—
20
—
20
—
ns
OE pulse width
tOEP
15
—
20
—
20
—
ns
Write Cycle
HM514400B/BL, HM514400C/CL
-6
-7
-8
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Write command setup time
tWCS
0
—
0
—
0
—
ns
10
Write command hold time
tWCH
15
—
15
—
15
—
ns
Write command pulse width
tWP
10
—
10
—
10
—
ns
Write command to RAS lead time
tRWL
15
—
20
—
20
—
ns
Write command to CAS lead time
tCWL
15
—
20
—
20
—
ns
Data-in setup time
tDS
0
—
0
—
0
—
ns
11
Data-in hold time
tDH
15
—
15
—
15
—
ns
11
10
HM514400B/BL, HM514400C/CL Series
Read-Modify-Write Cycle
HM514400B/BL, HM514400C/CL
-6
-7
-8
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Read-modify-write cycle time
tRWC
150
—
180
—
200
—
ns
RAS to WE delay time
tRWD
80
—
95
—
105
—
ns
10
CAS to WE delay time
tCWD
35
—
45
—
45
—
ns
10
Column address to WE delay time
tAWD
50
—
60
—
65
—
ns
10
OE hold time from WE
tOEH
15
—
20
—
20
—
ns
Refresh Cycle
HM514400B/BL, HM514400C/CL
-6
-7
-8
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
CAS setup time (CBR refresh cycle)
tCSR
10
—
10
—
10
—
ns
CAS hold time (CBR refresh cycle)
tCHR
10
—
10
—
10
—
ns
RAS precharge to CAS hold time
tRPC
10
—
10
—
10
—
ns
CAS precharge time in normal mode
tCPN
10
—
10
—
10
—
ns
Notes
Fast Page Mode Cycle
HM514400B/BL, HM514400C/CL
-6
-7
-8
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Fast page mode cycle time
tPC
40
—
45
—
50
—
ns
Fast page mode CAS precharge time tCP
10
—
10
—
10
—
ns
Fast page mode RAS pulse width
tRASC
—
100000 —
100000 —
100000 ns
12
Access time from CAS precharge
tACP
—
35
—
40
—
45
ns
3, 13,
17
RAS hold time from CAS precharge
tRHCP
35
—
40
—
45
—
ns
11
HM514400B/BL, HM514400C/CL Series
Fast Page Mode Read-Modify-Write Cycle
HM514400B/BL, HM514400C/CL
-6
-7
-8
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Fast page mode read-modify-write
cycle time
tPCM
80
—
95
—
100
—
ns
Fast page mode read-modify-write
cycle CAS precharge to WE delay
time
tCPW
55
—
65
—
70
—
ns
10
Notes
Test Mode Cycle
HM514400B/BL, HM514400C/CL
-6
-7
-8
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Test mode WE setup time
tWS
0
—
0
—
0
—
ns
Test mode WE hold time
tWH
10
—
10
—
10
—
ns
Counter Test Cycle
HM514400B/BL, HM514400C/CL
-6
-7
-8
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
CAS precharge time in counter test
cycle
tCPT
40
—
40
—
40
—
ns
12
Notes
HM514400B/BL, HM514400C/CL Series
Notes: 1. AC measurements assume tT = 5 ns.
2. Assumes that tRCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the
maximum recommended value shown in this table, tRAC exceeds the value shown.
3. Measured with a load circuit equivalent to 2 TTL loads and 100 pF.
4. Assumes that tRCD ≥ tRCD (max) and tRAD ≤ tRAD (max).
5. Assumes that tRCD ≤ tRCD (max) and tRAD ≥ tRAD (max).
6. tOFF (max) defines the time at which the output achieves the open circuit condition and is not
referred to output voltage levels.
7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also,
transition times are measured between VIH and VIL.
8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified
as a reference point only, if tRCD is greater than the specified tRCD (max) limit, then access time
is controlled exclusively by tCAC.
9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified
as a reference point only, if tRAD is greater than the specified tRAD (max) limit, then access time
is controlled exclusively by tAA.
10. tWCS, tRWD, tCWD, tCPW and tAWD are not restrictive operating parameters. They are included in
the data sheet as electrical characteristics only; if tWCS ≥ tWCS (min), the cycle is an early write
cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle;
if tRWD ≥ tRWD (min), tCWD ≥ tCWD (min), tCPW ≥ tCPW (min) and tAWD ≥ tAWD (min), the cycle is a
read-modify-write and the data output will contain data read from the selected cell; if neither of
the above sets of conditions is satisfied, the condition of the data out (at access time) is
indeterminate.
11. These parameters are referred to CAS leading edge in an early write cycle and to WE leading
edge in a delayed write or read-modify-write cycle.
12. tRASC defines RAS pulse width in fast page mode cycles.
13. Access time is determined by the longest among tAA, tCAC and tACP.
14. An initial pause of 100 µs is required after power up followed by a minimum of eight initialization
cycles (RAS-only refresh cycle or CAS-before-RAS refresh cycle). If the internal refresh counter
is used, a minimum of eight CAS-before-RAS refresh cycles is required.
15. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data
to the device.
16. Test mode operation specified in this data sheet is 2-bit test function controlled by control
address bits - - - CA0. This test mode operation can be performed by WE-and-CAS-before-RAS
(WCBR) refresh cycle. Refresh during test mode operation will be performed by normal read
cycles or by WCBR refresh cycles. When the state of two test bits accord each other, the
condition of the output data is high level. When the state of test bits do not accord, the condition
of the output data is low level. In order to end this test mode operation, perform a RAS-only
refresh cycle or a CAS-before-RAS refresh cycle.
17. In a test mode read cycle, the value of tRAC, tAA, tCAC, tOAC and tACP is delayed for 2 ns to 5 ns
for the specified value. These parameters should be specified in test mode cycles by adding the
above value to the specified value in this data sheet.
18. Either tRCH or tRRH must be satisfied
19. tRAS (min) = tRWD (min) + tRWL (min) + tT in read-modify-write cycle.
20. tCAS (min) = tCWD (min) + tCWL (min) + tT in read-modify-write cycle.
13
HM514400B/BL, HM514400C/CL Series
Timing Waveforms*21
Read Cycle
t RC
t RAS
RAS
tT
t RP
t CRP
t RSH
t CAS
t CSH
t RCD
CAS
t RAD
t ASR
Address
t RAH
t RAL
t CAH
t ASC
Row
Column
t RCS
t RCH
t RRH
WE
t CAC
t AA
t OFF1
Dout
Dout
t RAC
t OFF2
t DZC
t OAC
t CDD
High-Z
Din
t ODD
t DZO
t OEP
@
€
À
@
OE
Notes: 21.
H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max))
Invalid Dout
14
HM514400B/BL, HM514400C/CL Series
Early Write Cycle
t RC
t RAS
RAS
t RP
t RSH
t CAS
tT
t RCD
t CRP
t CSH
CAS
t ASR
Address
t RAH
t ASC
Row
t CAH
Column
t WCS
t WCH
WE
t DH
t DS
Din
Dout
Din
High-Z*
* t WCS
t WCS (min)
** OE : H or L
15
HM514400B/BL, HM514400C/CL Series
Delayed Write Cycle
t RC
t RAS
t RP
RAS
t CSH
t CRP
t RCD
t RSH
t CAS
tT
CAS
t ASR
Address
t ASC
t RAH
t CWL
t RWL
t CAH
Row
Column
t RCS
t WP
WE
t DS
t DH
High-Z
Din
Din
t DZC
t ODD
t OEH
t DZO
Dout
Invalid Dout*
t OFF2
OE
*
* Invalid Dout comes out, when OE is low level.
16
HM514400B/BL, HM514400C/CL Series
Read-Modify-Write Cycle
t RWC
t RAS
t RP
RAS
tT
t RCD
t CAS
t CRP
CAS
t RAD
t ASR
Address
t RAH
tCAH
t ASC
Column
Row
t CWL
t CWD
t RCS
t RWL
t AWD
t WP
WE
t RWD
t AA
t CAC
t DS
t RAC
t DH
t DZC
High-Z
Din
Dout
Din
Dout
t OAC
t OFF2
t DZO
OE
t OEH
t ODD
t OEP
17
HM514400B/BL, HM514400C/CL Series
Hidden Refresh Cycle
tRC
t RC
t RP
t RAS
(Read)
t RC
t RAS
t RP
(Refresh)
t RAS
tRP
(Refresh)
RAS
tT
t RSH
t CHR
t CRP
t CAS
t RCD
CAS
t ASC
t ASR
t RAD
t RAL
t CAH
t RAH
Address
Row
Column
t RCH
t RRH
t RCS
t CAC
WE
t AA
t OFF1
t RAC
Dout
Dout
t DZC
t OFF2
High-Z
Din
tDZO
OE
18
t CDD
t OAC
t ODD
HM514400B/BL, HM514400C/CL Series
Fast Page Mode Read Cycle
t RASC
t RHCP
t RP
RAS
tT
t CSH
t RCD
t PC
t CAS
t CP
t RSH
t CAS
t CP
t CRP
t CAS
CAS
t RAL
t ASR
t RAD
t RAH
Address
tASC
Row
t ASC t CAH
t CAH
Column
Column
Column
t RCS
t RCS
t CAH
t ASC
t RCS
t RRH
t RCH
t RCH
t RCH
WE
t DZC
Din
t RAC
t DZC
t DZC
t CDD
High-Z
High-Z
t ODD
t CAC
tCAC
t CAC
t AA
t ACP
t AA
t AA
Dout
Dout
t OAC
OE
t OFF2
t OEP
High-Z
t OFF1
t OFF1
t DZO
Dout
t DZO
t ODD
t ACP
t OFF1
t DZO
t CDD
t CDD
Dout
t ODD
t OAC
t OFF2
t OFF2
t OEP
t OEP
t OAC
19
HM514400B/BL, HM514400C/CL Series
Fast Page Mode Early Write Cycle
t RASC
t RP
RAS
tT
t CSH
t RCD
t RSH
t PC
t CAS
t CP
t CAS
t CAS
t CP
t CAH
t ASC
t CRP
CAS
t ASR
Address
t RAH
Row
t ASC
t CAH
Column
t WCS
t WCH
t ASC
Column
t WCS
t CAH
Column
t WCH
t WCH
t WCS
WE
t DS
Din
Dout
Din
t DH
t DS
Din
t DH
t DS
t DH
Din
High-Z
* OE : H or L
20
HM514400B/BL, HM514400C/CL Series
Fast Page Mode Delayed Write Cycle
t RASC
t RP
RAS
tT
t CSH
tRCD
t PC
t CAS
t CP
t CAS
t RSH
t CAS
t CP
t CRP
CAS
t ASR
t RAH
Address
t ASC
t CAH
t ASC
t CAH
Row
t CAH
t ASC
Column
Column
Column
t CWL
t CWL
t CWL
t WP
t RCS
t WP
t WP
t RWL
WE
t DH
t DS
Din
t RCS
t DH
t DS
t DH
t DS
Din
Din
t RCS
Din
t OEH
High-Z
Dout
t ODD
OE
21
HM514400B/BL, HM514400C/CL Series
Fast Page Mode Read-Modify-Write Cycle
t RP
t RASC
RAS
t RCD
t PCM
tT
t CAS
CAS
t CRP
t CP
t CP
t CAS
t CAS
t RAD
t RAH
t ASR
Address
t ACP
t CAH
t ASC
t ASC
Row
t ASC
Column
Column
t RCS
t CAH
t CAH
t AWD
t CWD
t CWL
t RWD
t WP
Column
t AWD
t CWL
t CWD
t RCS
t CPW
t WP
t RCS
t CPW
t CWL
t AWD
t RWL
t CWD
t WP
WE
t CAC
t DZC
t DZC t CAC
t DH
High-Z
Din
High-Z
Din
tAA
Din
t OEH
Dout
t OAC
t OEH
Dout
t OFF2
t DS
t DH
t DZC
High-Z
Din
t CAC
t DZO
tOAC
t DZO
t DH
t AA
t RAC
Dout
t ACP
t DS
t DS
t AA
t OAC
t OEH
Dout
t OFF2
t DZO
t OFF2
OE
t ODD
t ODD
t OEP
22
t OEP
t ODD
tOEP
HM514400B/BL, HM514400C/CL Series
Test Mode Cycle
Set Cycle**
*,**
Reset Cycle
Test Mode Cycle
Normal Mode
RAS
CAS
WE
* CBR or RAS-only refresh
** Address, Din, OE: H or L
Test Mode Set Cycle
WE-and-CAS-Before RAS-Refresh Cycle
t RC
t RP
t RAS
t RP
RAS
t RPC
t CSR
t CHR
t RPC
t CRP
CAS
t WS
t WH
t CPN
t CPN@
@@
tT
WE
Address
t OFF1
Dout
High-Z
23
HM514400B/BL, HM514400C/CL Series
CAS-Before-RAS Refresh Cycle
t RC
t RP
t RAS
t RP
RAS
tT
t CPN
CAS
t CSR
t RPC
t CHR
t CPN
t RPC
t WS
t WH
WE
Address
t OFF1
Dout
24
High-Z
t CRP
HM514400B/BL, HM514400C/CL Series
RAS-Only Refresh Cycle
t RC
t RAS
t RP
RAS
tT
t CRP
tRPC
tCRP
CAS
t RAH
t ASR
Address
Dout
Row
High-Z
* Refresh address : A0 – A9 (AX0 – AX9)
** WE : H or L
25
HM514400B/BL, HM514400C/CL Series
CAS-Before-RAS Refresh Counter Check Cycle (Read)
t RAS
t RP
RAS
tT
t CSR
t CHR
t CPT
t RSH
tCRP
t CAS
CAS
t ASC
t CAH
Column
Address
t RCH
t RRH
t WS
t WH
t RCS
WE
t CDD
t DZC
High-Z
Din
t CAC
t AA
t OFF1
Dout
Dout
t DZO
t OFF2
t OAC
t OEP
OE
26
t ODD
HM514400B/BL, HM514400C/CL Series
CAS-Before-RAS Refresh Counter Check Cycle (Write)
t RAS
t RP
RAS
tT
t CSR
t CHR
t CPT
t RSH
t CRP
t CAS
CAS
t ASC
t CAH
Address
Column
t WS
t WH
t WCS
t WCH
WE
t DS
Din
Dout
t DH
Din
High-Z
OE
27