HM514260C Series HM51S4260C Series 262,144-word × 16-bit Dynamic Random Access Memory ADE-203-260A (Z) Rev. 1.0 Jun. 12, 1995 Description The Hitachi HM51(S)4260C is CMOS dynamic RAM organized as 262,144-word × 16-bit. HM51(S)4260C has realized higher density, higher performance and various functions by employing 0.8 µm CMOS process technology and some new CMOS circuit design technologies. The HM51(S)4260C offers fast page mode as a high speed access mode. Multiplexed address input permits the HM51(S)4260C to be packaged in standard 400-mil 40-pin plastic SOJ and standard 400-mil 44-pin plastic TSOPII. Internal refresh timer enables HM51S4260C self refresh operation. Features • • • • • • • • • Single 5 V (±10%) (HM51(S)4260C-6/7/8) (±5%) (HM51(S)4260C-6R) High speed — Access time: 60 ns/70 ns/80 ns (max) Low power dissipation — Active mode: 825 mW/788 mW/770 mW/688 mW (max) — Standby mode: 11 mW (max) (HM51(S)4260C-6/7/8) 10.5 mW (max) (HM51(S)4260C-6R) 1.1 mW (max) (L-version) (HM51(S)4260C-6/7/8) 1.05 mW (max) (L-version) (HM51(S)4260C-6R) Fast page mode capability 512 refresh cycles: 8 ms 128 ms (L-version) 2 CAS-byte control 2 variations of refresh — RAS-only refresh — CAS-before-RAS refresh Battery backup operation (L-version) Self refresh operation (HM51S4260C) HM514260C, HM51S4260C Series Ordering Information Type No. Access Time Package HM514260CJ-6 HM514260CJ-6R HM514260CJ-7 HM514260CJ-8 60 ns 60 ns 70 ns 80 ns 400-mill 40-pin plastic SOJ (CP-40DA) HM514260CLJ-6 HM514260CLJ-6R HM514260CLJ-7 HM514260CLJ-8 60 ns 60 ns 70 ns 80 ns HM51S4260CJ-6 HM51S4260CJ-6R HM51S4260CJ-7 HM51S4260CJ-8 60 ns 60 ns 70 ns 80 ns HM51S4260CLJ-6 HM51S4260CLJ-6R HM51S4260CLJ-7 HM51S4260CLJ-8 60 ns 60 ns 70 ns 80 ns HM514260CTT-6 HM514260CTT-6R HM514260CTT-7 HM514260CTT-8 60 ns 60 ns 70 ns 80 ns HM514260CLTT-6 HM514260CLTT-6R HM514260CLTT-7 HM514260CLTT-8 60 ns 60 ns 70 ns 80 ns HM51S4260CTT-6 HM51S4260CTT-6R HM51S4260CTT-7 HM51S4260CTT-8 60 ns 60 ns 70 ns 80 ns HM51S4260CLTT-6 HM51S4260CLTT-6R HM51S4260CLTT-7 HM51S4260CLTT-8 60 ns 60 ns 70 ns 80 ns 400-mill 44-pin plastic TSOP II (TTP-44/40DB) 2 HM514260C, HM51S4260C Series Pin Arrangement HM514260CTT/CLTT Series HM51S4260CTT/CLTT Series HM514260CJ/CLJ Series HM51S4260CJ/CLJ Series VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC NC WE RAS NC A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE A8 A7 A6 A5 A4 VSS (Top view) VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 1 2 3 4 5 6 7 8 9 10 44 43 42 41 40 39 38 37 36 35 VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC NC WE RAS NC A0 A1 A2 A3 VCC 13 14 15 16 17 18 19 20 21 22 32 31 30 29 28 27 26 25 24 23 NC LCAS UCAS OE A8 A7 A6 A5 A4 VSS (Top view) Pin Description Pin Name Function A0 to A8 Address input –Row address –Column address –Refresh address A0 to A8 A0 to A8 A0 to A8 I/O0 to I/O15 Data-in/data-out RAS Row address strobe UCAS, LCAS Column address strobe WE Read/write enable OE Output enable VCC Power (+5 V) VSS Ground NC No connection 3 Selector Row Decoder 4 Row Row Decoder Decoder I/O4 I/O4 Buffer I/O5 I/O5 Buffer I/O6 I/O6 Buffer I/O9 Buffer I/O9 I/O7 I/O7 Buffer I/O8 Buffer I/O8 I/O3 I/O2 I/O1 I/O0 I/O15 I/O14 I/O13 I/O12 I/O3 Buffer I/O2 Buffer I/O1 Buffer I/O0 Buffer I/O15 Buffer I/O14 Buffer I/O13 Buffer I/O12 Buffer Address A4,A5 Selector Row Decoder Row Row Decoder Decoder 256 k Memory Array Mat Selector I/O Bus & Column Decoder A0,A1,A2,A3 256 k Memory Array Mat Row Row Decoder Decoder Row Decoder 256 k Memory Array Mat Selector I/O Bus & Column Decoder Selector Row Decoder 256 k Memory Array Mat Address Peripheral Circuit Row Row Decoder Decoder 256 k Memory Array Mat Selector I/O Bus & Column Decoder Row Decoder 256 k Memory Array Mat Row Decoder 256 k Memory Array Mat I/O Bus & Column Decoder 256 k Memory Array Mat 256 k Memory Array Mat I/O Bus & Column Decoder 256 k Memory Array Mat 256 k Memory Array Mat I/O Bus & Column Decoder 256 k Memory Array Mat Peripheral Circuit 256 k Memory Array Mat I/O Bus & Column Decoder 256 k Memory Array Mat 256 k Memory Array Mat I/O Bus & Column Decoder 256 k Memory Array Mat HM514260C, HM51S4260C Series Block Diagram Row Decoder Selector I/O11 Buffer Peripheral Circuit A6,A7,A8 Selector Row Decoder I/O11 I/O10 I/O10 Buffer LCAS WE UCAS RAS OE HM514260C, HM51S4260C Series Operation Mode The HM51(S)4260C series has the following 11 operation modes. 1. Read cycle 2. Early write cycle 3. Delayed write cycle 4. Read- modify-write cycle 5. RAS-only refresh cycle 6. CAS-before-RAS refresh cycle 7. Self refresh cycle(HM51S4260C) 8. Fast page mode read cycle 9. Fast page mode early write cycle 10. Fast page mode delayed write cycle 11. Fast page mode read- modify-write cycle Inputs RAS LCAS UCAS WE OE Output Operation H H H D D Open Standby H L L H L Valid Standby L L L H L L L L Valid Read cycle L* 2 D Open Early write cycle 2 H Undefined Delayed write cycle L L L L* L L L H to L L to H Valid Read-modify-write cycle L H H D D Open RAS-only refresh cycle H to L H L D D Open CAS-before-RAS refresh cycle L H L L H to L H to L L L H to L H to L Self refresh cycle (HM51S4260C) H L Valid Fast page mode read cycle L* 2 D Open Fast page mode early write cycle 2 H Undefined Fast page mode delayed write cycle L H to L H to L L* L H to L H to L H to L L to H Valid Fast page mode read-modify-write cycle L L L H H Open Read cycle (Output disabled) Notes: 1. H: High(inactive) L: Low(active) D: H or L 2. t WCS ≥ 0 ns Early write cycle t WCS < 0 ns Delayed write cycle 3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by the earliest of UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However write OPERATION and output HIZ control are done independently by each UCAS, LCAS. ex. if RAS = H to L, LCAS = L, UCAS = H, then CAS-before-RAS refresh cycle is selected. 5 HM514260C, HM51S4260C Series Absolute Maximum Ratings Parameter Symbol Value Unit Voltage on any pin relative to V SS VT –1.0 to +7.0 V Supply voltage relative to VSS VCC –1.0 to +7.0 V Short circuit output current Iout 50 mA Power dissipation PT 1.0 W Operating temperature Topr 0 to +70 °C Storage temperature Tstg –55 to +125 °C Recommended DC Operating Conditions (Ta = 0 to +70°C)*2 Parameter Symbol Min Typ Max Unit Notes Supply voltage VSS 0 0 0 V 2 VCC (HM51(S)4260C-6/7/8) 4.5 5.0 5.5 V 1, 2 VCC (HM51(S)4260C-6R) 4.75 5.0 5.25 V 1, 2 Input high voltage VIH 2.4 — 6.5 V 1 Input low voltage VIL –1.0 — 0.8 V 1 Notes: 1. All voltage referred to VSS . 2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. 6 HM514260C, HM51S4260C Series DC Characteristics (Ta = 0 to 70°C, VCC = 5 V ±5%, VSS = 0 V) (HM51(S)4260C-6R) (Ta = 0 to 70°C, VCC = 5 V ±10%, VSS = 0 V) (HM51(S)4260C-6/7/8) HM514260C, HM51S4260C -6/-6R -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Test Conditions Operating current*1, *2 I CC1 — 150 — 140 — 125 mA RAS, UCAS or LCAS cycling t RC = min Standby current I CC2 — 2 — 2 — 2 mA TTL interface RAS, UCAS, LCAS = VIH Dout = High-Z — 1 — 1 — 1 mA CMOS interface RAS, UCAS, LCAS, WE, OE ≥ V CC – 0.2 V Dout = High-Z Standby current (L-version) I CC2 — 200 — 200 — 200 µA CMOS interface RAS, UCAS, LCAS, OE, WE ≥ V CC – 0.2 V Dout = High-Z RAS-only refresh current*2 I CC3 — 140 — 130 — 110 mA t RC = min Standby current *1 I CC5 — 5 5 5 RAS = VIH, UCAS or LCAS = VIL Dout = enable CAS-before-RAS refresh current *2 I CC6 — 140 — 130 — 110 mA t RC = min Fast page mode current*1, *3 I CC7 — 150 — 130 — 120 mA t PC = min Battery backup current*4 (Standby with CBR refresh) (L-version) I CC10 — 300 — 300 — 300 µA Standby: CMOS interface Dout = High-Z CBR refresh: tRC = 250 µs t RAS ≤ 1 µs, UCAS, LCAS = VIL WE, OE = VIH Self-refresh mode current (HM51S4260C) I CC11 — 1 1 1 mA CMOS interface RAS, UCAS, LCAS ≤ 0.2 V, Dout = High-Z Self-refresh mode current (HM51S4260CL) I CC11 — 200 — 200 µA CMOS interface RAS, UCAS, LCAS ≤ 0.2 V, Dout = High-Z — — — — 200 — 7 mA HM514260C, HM51S4260C Series DC Characteristics (Ta = 0 to 70°C, VCC = 5 V ±5%, VSS = 0 V) (HM51(S)4260C-6R) (Ta = 0 to 70°C, VCC = 5 V ±10%, VSS = 0 V) (HM51(S)4260C-6/7/8) (cont) HM514260C, HM51S4260C -6/-6R -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Test Conditions Input leakage current I LI –10 10 –10 10 –10 10 µA 0 V ≤ Vin ≤ 6.5 V Output leakage current I LO –10 10 –10 10 –10 10 µA 0 V ≤ Vout ≤ 6.5 V, Dout = disable Output high voltage VOH 2.4 VCC 2.4 VCC 2.4 VCC V High Iout = –5.0 mA Output low voltage VOL 0 0.4 0 0.4 0 0.4 V Low Iout = 4.2 mA Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while UCAS and LCAS = VIH. 4. VIH ≥ V CC – 0.2 V, 0 ≤ V IL ≤ 0.2 V, Address can be changed once or less while RAS = VIL 5. All the V CC pins shall be supplied with the same voltage. And all the VSS pins shall be supplied with the same voltage. Capacitance (Ta = +25°C, VCC = 5 V ±5%) (HM51(S)4260C-6R) (Ta = +25°C, VCC = 5 V ±10%) (HM51(S)4260C-6/7/8) Parameter Symbol Typ Max Unit Notes Input capacitance (Address) CI1 — 5 pF 1 Input capacitance (Clocks) CI2 — 7 pF 1 Output capacitance (Data-in, Data-out) CI/O — 10 pF 1, 2 Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. UCAS and LCAS = VIH to disable Dout 8 HM514260C, HM51S4260C Series AC Characteristics (Ta = 0 to 70°C, VCC = 5 V ±5%, VSS = 0 V) (HM51(S)4260C-6R)*1, *14, *15, *17, *18 (Ta = 0 to 70°C, VCC = 5 V ±10%, VSS = 0 V) (HM51(S)4260C-6/7/8)*1, *14, *15, *17, *18 Test Conditions • • • Input rise and fall time: 5 ns Input timing reference levels: 0.8 V, 2.4 V Input levels: 0 V, 3 V Output load: 2 TTL gate + CL (50 pF) (HM51(S)4260C-6R) (Including scope and jig) 2 TTL gate + CL (100 pF) (HM51(S)4260-6/7/8) (Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters) HM514260C, HM51S4260C -6/-6R -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Notes Random read or write cycle time t RC 110 — 130 — 150 — ns RAS precharge time t RP 40 — 50 — 60 — ns RAS pulse width t RAS 60 10000 70 10000 80 10000 ns CAS pulse width t CAS 15 10000 20 10000 20 10000 ns Row address setup time t ASR 0 — 0 — 0 — ns Row address hold time t RAH 10 — 10 — 10 — ns Column address setup time t ASC 0 — 0 — 0 — ns 19 Column address hold time t CAH 15 — 15 — 15 — ns 19 RAS to CAS delay time t RCD 20 45 20 50 20 60 ns 8 RAS to column address delay time t RAD 15 30 15 35 15 40 ns 9 RAS hold time t RSH 15 — 20 — 20 — ns CAS hold time t CSH 60 — 70 — 80 — ns CAS to RAS precharge time t CRP 10 — 15 — 15 — ns OE to Din delay time t ODD 15 — 20 — 20 — ns OE delay time from Din t DZO 0 — 0 — 0 — ns CAS setup time from Din t DZC 0 — 0 — 0 — ns Transition time (rise and fall) tT 3 50 3 50 3 50 ns Refresh period t REF — 8 — 8 — 8 ms Refresh period (L-version) t REF — 128 — 128 — 128 ms 9 23 20 7 HM514260C, HM51S4260C Series Read Cycle HM514260C, HM51S4260C -6/-6R -7 -8 Min Max Parameter Symbol Min Max Min Max Unit Notes Access time from RAS t RAC — 60 — 70 — 80 ns 2, 3 Access time from CAS t CAC — 15 — 20 — 20 ns 3, 4, 13 Access time from address t AA — 30 — 35 — 40 ns 3, 5, 13 Access time from OE t OAC — 15 — 20 — 20 ns 23 Read command setup time t RCS 0 — 0 — 0 — ns 19 Read command hold time to CAS t RCH 0 — 0 — 0 — ns 16, 19 Read command hold time to RAS t RRH 0 — 0 — 0 — ns 16 Column address to RAS lead time t RAL 30 — 35 — 40 — ns Output buffer turn-off time t OFF1 0 15 0 15 0 15 ns 6 Output buffer turn-off to OE t OFF2 0 15 0 15 0 15 ns 6 CAS to Din delay time t CDD 15 — 15 — 15 — ns Write Cycle HM514260C, HM51S4260C -6/-6R -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Notes Write command setup time t WCS 0 — 0 — 0 — ns 10, 19 Write command hold time t WCH 15 — 15 — 15 — ns 19 Write command pulse width t WP 10 — 10 — 10 — ns Write command to RAS lead time t RWL 20 — 20 — 20 — ns Write command to CAS lead time t CWL 20 — 20 — 20 — ns 21 Data-in setup time t DS 0 — 0 — 0 — ns 11 Data-in hold time t DH 15 — 15 — 15 — ns 11 CAS to OE delay time t COD — 0 — 0 — 0 ns 23 10 HM514260C, HM51S4260C Series Read-Modify-Write Cycle HM514260C, HM51S4260C -6/-6R -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Notes Read-modify-write cycle time t RWC 150 — 180 — 200 — ns RAS to WE delay time t RWD 80 — 95 — 105 — ns 10 CAS to WE delay time t CWD 35 — 45 — 45 — ns 10 Column address to WE delay time t AWD 50 — 60 — 65 — ns 10, 13 OE hold time from WE t OEH 15 — 20 — 20 — ns Refresh Cycle HM514260C, HM51S4260C -6/-6R -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Note CAS setup time (CBR refresh cycle) t CSR 10 — 10 — 10 — ns 19 CAS hold time (CBR refresh cycle) t CHR 10 — 10 — 10 — ns 20 RAS precharge to CAS hold time t RPC 10 — 10 — 10 — ns 19 CAS precharge time in normal mode t CPN 10 — 10 — 10 — ns 22 Fast Page Mode Cycle HM514260C, HM51S4260C -6/-6R -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Notes Fast page mode cycle time t PC 40 — 45 — 50 — ns Fast page mode CAS precharge time t CP 10 — 10 — 10 — ns 22 Fast page mode RAS pulse width t RASC — 100000 — 100000 — 100000 ns 12 Access time from CAS precharge t ACP — 35 — 40 — 45 ns 3, 13, 20 RAS hold time from CAS precharge t RHCP 35 — 40 — 45 — ns Fast page mode read-modify-write cycle t CPW CAS precharge to WE delay time 55 — 65 — 70 — ns Fast page mode read-modify-write cycle t PCM time 80 — 95 — 100 — ns 11 HM514260C, HM51S4260C Series Self refresh Mode HM51S4260C -6/-6R -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Notes RAS pulse width (self refresh) t RASS 100 — 100 — 100 — µs RAS precharge time (self refresh) t RPS 110 — 130 — 150 — ns CAS hold time (self refresh) t CHS –50 — –50 — –50 — ns 24, 25, 26 21 Notes: 1. AC measurements assume t T = 5 ns. 2. Assumes that t RCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 3. Measured with a load circuit equivalent to 2 TTL loads and 100 pF (HM51(S)4260C-6/7/8), 2 TTL 50 pF (HM51(S)4260C-6R). 4. Assumes that t RCD ≥ tRCD (max) and tRAD ≤ tRAD (max). 5. Assumes that t RCD ≤ tRCD (max) and tRAD ≥ tRAD (max). 6. t OFF (max) defines the time at which the output achieves the open circuit condition and is not referred to output voltage levels. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH and VIL. 8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only, if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only, if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 10. t WCS , t RWD, t CWD and t AWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only: if tWCS ≥ tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t RWD ≥ tRWD (min), tCWD ≥ t CWD (min), tAWD ≥ tAWD (min) and tCPW ≥ tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 11. These parameters are referred to CAS leading edge in an early write cycle and to WE leading edge in a delayed write or a read-modify-write cycle. 12. t RASC defines RAS pulse width in fast page mode cycles. 13. Access time is determined by the longest among tAA, t CAC and t ACP. 14. An initial pause of 100 µs is required after power up followed by a minimum of eight initialization cycles (RAS-only refresh cycle or CAS-before-RAS refresh cycle). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles is required. 15. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 16. Either t RCH or tRRH must be satisfied for a read cycle. 17. When both UCAS and LCAS go low at the same time, all 16-bits data are written into the device. UCAS and LCAS cannot be staggered within the same write/read cycles. 18. All the V CC and VSS pins shall be supplied with the same voltages. 19. t ASC, tCAH , t RCS , t WCS , t WCH, t CSR and t RPC are determined by the earlier falling edge of UCAS or LCAS. 20. t CRP , t CHR, t ACP, tRCH and t CPW are determined by the later rising edge of UCAS or LCAS. 21. t CWL, t DH, t DS and t CHS should be satisfied by both UCAS and LCAS. 12 HM514260C, HM51S4260C Series @ À À@ 22. t CPN and t CP are determined by the time that both UCAS and LCAS are high. 23. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large VCC/VSS line noise, which causes to degrade VIH min/VIL max level. 24. If you use distributed CBR refresh mode with 15.6 µs interval in normal read/write cycle, CBR refresh should be executed within 15.6 µs immediately after exiting from and before entering into self refresh mode. 25. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 512 cycles of distributed CBR refresh with 15.6 µs interval should be executed within 8 ms immediately after exiting from and before entering into the self refresh mode. 26. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. 27. H or L (H: VIH (min) ≤ V IN ≤ V IH (max), L: VIL (min) ≤ V IN ≤ V IL (max)) Invalid Dout 13 HM514260C, HM51S4260C Series Notes concerning 2CAS control Please do not separate the UCAS/LCAS operation timing intentionally. UCAS/LCAS are allowed under the following conditions. However skew between (1) Each of the UCAS/LCAS should satisfy the timing specifications individually. (2) Different operation mode for upper/lower byte is not allowed; such as following. RAS Delayed write UCAS Early write LCAS WE (3) Closely separated upper/lower byte control is not allowed. However when the condition (tCP ≤ tU L) is satisfied, fast page mode can be performed. RAS UCAS LCAS t UL 14 HM514260C, HM51S4260C Series Timing Waveforms*27 Read Cycle t RC t RAS RAS tT t RP t RSH t CRP t CAS t CSH t RCD UCAS LCAS t ASR t RAD t RAL t CAH t RAH t ASC Address Column Row t RCH t RCS t RRH WE t CAC t OFF1 t AA High-Z Dout Dout t RAC t OAC t DZC Din t OFF2 t CDD High-Z t ODD t DZO OE 15 HM514260C, HM51S4260C Series Early Write Cycle t RC t RAS t RP RAS tT t RSH t RCD t CAS t CRP t CSH UCAS LCAS t ASR t RAH Address t ASC Row t CAH Column t WCH t WCS WE t DS Din Dout t DH Din High-Z * OE : H or L 16 HM514260C, HM51S4260C Series Delayed Write Cycle t RC t RAS t RP RAS t CSH t CRP tT t RCD t RSH t CAS UCAS LCAS t RAH Address t CWL t RWL t ASC t ASR t CAH Column Row t RCS t WP WE t DH t DS Din Din t DZC t DZO Dout t OEH t ODD High-Z t COD *Invalid Dout t OFF2 OE * Do not enable Dout during delayed write cycle. 17 HM514260C, HM51S4260C Series Read-Modify-Write Cycle t RWC tT t RP RAS t CRP t RCD UCAS LCAS t RAD t ASR t ASC t RAH Address t CAH Column Row t CWL t RCS t CWD t RWL t AWD t WP t AA WE t RWD t CAC t RAC t DS t DZC High-Z Din Dout t DH High-Z Din Dout t OEH t OAC t OFF2 t DZO t ODD OE 18 HM514260C, HM51S4260C Series RAS-Only Refresh Cycle t RC t RP t RAS RAS tT t CRP t CRP t RPC UCAS LCAS t RAH t ASR Address Dout Row High-Z * OE, WE : H or L ** Refresh address : A0 – A8 (AX0 – AX8) 19 HM514260C, HM51S4260C Series CAS-Before-RAS Refresh Cycle t RC t RP t RAS ** t RP t RC t RAS ** t RP RAS tT t RPC t CPN t RPC t CSR t CHR t CPN t CRP t CSR t CHR UCAS LCAS Address t OFF1 Dout High-Z * WE : H or L > tRAS (max). ** Do not extend tRAS _ Untested self refresh mode may be activated and loss of data may be resulted (HM514260C). 20 HM514260C, HM51S4260C Series Fast Page Mode Read Cycle t RASC t RP t RHCP RAS tT t CAS t RCD t CRP t RSH t PC t CSH t CP t CAS t CAS t CP UCAS LCAS t RAD t ASR Address t CAH t RAH t ASC Row t ASC t ASC t CAH Column Column Column t RRH t RCS t RCS t RCH t RCH t RCS t RAL t CAH t RCH WE t CDD t DZC Din t DZC High-Z High-Z t ODD t CAC t CAC t AA t RAC High-Z t CAC t AA t ACP t ACP t OFF1 Dout t DZO High-Z t AA t OFF1 Dout t CDD t CDD t DZC t OFF1 t DZO Dout t OAC Dout t ODD t DZO t OFF2 t OFF2 OE t OAC 21 t ODD t OAC t OFF2 HM514260C, HM51S4260C Series Fast Page Mode Early Write Cycle t RASC t RP RAS t CSH tT t CAS t RCD t RSH t PC t CP t CAS t CP t CAS t CRP UCAS LCAS t ASR Address t RAH Row t ASC t CAH t ASC Column t WCS t WCH t CAH t ASC Column Column t WCS t CAH t WCH t WCS t WCH WE t DS Din Dout t DS t DS t DH t DH t DH Din Din Din High-Z * OE : H or L 22 HM514260C, HM51S4260C Series Fast Page Mode Delayed Write Cycle t RASC t RP RAS t CSH t RSH t PC tT t CAS t RCD t CP t CP t CAS t CAS t CRP UCAS LCAS t ASC t ASR t CAH t RAH Address Row t CAH t ASC Column t ASC t CWL Column t CAH Column t CWL t CWL t RCS t WP t RWL t WP t WP WE t DH t DS Din t DH t RCS t DS Din Din t RCS t DH t DS Din t OEH High-Z Dout t ODD OE 23 HM514260C, HM51S4260C Series Fast Page Mode Read-Modify-Write Cycle t RP t RASC RAS t RCD t PCM tT UCAS LCAS t RAD t RAH Address t ACP t CAH t ASR t CRP t CP t CP Row t CAH t CAH t ASC t ASC t ASC Column Column t RCS t AWD t CWD t CWL t RWD t WP Column t CWL t AWD t CWD t RCS t WP t CPW t RCS t CPW t CWL t AWD t RWL t CWD t WP WE t CAC t DZC High-Z Din t DH t DZC t CAC High-Z Din t AA Din t DS t DH t DZC High-Z Din t CAC t DZO t OAC t OEH t OAC Dout t DZO t DH t AA t RAC Dout t ACP t DS t DS t OEH t OFF2 t OEH Dout Dout t OFF2 t OAC t DZO t OFF2 OE t ODD t ODD 24 t ODD HM514260C, HM51S4260C Series Self Refresh Cycle t RASS t RP t RPS RAS tT t RPC t CPN t CRP t CSR t CHS UCAS LCAS Address t OFF1 High-Z Dout * WE, OE : H or L The low self refresh current is achieved by introducing extremely long internal refresh cycle. Therefore some care needs to be taken on the refresh. 1. Please do not use tRASS timing, 10 µs ≤ tRASS ≤ 100 µs. During this period, the device is in transition state from normal operation mode to self refresh mode. If tRASS ≥ 100 µs, then RAS precharge time should use tRPS instead of tRP. 2. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 512 cycles of distributed CBR refresh with 15.6 µs interval should be executed within 8 ms immediately after exiting from and before entering into the self refresh mode. 3. If you use distributed CBR refresh mode with 15.6 µs interval in normal read/write cycle, CBR refresh should be executed within 15.6 µs immediately after exiting from and before entering into self refresh mode. 4. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. 25 HM514260C, HM51S4260C Series Package Dimensions HM51(S)4260CJ/CLJ Series (CP-40DA) Unit: mm 25.80 26.16 Max 0.43 ± 0.10 1.27 2.85 ± 0.12 +0.25 –0.17 1.30 Max 0.80 10.16 ± 0.13 20 0.74 3.50 ± 0.26 1 11.18 ± 0.13 21 40 9.40 ± 0.25 0.10 26 HM514260C, HM51S4260C Series HM51(S)4260CTT/CLTT Series (TTP44/40DB) 23 10.16 44 18.41 18.81 Max 35 32 Unit: mm 22 0.13 M 11.76 ± 0.20 +0.075 –0.025 0 – 5° 0.10 0.145 1.20 Max 1.005 Max 27 0.80 0.50 ± 0.10 0.68 0.27 ± 0.07 10 13 0.80 0.13 ± 0.05 1