TRIQUINT TQ9303

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TQ9303
Figure 1. TQ9303 Block Diagram
Data
10
Control
2
Data
32
Parity
TQ9501
or
GA9101
Tx
2
Optical Tx
or
Copper
Interface
4
Control
Fibre Channel
Encoder/Decoder
11
2
Data
Features
32
Parity
• Compliant with ANSI X3T11
Fibre Channel Standard
4
Data
Control
10
Control
2
12
TQ9502
or
GA9102
Rx
2
Optical Rx
or
Copper
Interface
The TQ9303 ENDEC (ENcoder/DECoder) implements 8b/10b encoding
and decoding, ordered set encoding and decoding, and parity checking
and generation as defined in the Fibre Channel Physical Signaling
Interface Standard (FC-PH). The ENDEC fully implements the FC-1 layer
of the Fibre Channel Standard. Implemented in a 0.8-micron CMOS
process, the ENDEC also performs 32-bit CRC checking and generation
as defined in the FC-2 layer of the Fibre Channel specification.
The TQ9303 ENDEC interfaces directly to TriQuint’s FC-0 layer Fibre Channel
Transmitter (Tx) and Receiver (Rx) chipsets at the speeds shown below:
FC Rate
Transmitter
Receiver
Data Rate (Mbaud)
FC-266
FC-531
FC-1063
GA9101
TQ9501
TQ9501
GA9102
TQ9502
TQ9502
194–266
500–625
1000–1250
• Full implementation of
Fibre Channel’s FC-1 layer
DATACOM
PRODUCTS
TQ9303
ENDEC
HOST
• Interfaces directly with
TriQuint’s GA9101/GA9102
and TQ9501/TQ9502 FC-0
Fibre Channel chipsets
• Suitable for proprietary serial
links (virtual ribbon cable)
• Implements 8b/10b encoding
and decoding
• Implements ordered set
encoding and decoding
• Checks and generates 32-bit
CRC and parity
• 10-bit TTL-compatible interface
to Transmitter and Receiver
• 32-bit interface to the host
• Fully synchronous operation
• 160-pin PQFP
Triquint’s Transmitter and Receiver devices are designed with TriQuint’s
proprietary 0.7-micron GaAs process. The Tx and Rx interface directly to
copper-based electrical media or to a fiber-optic module. The Transmitter
performs parallel-to-serial conversion on the encoded data and generates
the internal high-speed clock for the serial output data stream. The Receiver
recovers the clock and data from the input serial stream, performs serialto-parallel conversion, and detects and aligns on the K28.5 character.
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1
TQ9303
Fibre Channel provides a transport vehicle for Intelligent
Peripheral Interface (IPI) and Small Computer System
Interface (SCSI) upper layer command sets, HighPerformance Parallel Interface (HIPPI) data link layer,
and other user-defined command sets. Fibre Channel
replaces the SCSI, IPI, and HIPPI physical interfaces
with a protocol-efficient alternative that provides
performance improvements over distance and speed.
Fibre Channel is optimized for predictable transfers of
large blocks of data such as those used in file transfers
between processors (such as super computers, mainframes, and super minis), storage systems (such as disk
and tape drives), communications devices, and outputonly devices (such as laser printers and raster scan
graphics terminals). The Fibre Channel protocol is
implemented in hardware, making it simple, efficient,
and robust.
The lower level physical interface is decoupled from the
higher level protocol, allowing Fibre Channel to be configured with various topologies. Point-to-point, multi-drop
bus, ring, and cross-point switch topologies are permitted in Fibre Channel, optimizing it for specific applications.
Fibre Channel supports distances up to 10␣ Km at baud
rates of 132.8125␣ Mbaud to 1.0625␣ Gbaud. Coax and
STP (Shielded Twisted Pair) are used at lower data
rates and shorter distances, while fiber-optic cables are
used for higher data rates and longer distances.
Figure 2. TQ9303 ENDEC Block Diagram
20 17
40
40
Word-toHalf-Word
Shifter
Mux
17
8b/10b
Encoder
Half-Word- 10
to-Byte
Shifter
Mux
20
Register
8
Register
CTXC0,
CTXC1,
CTXP0..3,
CTXRAWA,
CTXRAWB
CTXRAW,
CTXPENN,
CTXPMODE
32
17
Parity
Checker/
Generator
3
Register
CTXD0..31
CTXPERR
CTXCERR
CTXCLK
CTXWREF
Ordered Set
Encoder
10
BTXD0..9
32-BIT CRC
Generator/
Checker
Word Half Word Byte
Clk
Clk
Clk
BTXCKIN
BTXCKOUT
Clock Generator
ENCODER SECTION
RESETN
DECODER SECTION
1
RXERROR
CRXP0..3,
CRXS0,
CRXS2..4
RAW Rx,
RXPMODE
CRXS1
CRXS5
8
40 Half-Wordto-Word
Shifter
36
4
2
Mux
16
16
1
10b/8b
Decoder
20
Byte-toHalf-Word
Shifter
10
BRXD0..9
3
Parity
Generator
2
32-Bit CRC
Checker
Line State
Decoder
Ordered Set
Decoder
Word Sync
Detector
Word Half Word Byte
Clk
Clk
Clk
WRDSYNC
RXCKPH0,1
CRXCLK
20
Register
Register
32
Register
CRXD0..31
20
2
Clock Generator
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BRXCLK
BRXSYNC
TQ9303
Functional Description
Encoder Section
The Encoder has several functional blocks:
Parity Check, 32-Bit CRC, Ordered Set generator,
8b/10b Encoder, and Clock Generator. The Encoder
section has two modes of operation: Normal mode and
Raw mode. In the Normal mode, the Encoder section
receives a word from the host interface, checks parity,
calculates CRC, divides the word into bytes, encodes
them using 8b/10b, and generates a 10-bit output, as
illustrated in Figure 2. In the Raw mode, the Encoder
section receives a word from the host interface without
parity check, CRC check, or 8b/10b encoding.
The following is the encode sequence data flow:
1. Word input
2. Parity check
3. Word–to–half-word conversion
4. Ordered set encoding
5. 32-bit CRC check or generate
6. Muxing between ordered set, 32-bit CRC, and
unchanged input
7. 8b/10b encoding
8. Muxing between unchanged input and
encoded word
DATACOM
PRODUCTS
The TQ9303 may be divided into two independent
functional sections: the Encoder and Decoder, as
shown in Figure 2. The Encoder section describes the
flow of data from the host to the transmitter.
Conversely, the Decoder section describes the flow of
data from the receiver to the host. Designed for fullduplex operation, the Encoder and Decoder will
transmit and receive one at a time or simultaneously.
The Encoder performs 8b/10b encoding of information
from the host to the transmitter. The Decoder performs
10b/8b decoding of information from the receiver to
the host. The host interface is denoted by a letter C (as
in CTXP), and the transmit/receive interface is denoted
by a letter B (as in BTXD0). Pins within the Encoder
section are denoted with the letters TX (as in CTXP),
and pins within the Decoder section are denoted with
RX (as in CRXS1). At the host interface, the TQ9303
has a 32-bit transmit data bus and a 32-bit receive data
bus, each with 4-bit parity and 8-bit control. The
transmitter and receiver interfaces to the TQ9303 are
10-bit data buses. Table␣ 5 includes all the pin
descriptions. Detailed descriptions of the Encoder and
Decoder sections follow.
9. Half-word–to–byte conversion
10. Byte output
Parity Check Block
Parity check depends on the TXPENN (Transmit Parity
ENable Not) input. TXPENN high ignores parity, while
TXPENN low checks parity for each byte on the data
bus, CTXD0..31. There are four parity bits (CTXP0..3),
each bit corresponding to a byte of data, as follows:
CTXP0 to CTXD0..7, CTXP1 to CTXD8..15, CTXP2 to
CTXD16..23, and CTXP3 to CTXD24..31. Control bit
TXPMODE (Transmit Parity MODE) alters the normal
meaning of CTXP3. TXPMODE low is the normal mode,
where CTXP3 checks for parity for CTXD24..31. With
TXPMODE high, CTXP3 checks for parity for
CTXD24..31 and CTXC0. CTXC0 is a control input
which indicates whether CTXD0..31 is data or an
ordered set. An ordered set is a Fibre Channel word
where the most significant byte is composed of a valid
special character, K28.5, as defined in the standard.
Appendix A includes a table of valid special characters.
The parity bits follow odd parity convention, where it is
high if the number of ones is even and low if the
number of ones is odd.
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3
TQ9303
CTXPERR (Transmit Parity ERRor) is driven high
when an error is detected in the parity check mode.
When parity checking is disabled, CTXPERR is driven
low. In Raw Mode transmit, where the data flow
bypasses the parity check, 32-bit CRC, 8b/10b encoder,
and ordered set encoder, CTXPERR is driven low.
32-Bit CRC Block
32-bit Cyclic Redundancy Checking (CRC) generates
or checks CRC, depending on CTXC1. CTXC1 high
generates CRC, while CTXC1 low checks CRC for the
incoming frame. The CRC used in Fibre Channel is the
same as FDDI's frame check sequence, where a 32bit CRC is computed for every frame, starting after
SOF (Start Of Frame) and ending a byte before EOF
(End Of Frame). The resulting 32-bit CRC is
automatically inserted into the frame before EOF.
In the check CRC mode, CTXCERR (Transmit Crc
ERRor) is driven high when a CRC error is detected.
In the generate CRC mode, CTXCERR is driven low. In
Raw Mode transmit where the data flow bypasses the
parity check, 32-bit CRC, 8b/10b encoder, and ordered
set encoder, CTXCERR is driven low.
The Generate CRC mode timing diagrams are shown in
Figure 3. CTXC1 is high for the entire frame, when
generating CRC. CTXC0 is high only for the duration of
SOF, indicating that the input word (CTXD0..31) is an
ordered set. Similarly, CTXC0 is high for the duration of
EOF, which is another ordered set. The 32-bit CRC
block computes the CRC for data after SOF and before
EOF. The resulting CRC is inserted between the last
data word and EOF at the output (BTXD0..9).
The Check CRC mode timing diagrams are shown in
Figure 4. CTXC1 is low for the whole frame when
checking CRC. CTXC0 is high only for the duration of
SOF, indicating that the input word (CTXD0..31) is an
ordered set. Similarly, CTXC0 is high for the duration of
EOF, another ordered set. 32-bit CRC begins after SOF
Figure 3. Generate CRC Mode TIming
CRC Computation
CTXD0..31
SOF
D0
D1
Dn
EOF
Dn-1
Dn
"d"
Idle
CTXC1
CTXC0
BTXD0..9
4 Bytes
SOF
4
D0
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CRC
EOF
TQ9303
Figure 4. Check CRC Mode TIming
CRC Computation
CTXD0..31
SOF
D0
D1
Dn
CRC
Dn-1
Dn
EOF
Idle
CTXC1
CTXC0
DATACOM
PRODUCTS
CTCXERR
BTXD0..9
4 Bytes
SOF
D0
and ends before EOF. CTXCERR remains low if the
computed CRC matches the CRC input on CTXD0..31.
CTXCERR is driven high for one word cycle after the
end of EOF.
If CTXC1␣ is␣ high (generate CRC) then the ENDEC will
add one word (the CRC) to the user’s data frame before
encoding the EOF. In this situation, when the user
commands the ENDEC to encode an EOF, it is latched
for one CTXCLK cycle while the ENDEC inserts the
generated CRC in the data stream. Then the requested
EOF is encoded. During the encoding of the EOF (that
is, the one that was latched for encoding after the CRC
was inserted) the ENDEC ignores the CTX inputs.
Ordered Set Generator Block
An ordered set is a Fibre Channel word in which the
first byte is a K28.5 special character, followed by valid
data characters. Appendix B contains tables for the
ordered set coding scheme. When CTXC0 is high, the
ordered set generator generates an ordered set from
CRC
EOF
the most significant byte of the input data, CTXD24..31.
Although only the most significant byte of the input
word is required for generating an ordered set, and
lower order bits CTXD0..23 are “don’t cares” for
encoding the ordered set, parity checking is performed
on the word. Valid word parity must be maintained to
prevent parity errors.
If a parity or CRC error is detected within a frame,
some EOF ordered sets are modified, indicating an
invalid frame. Ordered sets EOFN (EOF Normal) and
EOFT (EOF Terminate) are modified to EOFNI (EOF
Normal–Invalid).
Any ordered set can be sent or received. If the ordered
set desired is not in the predefined set of Fibre Channel
ordered sets, the user can create it using the “special”
ordered set commands (see Appendix B). For instance,
to send “K28.5, D0.0, D31.7, D0.0,” the user would
send 8500FF00h on CTXD0..31 while holding CTXC0
high. When receiving this same “special” ordered set
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5
TQ9303
(which does not correspond to any predefined Fibre
Channel ordered set) the ENDEC will send the user the
same value, 8500FF00h, while holding CRXS0 high. It
is up the the user to examine the second, third, and
fourth bytes of “special” ordered sets to identify them.
in raw mode, a “raw” word may be inserted into the
data flow at any time, although running disparity will be
forced negative and the word sync detector state
machine will reset.
Proprietary Link Mode
8b/10b Encoder Block
The 8b/10b Encoder encodes 8-bit-wide data to 10-bitwide data to improve its transmission characteristics.
The 8b/10b coding scheme maintains the signal DC
balance by keeping the same number of ones and zeros
for easier receiver designs, provides good transition
density for improved clock recovery, and improves
error checking. It also forces the correct running
disparity when encoding line states, idles, or receiverready ordered sets. Appendix A contains the lookup
tables for the 8b/10b coding scheme.
The PL_IDLE (Proprietary Link IDLE) input can be used
to simplify designs that do not have to conform to Fibre
Channel standards. In such designs the CTXC0 input is
driven low (that is, grounded) and the PL_IDLE pin is
used to distinguish data from nondata. The PL_IDLE
pin controls a bit logic in front of the input registers of
the CTXC0 and CTXD24..31 inputs. It was added to
make it easier for users who aren’t concerned with the
Fibre Channel protocol, but simply want to control the
transmission of data without habing to mux control
information into their data paths in order to control the
CTXD24..31 pins for ordered set control.
Clock Generator Block
The Clock Generator generates word, half-word, and
byte clocks required by other blocks in the Encoder. It
uses BTXCKIN (a byte clock) from the transmitter as a
reference clock. For example, using Fibre Channel data
rates, BTXCKIN runs at 106.25␣ MHz using FC1063,
53.125␣ MHz using FC531, and 26.5625␣ MHz using
FC266. The Clock Generator generates BTXCKOUT for
clocking BTXD0..9. It also generates CTXWREF, a word
clock used by the host to generate CTXCLK, which
clocks the host I/O registers. CTXCLK runs at
25.5625␣ MHz using FC1063, 13.28125␣ MHz using
FC531, and 6.640625␣ MHz using FC266.
Raw Mode Transmit
In Raw Mode Transmit where TXRAW is high for the
whole frame, the input data word bypasses the parity
check, ordered set generator, CRC, and 8b/10b, and is
directly converted to bytes of data. The word-to-byte
mapping of input to output is listed in Table␣ 1. Note that
6
On the rising edge of CTXCLK on the first cycle of
PL_IDLE going high, the input registers for CTXC0 and
CTXD24..31 are “jammed” with the value that would
make the ENDEC encode an EOFa. As long as PL_IDLE
is held high, these input registers are jammed with the
value that would make the ENDEC encode an IDLE
ordered set. If CTXC1 is low (check mode) CTXERR will
properly reflect the validity of CRC contained in the
user’s data (assuming the user’s data contains CRC), or
it can be ignored if no CRC is used. If CTXC1 is high
(generate mode), the ENDEC will insert CRC before
encoding the EOFa followed by IDLEs. This creates a
situation in which the user’s data will begin as soon as
PL_IDLE is dropped (with no preceding SOF); but it
does not present a problem for the ENDEC, because the
CRC blocks in both Rx and Tx halves are initialized by
any ordered set. Thus, the IDLE ordered set that
preceeds the user’s data is sufficient to ensure proper
CRC calculation.
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TQ9303
Table 1. Raw Mode I/O Mapping
FIRST
BYTE
FIRST SERIAL BIT IN TX/RX
SECOND
BYTE
THIRD
BYTE
LAST SERIAL BIT IN TX/RX
FOURTH
BYTE
Bit
ENCODE: Word to Bytes
DECODE: Bytes to Word
39
CTXC0
BTXD0
BRXD0
CRXS0
38
CTXP3
BTXD1
BRXD1
CRXP3
37
CTXD31
BTXD2
BRXD2
CRXD31
36
CTXD30
BTXD3
BRXD3
CRXD30
35
CTXD29
BTXD4
BRXD4
CRXD29
34
CTXD28
BTXD5
BRXD5
CRXD28
33
CTXD27
BTXD6
BRXD6
CRXD27
32
CTXD26
BTXD7
BRXD7
CRXD26
31
CTXD25
BTXD8
BRXD8
CRXD25
30
CTXD24
BTXD9
BRXD9
CRXD24
29
CTXC1
BTXD0
BRXD0
CRXS2
28
CTXP2
BTXD1
BRXD1
CRXP2
27
CTXD23
BTXD2
BRXD2
CRXD23
26
CTXD22
BTXD3
BRXD3
CRXD22
25
CTXD21
BTXD4
BRXD4
CRXD21
24
CTXD20
BTXD5
BRXD5
CRXD20
23
CTXD19
BTXD6
BRXD6
CRXD19
22
CTXD18
BTXD7
BRXD7
CRXD18
21
CTXD17
BTXD8
BRXD8
CRXD17
20
CTXD16
BTXD9
BRXD9
CRXD16
19
CTXRAWA
BTXD0
BRXD0
CRXS3
18
CTXP1
BTXD1
BRXD1
CRXP1
17
CTXD15
BTXD2
BRXD2
CRXD15
16
CTXD14
BTXD3
BRXD3
CRXD14
15
CTXD13
BTXD4
BRXD4
CRXD13
14
CTXD12
BTXD5
BRXD5
CRXD12
13
CTXD11
BTXD6
BRXD6
CRXD11
12
CTXD10
BTXD7
BRXD7
CRXD10
11
CTXD9
BTXD8
BRXD8
CRXD9
10
CTXD8
BTXD9
BRXD9
CRXD8
9
CTXRAWB
BTXD0
BRXD0
CRXS4
8
CTXP0
BTXD1
BRXD1
CRXP0
7
CTXD7
BTXD2
BRXD2
CRXD7
6
CTXD6
BTXD3
BRXD3
CRXD6
5
CTXD5
BTXD4
BRXD4
CRXD5
4
CTXD4
BTXD5
BRXD5
CRXD4
3
CTXD3
BTXD6
BRXD6
CRXD3
2
CTXD2
BTXD7
BRXD7
CRXD2
1
CTXD1
BTXD8
BRXD8
CRXD1
0
CTXD0
BTXD9
BRXD9
CRXD0
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DATACOM
PRODUCTS
TRANSMISSION ORDER
7
TQ9303
Proprietary Link Mode (continued)
When PL_IDLE is driven low, data words on CTXD0..31
are encoded just as in Fibre Channel operation. When
PL_IDLE is driven high, the TQ9303 encodes one EOFa
ordered set followed by IDLE ordered sets for as long
as PL_IDLE remains high.
The EOFa ordered set is used to ensure proper running
disparity. When using the PL_IDLE signal, IDLE
ordered sets do not force proper running disparity. It is
therefore necessary to transmit at least one word with
PL_IDLE low followed by at least one word with
PL_IDLE high in order to guarantee proper running
disparity.
Without proper running disparity, the receiver portion
of the TQ9303 may flag the IDLE ordered sets as
errors and prevent the word sync state machine from
reaching the synchronized state as long as the running
disparity is incorrect.
Without proper running disparity, the receiver portion
of the TQ9303 may flag the IDLE ordered sets as errors
and prevent the word sync state machine from
reaching the synchronized state as long as the running
disparity is incorrect.
generation, the CRXS1 signal is used to indicate CRC
errors. When not using the CRC, CRXS1 should be
ignored. For non-Fibre Channel designs making use of
the PL_IDLE input, the CRXSO output can be used to
distinguish received data from idle time.
Decoder Section
The Decoder has several functional blocks:
10b/8b Decoder, Ordered Set Decoder, Word Sync
Detector, Line State Decoder, 32-bit CRC Checker,
Parity Generator, and Clock Generator.
The Decoder section has two modes of operation: the
Normal mode and Raw mode. In the Normal mode, the
Decoder section takes 10 bits of data from the Receiver
output, decodes it using 10b/8b, decodes ordered sets,
checks CRC, combines four bytes into a single word
output, and generates parity. In the Raw mode, the
Decoder section directly combines the bytes into
words, bypassing 10b/8b decoding, ordered set
decoding, CRC checking, and parity generation.
The following is the decode sequence data flow:
1. Byte Input
2. Byte–to–Half-Word Conversion
3. 10b/8b Decoding
The contents and parity of CTXD0..31 and CTXP0..3 are
ignored during the word cycles when PL_IDLE is held
high. If CTXC1 is low, then CRC checking will occur,
which may cause the TXCERR signal to indicate an
error, which can be ignored in proprietary designs. If
CTXC1 is driven high, then the TQ9303 will generate a
32-bit CRC word during the first word cycle of PL_IDLE
high. During the second word cycle of PL_IDLE high,
the EOFa will be encoded followed by IDLE ordered
sets. Therefore, at least two word cycles of PL_IDLE
high between data bursts must be provided when using
CRC generation (that is, CTXC1␣ high). When using CRC
8
4. Ordered Set Decoding
5. Line State Decoding
6. Word Sync Generation
7. 32-Bit CRC Checking
8. Muxing between Ordered Set, Unchanged Input,
10b/8b Decoded Input, and Status Bits
9. Half-Word–to–Word Conversion
10. Parity Generation
11. Word Output
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TQ9303
Figure 5. Sync State Flow Diagram
The 10b/8b Decoder decodes the 10-bit input
(BRXD0..9) into 8 bits, as defined by the Fibre Channel
8b/10b coding scheme. The 10b/8b Decoder drives the
RXERROR (Receiver ERROR) high whenever errors are
detected. There are three types of errors: invalid
characters, invalid running disparities, and special
characters that are not positioned in the most
significant byte of a word. When the 10b/8b Decoder
receives a BRXSYNC of 1, it identifies the input data
byte as a K28.5 character and realigns the data in the
higher order byte of the half word. In Fibre Channel,
K28.5 characters appear only in the most significant
byte of a valid generated parity word. RXERROR remains
high for the word cycle in which the error occurred.
RESET or RAW Mode
Invalid
Word
STATE 0
Loss of Word Sync
WSYNC = 0
Three Ordered Sets
Without Errors
STATE 1
Acquired Word Sync
WSYNC = 1
Invalid Word
STATE 2
1st Invalid Word
WSYNC = 1
Two Consecutive
Valid Words
DATACOM
PRODUCTS
10b/8b Decoder Block
Invalid Word
Ordered Set Decoder Block
The Ordered Set Decoder decodes the ordered sets
from the 10b/8b Decoder output. It generates the
decoded ordered set, which is then fed into the mux
along with CRXS0. CRXS0 is a status signal which is
low for a data word and high for an ordered set. The
ordered set decoding table is included in Appendix␣ B.
Two Consecutive
Valid Words
STATE 3
2nd Invalid Word
WSYNC = 1
Invalid Word
STATE 4
3rd Invalid Word
WSYNC = 1
Two Consecutive
Valid Words
Invalid Word
Word Sync Detector Block
The Word Sync Detector contains a state machine that
monitors the number of valid ordered sets and errors
received. The Word Sync Detector drives WRDSYNCN
low to indicate that word synchronization on the link
has been established. It drives WRDSYNCN high
when word synchronization has been lost.
Figure␣ 5 illustrates how word synchronization is
established and lost. The state machine has five states:
State␣ 0␣ – Loss of Word Sync, State␣ 1␣ – Word Sync
Acquired, State␣ 2␣ – 1st Invalid Word, State␣ 3␣ – 2nd
Invalid Word, and State␣ 4␣ – 3rd Invalid Word. Upon
RESET or Raw mode at State␣ 0, the initial condition of
WRDSYNCN is high. If the Word Sync Detector
receives three consecutive ordered sets without errors,
it acquires word synchronization and moves to State␣ 1,
where WRDSYNCN is driven low. If it receives an
invalid word while in State␣ 1, it moves to State␣ 2 (1st
Invalid Word). If the Word Sync Detector receives an
invalid word while in State␣ 2, it moves to State␣ 3 (2nd
Invalid Word). If, however, it receives two consecutive
valid words, it moves back to State␣ 1. This logic applies
to State␣ 3 and State␣ 4. In State␣ 4 (3rd Invalid Word) if
the Decoder receives an invalid word, it moves to
State␣ 0 (Loss of Word Sync).
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9
TQ9303
Line State Decoder Block
Parity Generator Block
The state machine that indicates line state status
simply looks for three consecutive line state primitives
(that is, three of a kind in a row) to achieve a particular
Fibre Channel line state. Line states are used in link
initialization protocol, as described in the Fibre Channel
specification (FC-PH). A subset of the ordered sets, line
states are Fibre Channel primitive sequences which
provide information regarding the condition of the link.
The following are the four line states:
Four parity bits (CTXP0..3) are generated by the Parity
Generator. Each parity bit corresponds to a byte of
data, as follows: CRXP0 to CRXD0..7, CRXP1 to
CRXD8..15, CRXP2 to CRXD16..23, and CRXP3 to
CRXD24..31.
• Off-Line State (OLS) indicates either an internal
port failure or a transmitter power down/
diagnostics performance / initialization.
• Non-Operational State (NOS) signals a link failure.
• Link Reset (LR) recognizes the OLS and port reset
conditions.
• Link Reset Response (LRR) recognizes a link reset.
These line states are defined in Appendix␣ B. The Line
State Decoder generates CRXS2..3, the line state status
bits which advise the host as to the state of the Sync
State Machine, and CRXS4..5, the line state ID bits
which signal the occurrance of certain primitive
sequences. The status bits are shown in Tables 2 and 3.
Control bit RXPMODE (Receive Parity MODE) alters the
normal meaning of CRXP3. RXPMODE low is the
normal mode, where CRXP3 generates parity for
CRXD24..31. With RXPMODE high, however, CRXP3
generates parity for CRXD24..31 and CRXS0. CRXS0 is
a control output that indicates whether CTXD0..31 is
data or an ordered set.
The parity bits follow odd parity convention, where it is
high if the number of ones is even and low if the
number of ones is odd.
In Raw mode, the Parity Generator does not generate
parity, and the output parity bits are mapped with the
input data as shown in Table␣ 1.
Clock Generator Block
The CRC Checker computes the 32-bit cyclic
redundancy check on the received data. The CRC Error
Status bit CRXS1 is driven high when an error is
detected. In Raw mode, CRC is not checked, and
CRXS1 is driven low.
The Clock Generator generates word, half-word, and
byte clocks required by other blocks in the Decoder.
The Clock Generator uses the recovered clock, BRXCLK,
generated by the TQ9502 Receiver. For example, using
Fibre Channel data rates, BRXCLK (a byte clock) runs at
106.25␣ MHz using FC1063, 53.125␣ MHz using FC531,
and 26.5625␣ MHz using FC266.
Table 2. Line State Status Output
Table 3. Line State ID Output
32-Bit CRC Checker Block
10
CRXS3
CRXS2
Line State Status
CRXS5
CRXS4
0
0
1
1
0
1
0
1
No State
Pending State
In State
Invalid Sequence
0
0
1
1
0
1
0
1
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Line State ID
NOS – Non-Operational State
OLS – Off-Line State
LR – Link Reset
LRR – Link Reset Response
TQ9303
The Clock Generator generates CRXCLK, a word clock,
which is used for clocking the host I/O registers. The
user may place the clock edge, CRXCLK, in four places
relative to the word input, thereby giving the user
control of setup and hold times. Clock edge placement
is selected via control pins RXCKPH0 and RXCKPH1
(Receiver ClocK PHase). CRXCLK runs at 26.5625␣ MHz
using FC1063 and 13.28125␣ MHz using FC531.
The Clock Generator also receives the BRXSYNC signal,
which is used for byte alignment. The Receiver drives
BRXSYNC high when detecting a K28.5 character.
Raw Mode Receive
In Raw Mode Receive where RXRAW is high for the
whole frame, the input data word bypasses the parity
check, ordered set generator, 32-bit CRC, and 8b/10b
encoder, and is directly converted to data words. The
byte-to-word mapping of data is listed in Table␣ 1.
Figure 6. Pinout
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
Pin 1
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
TQ9303
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
CTXC0
CTXC1
CTXRAWA
CTXRAWB
CTXCERR
CTXPERR
TXPENN
PL_IDLE
CTXCLK
TSTMODE
CTXWREF
VSS1
TXPMODE
TXRAW
RXRAW
VSS3
RXPMODE
VSS2
RXCKPH1
RXCKPH0
VDD3
RESETN
VSS1
CRXCLK
VSS1
WRDSYNCN
RXERROR
CRXS5
CRXS4
VSS1
CRXS3
CRXS2
CRXS1
VDD
CRXS0
CRXP3
CRXD31
VSS1
CRXD30
CRXD29
CRXD3
VDD
CRXD4
CRXD5
VSS1
CRXD6
CRXD7
CRXP0
CRXD8
VSS1
CRXD9
CRXD10
CRXD11
VDD
CRXD12
CRXD13
VSS1
CRXD14
CRXD15
VSS2
CRXP1
CRXD16
VSS1
CRXD17
CRXD18
CRXD19
VDD
CRXD20
CRXD21
VSS1
CRXD22
CRXD23
CRXP2
CRXD24
VSS1
CRXD25
CRXD26
VDD
CRXD27
CRXD28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DATACOM
PRODUCTS
CTXP3
CTXD31
CTXD30
CTXD29
CTXD28
CTXD27
CTXD26
CTXD25
CTXD24
VSS2
CTXP2
CTXD23
CTXD22
VSS3
CTXD21
CTXD20
CTXD19
CTXD18
CTXD17
VDD
CTXD16
CTXP1
CTXD15
CTXD14
CTXD13
CTXD12
CTXD11
CTXD10
CTXD9
VSS2
CTXD8
CTXP0
CTXD7
VDD3
CTXD6
CTXD5
CTXD4
CTXD3
CTXD2
CTXD1
CTXD0
VSS1
BTXD0
BTXD1
BTXD2
VSS1
BTXD3
BTXD4
VDD
BTXD5
BTXD6
VSS1
BTXD7
BTXD8
BTXD9
VSS1
BTXCKIN
VSS1
BTXCKOUT
VDD
BRXCLK
VSS3
BRXD0
BRXD1
BRXD2
BRXD3
VDD3
BRXD4
BRXD5
BRXD6
BRXD7
VSS3
BRXD8
BRXD9
BRXSYNC
VDD
CRXD0
CRXD1
VSS1
CRXD2
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11
TQ9303
Table 4. Pin Names
Pin
12
Description
Pin
Description
Pin
Description
Pin
Description
1
CTXD0
41
CRXD3
81
CRXD29
121
CTXP3
2
VSS
42
VDD
82
CRXD30
122
CTXD31
3
BTXD0
43
CRXD4
83
VSS
123
CTXD30
4
BTXD1
44
CRXD5
84
CRXD31
124
CTXD29
5
BTXD2
45
VSS
85
CRXP3
125
CTXD28
6
VSS
46
CRXD6
86
CRXS0
126
CTXD27
7
BTXD3
47
CRXD7
87
VDD
127
CTXD26
8
BTXD4
48
CRXP0
88
CRXS1
128
CTXD25
9
VDD
49
CRXD8
89
CRXS2
129
CTXD24
10
BTXD5
50
VSS
90
CRXS3
130
VSS
11
BTXD6
51
CRXD9
91
VSS
131
CTXP2
12
VSS
52
CRXD10
92
CRXS4
132
CTXD23
13
BTXD7
53
CRXD11
93
CRXS5
133
CTXD22
14
BTXD8
54
VDD
94
RXERROR
134
VSS
15
BTXD9
55
CRXD12
95
WRDSYNCN
135
CTXD21
16
VSS
56
CRXD13
96
VSS
136
CTXD20
17
BTXCKIN
57
VSS
97
CRXCLK
137
CTXD19
18
VSS
58
CRXD14
98
VSS
138
CTXD18
19
BTXCKOUT
59
CRXD15
99
RESETN
139
CTXD17
20
VDD
60
VSS
100
VDD
140
VDD
21
BRXCLK
61
CRXP1
101
RXCKPH0
141
CTXD16
22
VSS
62
CRXD16
102
RXCKPH1
142
CTXP1
23
BRXD0
63
VSS
103
VSS
143
CTXD15
24
BRXD1
64
CRXD17
104
RXPMODE
144
CTXD14
25
BRXD2
65
CRXD18
105
VSS
145
CTXD13
26
BRXD3
66
CRXD19
106
RXRAW
146
CTXD12
27
VDD
67
VDD
107
TXRAW
147
CTXD11
28
BRXD4
68
CRXD20
108
TXPMODE
148
CTXD10
29
BRXD5
69
CRXD21
109
VSS
149
CTXD9
30
BRXD6
70
VSS
110
CTXWREF
150
VSS
31
BRXD7
71
CRXD22
111
TSTMODE
151
CTXD8
32
VSS
72
CRXD23
112
CTXCLK
152
CTXP0
33
BRXD8
73
CRXP2
113
PL_IDLE
153
CTXD7
34
BRXD9
74
CRXD24
114
TXPENN
154
VDD
35
BRXSYNC
75
VSS
115
CTXPERR
155
CTXD6
36
VDD
76
CRXD25
116
CTXCERR
156
CTXD5
37
CRXD0
77
CRXD26
117
CTXRAWB
157
CTXD4
38
CRXD1
78
VDD
118
CTXRAWA
158
CTXD3
39
VSS
79
CRXD27
119
CTXC1
159
CTXD2
40
CRXD2
80
CRXD28
120
CTXC0
160
CTXD1
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TQ9303
Symbol
I/O
# of I/O
Interface
Description
Pin Numbers
BTXCKIN
I
1
Transmitter
Takes clock from Transmitter to generate BTXCKOUT.
17
BTXCKOUT
O
1
Transmitter
Used by Transmitter to clock in BTXD0..9.
19
BTXD0..9
O
10
Transmitter
Data Output.
3–5, 7, 8, 10, 11, 13–15
CTXWREF
O
1
Host
Reference Word Clock which can be used in signaling the
host to issue a CTXCLK.
110
CTXCLK
I
1
Host
Word Clock generated from CTXCLK to clock in/out host I/O
registers. The following signals are latched by CTXCLK:
CTXP0..3, CTXC0,1, CTXRAW, CTXPENN, CTXPMODE,
CTXPERR, CTXCERR.
112
CTXC0
I
1
Host
High indicates CTXD0..31 is an Ordered Set;
Low indicates data.
120
CTXC1
I
1
Host
High generates CRC; low checks CRC.
119
CTXD0..31
I
32
Host
Transmit data output (CTXD31 = MSB; CTXD0 = LSB).
1, 160–155, 153-151,
149–143, 141, 139–135,
133, 132, 129–122
CTXP0
I
1
Host
CTXD0..7 Odd Parity input.
152
CTXP1
I
1
Host
CTXD8..15 Odd Parity input.
142
CTXP2
I
1
Host
CTXD16..23 Odd Parity input.
131
CTXP3
I
1
Host
CTXD24..31 and optional CTXC0 Odd Parity input.
If TXPMODE is high, CTXP3 checks parity for
CTXD24..31 and CTXC0. If TXPMODE is low,
CTXP3 checks parity for CTXD24..31 only.
121
CTXRAWA
I
1
Host
Raw data bit 19.
118
CTXRAWB
I
1
Host
Raw data bit 9.
117
CTXPERR
O
1
Host
CTXPERR high indicates CTXD0..31 Parity Error.
115
CTXCERR
O
1
Host
CTXCERR high indicates CRC Error.
When in CRC Check mode, CTXC1 is low.
116
TSTMODE
I
1
Host
Normally GND. HIGH state used by vendor to monitor
delay and threshold.
111
TXRAW
I
1
Host
High selects Raw Transmit Data mode.
107
TXPENN
I
1
Host
Active Low Transmit Parity Enable; Tx checks Parity
when low.
114
TXPMODE
I
1
Host
If TXPMODE is high, CTXP3 generates parity for
CTXD24..31 and CTXC0. If TXPMODE is low,
CTXP3 generates parity for CTXD24..31 only.
108
PL_IDLE
I
1
Host
Proprietary link idle control
113
BRXCLK
I
1
Receiver
Driven by RXCLK. Clocks data from BRXD0..9.
21
BRXD0..9
I
10
Receiver
Receives RXD0..9 from Receiver.
23–26, 28–31, 33, 34
BRXSYNC
I
1
Receiver
SYNC.
35
CRXCLK
O
1
Host
CRXCLK latches CRXDO..31.
97
(Continued on next page)
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13
DATACOM
PRODUCTS
Table 5. Pin Descriptions
TQ9303
Table 5. Pin Descriptions (continued)
Symbol
I/O
# of I/O
Interface
Description
Pin Numbers
CRXD0..31
O
32
Host
Receive data output (CRXD31 = MSB; CRXD0 = LSB).
37,38,40,41,43,44,
46,47,49,51–53,55,
56,58,59,62,64–66,
68,69,71,72,74,
76,77,79–82,84
CRXS0
O
1
Host
High indicates CRXD0..31 is an Ordered Set;
Low indicates data.
86
CRXS1
O
1
Host
CRC error flag; high indicates a CRC error.
88
CRXS2,3
O
2
Host
Line state status bits. State equivalent for CRXS3
and CRXS2 from left to right, respectively:
␣ ␣ ␣ ␣ 00 - No State 01 - Pending
␣ ␣ ␣ ␣ 10 - State Rec. 11 - Bad Seq.
89,90
CRXS4,5
O
2
Host
Line state ID bits.
92,93
CRXP0
O
1
Host
CRXD0..7 Odd Parity output.
48
CRXP1
O
1
Host
CRXD8..15 Odd Parity output.
61
CRXP2
O
1
Host
CRXD16..23 Odd Parity output.
73
CRXP3
O
1
Host
CRXD24..31 and optional CRXS01 Odd Parity output.
If RXPMODE is high, CRXP3 generates Parity for
CRXD24..31 and CRXS0. If RXPMODE is low,
CRXP3 generates Parity for CRXD24..31 only.
85
RXERROR
O
1
Host
Receive Error; high indicates invalid data from the Receiver.
94
RXRAW
I
1
Host
High selects Raw Receive Data mode.
106
WRDSYNCN
O
1
Host
Word Synchronization Status Flag;
Low indicates Synchronization aqcuired.
Can be connected to SYNCEN on TQ9502/GA9102 Receiver.
95
RXPMODE
I
1
Host
Receiver Parity mode. If RXPMODE is high, CRXP3
generates Parity for CRXD24..31 and CRXS0.
If RXPMODE is low, CRXP3 generates Parity for
CRXD24..31 only.
104
RXCKPH0,1
I
2
Host
CRXCLK Phase Select pin.
101,102
RESETN
I
1
Host
Active low.
99
VDD
—
—
—
+5 Volt supply.
9,20,27,36,42,54,67,
78,87,100,140,154
GND (VSS)
—
—
—
Ground.
2,6,12,16,18,22,32,39,
45,50,57,60,63,70,75,
83,91,96,98,103,105,
109,130,134,150
14
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TQ9303
Table 6. Absolute Maximum Ratings
Parameter
Min.
Max.
Unit
Storage temperature
–65
+150
°␣ C
Ambient temperature
Supply voltage to ground
–55
–0.5
+125
+7.0
°␣ C
V
DC input voltage
–0.5
VDD + 0.5
V
DC input current
Thermal resistance (θJC)
–30
+5
5.6
mA
°C / W
Note:
Exceeding the absolute maximum ratings may damage the device.
Table 7. Operating Conditions
Range
Supply voltage
Ambient temperature
Power @ 125 MHz
Power @ DC
Note:
Unit
+5 ± 5%
V
0–70
≤4.1
0.3
°C
W
W
DATACOM
PRODUCTS
Parameter
Proper functionality is guaranteed under these conditions.
Table 8. DC Characteristics
Symbol
Description
Conditions
Min.
VOH
VOL
VIH
Output high voltage
Output low voltage
VDD = Min, IOH = –4 mA, VIN = VIH or VIL
VDD = Min, IOL = 4 mA, VIN = VIH or VIL
3.6
Input high level
2.0
VIL
Input low level
IIL
Input Leakage current
Guaranteed input logical high voltage
for all inputs
Guaranteed input logical low voltage
for all inputs
VDD = Max, VIN = 0.40V
Typ.
Max.
Unit
0.37
V
V
V
–150
0.8
V
–400
µA
Notes: • Unless otherwise specified, these values apply over the recommended operating range.
• Typical limits are: VDD = 5.0 V and TA = 25 °C.
• Input levels (VIH and VIL) are absolute values with respect to device ground, and all overshoots due to
system or tester noise are included.
• VIN, the TTL input, can be high or low.
TTL Test Load, TLL Outputs
VDD
2000 Ω
1360 Ω
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15
TQ9303
Table 9. AC Characteristics—Transmit (CTX) Timing
Parameter
Description
Abs.Min.
Rel.Min.
Abs.Max.
Rel.Max.
Unit
T1
CTXCLK Pulse Width High
12
t+4
3t – 4
ns
T2
T3
CTXCLK Pulse Width Low
CTXCLK Period
12
32
t+4
4t
3t – 4
4t
ns
ns
T4
CTXD(0..31), CTXP(0..3), CTXRAWA,
CTXRAWB, CTXPENN, CTXPMOD, CTXC0, and
1.9
ns
T5
0.9
ns
T6
T7
CTXCLK↑–to–CTXD(0..31), CTXP(0..3),
CTXRAWA, CTXRAWB, CTXPENN, CTXPMOD,
CTXC0, and CTXRAW hold time
CTXC0 and CTXC1–to–CTXCLK↑ setup time
CTXCLK↑–to–CTXC0 and CTXC1 hold time
0.8
2
ns
ns
T8
CTXCLK↑–to–CTXCERR and CTXPERR Output
2.5
CTXRAW–to–CTXCLK↑ setup time
15.5
Notes:
• “t” represents one (1) BTXCKIN period.
• Minimum setup and hold times are based on a 30-pf load on all outputs and a 50% duty cycle on CTXCLK.
Figure 7. Transmit (CTX) Timing
CTXCLK
T1
T2
T3
CTXD(0..31),
CTXP(0..3),
CTXRAWA,
CTXRAWB,
CTXPENN,
CTXPMOD,
CTXC0,
CTXRAW,
PL_IDLE
T4
T6
T5
T7
CTXC1
T8
CTXCERR,
CTXPERR
16
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ns
TQ9303
Table 10. AC Characteristics—Transmit (BTX) Timing (1)
Parameter
Description
Abs.Min.
Rel.Min.
Abs.Max.
Rel.Max.
Unit
T9
BTXCKN Pulse Width High
3.2
0.4t
0.6t
ns
T10
T11
BTXCKIN Pulse Width Low
BTXCKIN Period
3.2
8
0.4t
t
0.6t
t
ns
ns
T12
BTXD(0..9)-to-BTXCKOUT↑ setup time
(2)
(2)
(2)
(2)
T13
BTXCKOUT↑-to-BTXD(0..9) hold time
(2)
(2)
(2)
(2)
Notes: 1. “t” represents one (1) BTXCKIN period.
2. See Table 11, "Transmit (BTX) Timing Formulas,” below.
Figure 8. Transmit (BTX) Timing
T9
DATACOM
PRODUCTS
BTXCKIN
T10
T11
T12
T13
BTXD(0..9)
BTXCKOUT
Table 11. Transmit (BTX) Timing Formulas
Parameter
Note:
Formula
T12
d * t – 1.94 ns
T13
(1 – d) * t – 1.42 ns
t␣ =␣ 8␣ ns
(125␣ MHz)
t␣ =␣ 9.41␣ ns
(106.25␣ MHz)
t␣ =␣ 16␣ ns
(62.5␣ MHz)
t␣ =␣ 18.821␣ ns
(53.125␣ MHz)
2.06 ns
(1.8 ns min.)
2.58 ns
(3.4 ns min.)
2.76 ns
(2.5 ns min.)
3.28 ns
(2.1 ns min.)
6.06 ns
7.47 ns
6.58 ns
7.99 ns
“d” represents one (1) BTXCKIN duty cycle, T9␣ /␣ T11 or T9␣ /␣ (T9␣ +␣ T10). The calculations given above are made with d␣ =␣ 0.5␣ (50%).
When BTXCKIN has other than a 50% duty cycle (d <> 0.5), TSETUP and THOLD are affected by the shift in clock edges. The rising edge
of BTXCKOUT is triggered by the falling edge of BTXCKIN; thus, if the BTXCKIN high time is 2␣ ns less than the BTXCKIN low time,
then 1␣ ns must be subtracted from the setup times given abore, and 1␣ ns must be added to the hold times given above.
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17
TQ9303
Table 12. AC Characteristics—Receive (BRX) Timing
Parameter
Description
Abs.Min.
Rel.Min.
Abs.Max.
Unit
T14
BRXCLK Pulse Width High
3.2
0.4t
0.6t
ns
T15
T16
BRXCLK Pulse Width Low
BRXCLK Period
3.2
8
0.4t
t
0.6t
t
ns
ns
T17
BRXD(0..9) and BRXSYNC–to–BTXCKOUT↑
setup time
BRXCLK↑–to–BRXD(0..9) and BRXSYNC
hold time
1.25
ns
0.25
ns
T18
Note:
“t” represents one (1) BRXCLK period.
Figure 9. Receive (BRX) Timing
Figure
BRXCLK
T14
T15
T16
T17
T18
BRXD(0..9),
BRXSYNC
18
Rel.Max.
For additional information and latest specifications, see our website: www.triquint.com
TQ9303
Table 13. AC Characteristics—Receive (CRX) Timing (1)
Parameter
Description
Abs.Min.
Rel.Min.
Abs.Max.
Rel.Max.
Unit
T19
CRXCLK Pulse Width High
13
2t – 3
19
2t + 3
ns
T20
T21
CRXCLK Pulse Width Low
CRXCLK Period
13
32
2t – 3
4t
19
2t + 3
4t
ns
ns
T22
CRXD*, CRXP*, and CRXS*–to–CRXCLK↑
setup time
CRXCLK↑–to–CRXD*, CRXP*,
and CRXS* hold time
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
T23
Notes: 1. “t” represents one (1) BRXCLK period.
2. See Table 14, “Receive (CRX) Timing Formulas,” below.
DATACOM
PRODUCTS
Figure 10. Receive (CRX) Timing
CRXCLK
T19
T20
T21
CRXD(0..31),
CRXP(0..3),
RXERROR,
WRDSYNCN
T22
T23
Table 14. Receive (CRX) Timing Formulas
Parameter
RXCKPH(1:0)
0:0
0:1
1:0
1:1
0:0
0:1
1:0
1:1
Formula
0.054t␣ –␣ 0.94␣ ns
1.054t␣ –␣ 0.94␣ ns
2.054t␣ –␣ 0.94␣ ns
3.054t␣ –␣ 0.94␣ ns
3.5t␣ –␣ 0.07␣ ns
2.5t␣ –␣ 0.07␣ ns
1.5t␣ –␣ 0.07␣ ns
0.5t␣ –␣ 0.07␣ ns
t␣ =␣ 8␣ ns
(125␣ MHz)
t␣ =␣ 9.41␣ ns
(106.25␣ MHz)
t␣ =␣ 16␣ ns
(62.5␣ MHz)
t␣ =␣ 18.821␣ ns
(53.125␣ MHz)
–0.47␣ ns
7.53␣ ns
15.53␣ ns
23.53␣ ns
28.07␣ ns
20.07␣ ns
12.07␣ ns
4.07␣ ns
–0.39␣ ns
9.02␣ ns
18.43␣ ns
27.84␣ ns
33.01␣ ns
23.59␣ ns
14.18␣ ns
4.77␣ ns
0.00␣ ns
16.00␣ ns
32.00␣ ns
48.00␣ ns
56.07␣ ns
40.07␣ ns
24.07␣ ns
8.07␣ ns
0.16␣ ns
18.99␣ ns
37.81␣ ns
56.63␣ ns
65.95␣ ns
47.12␣ ns
28.30␣ ns
9.48␣ ns
For additional information and latest specifications, see our website: www.triquint.com
19
TQ9303
Table A-1. Valid Data Characters
Data Byte
Bits
Name
HGF
EDCBA 1
Current
abcdei
RD –
fghj 2
Current
abcdei
RD +
fghj 2
Data Byte
Bits
Name
HGF
EDCBA 1
Current
abcdei
RD –
fghj 2
Current
abcdei
RD +
fghj 2
D0.0
D1.0
D2.0
D3.0
D4.0
D5.0
D6.0
D7.0
D8.0
D9.0
D10.0
D11.0
D12.0
D13.0
D14.0
D15.0
D16.0
D17.0
D18.0
D19.0
D20.0
D21.0
D22.0
D23.0
D24.0
D25.0
D26.0
D27.0
D28.0
D29.0
D30.0
D31.0
D0.1
D1.1
D2.1
D3.1
D4.1
D5.1
D6.1
D7.1
D8.1
D9.1
D10.1
D11.1
D12.1
D13.1
D14.1
D15.1
D16.1
D17.1
D18.1
D19.1
D20.1
D21.1
D22.1
D23.1
D24.1
D25.1
D26.1
D27.1
D28.1
D29.1
D30.1
D31.1
D0.2
D1.2
D2.2
D3.2
D4.2
D5.2
D6.2
100111
011101
101101
110001
110101
101001
011001
111000
111001
100101
010101
110100
001101
101100
011100
010111
011011
100011
010011
110010
001011
101010
011010
111010
110011
100110
010110
110110
001110
101110
011110
101011
100111
011101
101101
110001
110101
101001
011001
111000
111001
100101
010101
110100
001101
101100
011100
010111
011011
100011
010011
110010
001011
101010
011010
111010
110011
100110
010110
110110
001110
101110
011110
101011
100111
011101
101101
110001
110101
101001
011001
0100
0100
0100
1011
0100
1011
1011
1011
0100
1011
1011
1011
1011
1011
1011
0100
0100
1011
1011
1011
1011
1011
1011
0100
0100
1011
1011
0100
1011
0100
0100
0100
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
0101
0101
0101
0101
0101
0101
0101
011000
100010
010010
110001
001010
101001
011001
000111
000110
100101
010101
110100
001101
101100
011100
101000
100100
100011
010011
110010
001011
101010
011010
000101
001100
100110
010110
001001
001110
010001
100001
010100
011000
100010
010010
110001
001010
101001
011001
000111
000110
100101
010101
110100
001101
101100
011100
101000
100100
100011
010011
110010
001011
101010
011010
000101
001100
100110
010110
001001
001110
010001
100001
010100
011000
100010
010010
110001
001010
101001
011001
1011
1011
1011
0100
1011
0100
0100
0100
1011
0100
0100
0100
0100
0100
0100
1011
1011
0100
0100
0100
0100
0100
0100
1011
1011
0100
0100
1011
0100
1011
1011
1011
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
0101
0101
0101
0101
0101
0101
0101
D7.2
D8.2
D9.2
D10.2
D11.2
D12.2
D13.2
D14.2
D15.2
D16.2
D17.2
D18.2
D19.2
D20.2
D21.2
D22.2
D23.2
D24.2
D25.2
D26.2
D27.2
D28.2
D29.2
D30.2
D31.2
D0.3
D1.3
D2.3
D3.3
D4.3
D5.3
D6.3
D7.3
D8.3
D9.3
D10.3
D11.3
D12.3
D13.3
D14.3
D15.3
D16.3
D17.3
D18.3
D19.3
D20.3
D21.3
D22.3
D23.3
D24.3
D25.3
D26.3
D27.3
D28.3
D29.3
D30.3
D31.3
D0.4
D1.4
D2.4
D3.4
D4.4
D5.4
D6.4
D7.4
D8.4
D9.4
D10.4
D11.4
D12.4
D13.4
111000
111001
100101
010101
110100
001101
101100
011100
010111
011011
100011
010011
110010
001011
101010
011010
111010
110011
100110
010110
110110
001110
101110
011110
101011
100111
011101
101101
110001
110101
101001
011001
111000
111001
100101
010101
110100
001101
101100
011100
010111
011011
100011
010011
110010
001011
101010
011010
111010
110011
100110
010110
110110
001110
101110
011110
101011
100111
011101
101101
110001
110101
101001
011001
111000
111001
100101
010101
110100
001101
101100
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0011
0011
0011
1100
0011
1100
1100
1100
0011
1100
1100
1100
1100
1100
1100
0011
0011
1100
1100
1100
1100
1100
1100
0011
0011
1100
1100
0011
1100
0011
0011
0011
0010
0010
0010
1101
0010
1101
1101
1101
0010
1101
1101
1101
1101
1101
000111
000110
100101
010101
110100
001101
101100
011100
101000
100100
100011
010011
110010
001011
101010
011010
000101
001100
100110
010110
001001
001110
010001
100001
010100
011000
100010
010010
110001
001010
101001
011001
000111
000110
100101
010101
110100
001101
101100
011100
101000
100100
100011
010011
110010
001011
101010
011010
000101
001100
100110
010110
001001
001110
010001
100001
010100
011000
100010
010010
110001
001010
101001
011001
000111
000110
100101
010101
110100
001101
101100
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
1100
1100
1100
0011
1100
0011
0011
0011
1100
0011
0011
0011
0011
0011
0011
1100
1100
0011
0011
0011
0011
0011
0011
1100
1100
0011
0011
1100
0011
1100
1100
1100
1101
1101
1101
0010
1101
0010
0010
0010
1101
0010
0010
0010
0010
0010
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
001
001
001
001
001
001
001
001
001
001
001
001
001
001
001
001
001
001
001
001
001
001
001
001
001
001
001
001
001
001
001
001
010
010
010
010
010
010
010
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
00000
00001
00010
00011
00100
00101
00110
010
010
010
010
010
010
010
010
010
010
010
010
010
010
010
010
010
010
010
010
010
010
010
010
010
011
011
011
011
011
011
011
011
011
011
011
011
011
011
011
011
011
011
011
011
011
011
011
011
011
011
011
011
011
011
011
011
100
100
100
100
100
100
100
100
100
100
100
100
100
100
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
Notes: 1. “HGF, EDCBA” corresponds to data inputs CTXD7–CTXD0, in that order.
2. “abcdei, fghj” corresponds to BTXD9–BTXD0,␣ in that order; “a” is to be transmitted first, followed by “b,” “c,” . . . “j.”
20
For additional information and latest specifications, see our website: www.triquint.com
TQ9303
Data Byte
Bits
Name
HGF
EDCBA 1
Current
abcdei
RD –
fghj 2
Current
abcdei
RD +
fghj 2
Data Byte
Bits
Name
HGF
EDCBA 1
Current
abcdei
RD –
fghj 2
Current
abcdei
RD +
fghj 2
D14.4
D15.4
D16.4
D17.4
D18.4
D19.4
D20.4
D21.4
D22.4
D23.4
D24.4
D25.4
D26.4
D27.4
D28.4
D29.4
D30.4
D31.4
D0.5
D1.5
D2.5
D3.5
D4.5
D5.5
D6.5
D7.5
D8.5
D9.5
D10.5
D11.5
D12.5
D13.5
D14.5
D15.5
D16.5
D17.5
D18.5
D19.5
D20.5
D21.5
D22.5
D23.5
D24.5
D25.5
D26.5
D27.5
D28.5
D29.5
D30.5
D31.5
D0.6
D1.6
D2.6
D3.6
D4.6
D5.6
D6.6
D7.6
D8.6
D9.6
D10.6
D11.6
D12.6
D13.6
D14.6
D15.6
D16.6
D17.6
011100
010111
011011
100011
010011
110010
001011
101010
011010
111010
110011
100110
010110
110110
001110
101110
011110
101011
100111
011101
101101
110001
110101
101001
011001
111000
111001
100101
010101
110100
001101
101100
011100
010111
011011
100011
010011
110010
001011
101010
011010
111010
110011
100110
010110
110110
001110
101110
011110
101011
100111
011101
101101
110001
110101
101001
011001
111000
111001
100101
010101
110100
001101
101100
011100
010111
011011
100011
1101
0010
0010
1101
1101
1101
1101
1101
1101
0010
0010
1101
1101
0010
1101
0010
0010
0010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
011100
101000
100100
100011
010011
110010
001011
101010
011010
000101
001100
100110
010110
001001
001110
010001
100001
010100
011000
100010
010010
110001
001010
101001
011001
000111
000110
100101
010101
110100
001101
101100
011100
101000
100100
100011
010011
110010
001011
101010
011010
000101
001100
100110
010110
001001
001110
010001
100001
010100
011000
100010
010010
110001
001010
101001
011001
000111
000110
100101
010101
110100
001101
101100
011100
101000
100100
100011
0010
1101
1101
0010
0010
0010
0010
0010
0010
1101
1101
0010
0010
1101
0010
1101
1101
1101
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
D18.6
D19.6
D20.6
D21.6
D22.6
D23.6
D24.6
D25.6
D26.6
D27.6
D28.6
D29.6
D30.6
D31.6
D0.7
D1.7
D2.7
D3.7
D4.7
D5.7
D6.7
D7.7
D8.7
D9.7
D10.7
D11.7
D12.7
D13.7
D14.7
D15.7
D16.7
D17.7
D18.7
D19.7
D20.7
D21.7
D22.7
D23.7
D24.7
D25.7
D26.7
D27.7
D28.7
D29.7
D30.7
D31.7
010011
110010
001011
101010
011010
111010
110011
100110
010110
110110
001110
101110
011110
101011
100111
011101
101101
110001
110101
101001
011001
111000
111001
100101
010101
110100
001101
101100
011100
010111
011011
100011
010011
110010
001011
101010
011010
111010
110011
100110
010110
110110
001110
101110
011110
101011
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0001
0001
0001
1110
0001
1110
1110
1110
0001
1110
1110
1110
1110
1110
1110
0001
0001
0111
0111
1110
0111
1110
1110
0001
0001
1110
1110
0001
1110
0001
0001
0001
010011
110010
001011
101010
011010
000101
001100
100110
010110
001001
001110
010001
100001
010100
011000
100010
010010
110001
001010
101001
011001
000111
000110
100101
010101
110100
001101
101100
011100
101000
100100
100011
010011
110010
001011
101010
011010
000101
001100
100110
010110
001001
001110
010001
100001
010100
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
1110
1110
1110
0001
1110
0001
0001
0001
1110
0001
0001
1000
0001
1000
1000
1110
1110
0001
0001
0001
0001
0001
0001
1110
1110
0001
0001
1110
0001
1110
1110
1110
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
110
110
110
110
110
110
110
110
110
110
110
110
110
110
111
111
111
111
111
111
111
111
111
111
111
111
111
111
111
111
111
111
111
111
111
111
111
111
111
111
111
111
111
111
111
111
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
DATACOM
PRODUCTS
Table A-1. Valid Data Characters (continued)
Table A-2. Valid Special Characters
Special
Code Name
Current
abcdei
RD –
fghj (2)
Current
abcdei
RD +
fghj (2)
K28.0
001111
0100
110000
1011
K28.1
K28.2
K28.3
K28.4
K28.5
K28.6
K28.7
K23.7
K27.7
K29.7
K30.7
001111
001111
001111
001111
001111
001111
001111
111010
110110
101110
011110
1001
0101
0011
0010
1010
0110
1000
1000
1000
1000
1000
110000
110000
110000
110000
110000
110000
110000
000101
001001
010001
100001
0110
1010
1100
1101
0101
1001
0111
0111
0111
0111
0111
Notes: 1. “HGF, EDCBA” corresponds to data inputs CTXD7–CTXD0, in that order.
2. “abcdei, fghj” corresponds to BTXD9–BTXD0,␣ in that order. “a” is to be transmitted first, followed by “b,” “c,” . . . “j.”
For additional information and latest specifications, see our website: www.triquint.com
21
TQ9303
Table B-1. TQ9303 Encoding
Ordered
Set
32-Bit Word Encoder Input
30
29
28
27:24
Sig
SOF
EOF
Type
23:16
15:8
7:0
Beg.
RD
Ordered Set Output
SOFn13
0
0
1
0
0001
_1
_1
_1
Neg
(K28.5–D21.5–D23.1–D23.1)
SOFn2
SOFn3
SOFi1
SOFi2
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0010
0011
0101
0110
_1
_1
_1
_1
_1
_1
_1
_1
_1
_1
_1
_1
Neg
Neg
Neg
Neg
(K28.5–D21.5–D21.1–D21.1)
(K28.5–D21.5–D22.1–D22.1)
(K28.5–D21.5–D23.2–D23.2)
(K28.5–D21.5–D21.2–D21.2)
SOFi3
SOFc1
SOFf
EOFn4,5
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
0111
1101
1000
0000
_1
_1
_1
_1
_1
_1
_1
_1
_1
_1
_1
_1
Neg
Neg
Neg
Neg
(K28.5–D21.5–D22.2–D22.2)
(K28.5–D21.5–D23.0–D23.0)
(K28.5–D21.5–D24.2–D24.2)
(K28.5–D21.4–D21.6–D21.6)
EOFt5
0
0
0
1
0100
_1
_1
_1
EOFdt6
0
0
0
1
1100
_1
_1
_1
Pos
Neg
Pos
Neg
(K28.5–D21.5–D21.6–D21.6)
(K28.5–D21.4–D21.3–D21.3)
(K28.5–D21.5–D21.3–D21.3)
(K28.5–D21.4–D21.4–D21.4)
EOFa
0
0
0
1
1001
_1
_1
_1
EOFni
0
0
0
1
0001
_1
_1
_1
Pos
Neg
Pos
Neg
(K28.5–D21.5–D21.4–D21.4)
(K28.5–D21.4–D21.7–D21.7)
(K28.5–D21.5–D21.7–D21.7)
(K28.5–D10.4–D21.6–D21.6)
EOFdti
0
0
0
1
1101
_1
_1
_1
Idle7
0
1
0
0
0000
_1
_1
_1
Pos
Neg
Pos
Neg
(K28.5–D10.5–D21.6–D21.6)
(K28.5–D10.4–D21.4–D21.4)
(K28.5–D10.5–D21.4–D21.4)
(K28.5–D21.4–D21.5–D21.5)
_1
_1
_1
Neg
Neg
Neg
Neg
(K28.5–D21.4–D10.2–D10.2)
(K28.5–D21.2–D31.5–D5.2)
(K28.5–D21.1–D10.4–D21.2)
(K28.5–D9.2–D31.5–D9.2)
Neg
(K28.5–D21.1–D31.5–D9.2)
(K28.0–DX.YB–DX.YC–DX.YD)
(K28.1–DX.YB–DX.YC–DX.YD)
(K28.2–DX.YB–DX.YC–DX.YD)
R-Rdy7
OLS7
LR7
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0110
1000
1001
1010
_1
_1
_1
_1
_1
_1
_1
_1
_1
LRR7
Undefined
Undefined
Undefined
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1011
0000
0001
0010
_1
(XYB)2
(XYB)2
(XYB)2
_1
(XYC)2
(XYC)2
(XYC)2
_1
(XYD)2
(XYD)2
(XYD)2
Undefined
Undefined
Undefined
Undefined
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0011
0100
0101
0110
(XYB)2
(XYB)2
(XYB)2
(XYB)2
(XYC)2
(XYC)2
(XYC)2
(XYC)2
(XYD)2
(XYD)2
(XYD)2
(XYD)2
(K28.3–DX.YB–DX.YC–DX.YD)
(K28.4–DX.YB–DX.YC–DX.YD)
(K28.5–DX.YB–DX.YC–DX.YD)
(K28.6–DX.YB–DX.YC–DX.YD)
Undefined
Undefined
Undefined
Undefined
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0111
1000
1001
1010
(XYB)2
(XYB)2
(XYB)2
(XYB)2
(XYC)2
(XYC)2
(XYC)2
(XYC)2
(XYD)2
(XYD)2
(XYD)2
(XYD)2
(K28.7–DX.YB–DX.YC–DX.YD)
(K23.7–DX.YB–DX.YC–DX.YD)
(K27.7–DX.YB–DX.YC–DX.YD)
(K29.7–DX.YB–DX.YC–DX.YD)
Undefined
1
0
0
0
1011
(XYB)2
(XYC)2
(XYD)2
(K30.7–DX.YB–DX.YC–DX.YD)
NOS7
Notes:
22
31
Cntl
1. Don’t care (any value).
2. Outputs for the data characters in the ordered set must be
encoded to the correct data values.
3. SOF – Start-of-frame delimiter.
4. EOF – End-of-frame delimiter
5. Encoded as EOFNI if TERR or PERR = 1.
6. Encoded as EOFDTI if TERR or PERR = 1.
7. Proper running disparity is forced before encoding
these ordered sets.
For additional information and latest specifications, see our website: www.triquint.com
TQ9303
Ordered Set
Input
31:24
SOF
32-Bit Decoded Output
23:16
EOF
Type
BRD –(2)
15:8
7:0
BRD +(3)
Cntl
Sig
SOFn1
0
0
1
0
0001
(B516)
(3716)
(3716)
SOFn2
SOFn3
SOFi1
SOFi2
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0010
0011
0101
0110
(B516)
(B516)
(B516)
(B516)
(3516)
(3616)
(5716)
(5516)
(3516)
(3616)
(5716)
(5516)
SOFi3
SOFc1
SOFf
EOFn
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
0111
1101
1000
0000
(9516)
(B516)
(B516)
(B516)
(B516)
(5616)
(1716)
(5816)
(D516)
(5616)
(1716)
(5816)
(D516)
EOFt
EOFdt
EOFa
EOFni
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0100
1100
1001
0001
(9516)
(9516)
(9516)
(8A16)
(B516)
(B516)
(B516)
(AA16)
(7516)
(9516)
(F516)
(D516)
(7516)
(9516)
(F516)
(D516)
EOFdti
Idle
R_Rdy
NOS
0
0
0
0
0
1
1
1
0
0
0
0
1
0
0
0
1101
0000
0110
1000
(8A16)
(AA16)
(9516)
(9516)
(5516)
(9516)
(B516)
(4A16)
(BF16)
(9516)
(B516)
(4A16)
(4516)
OLS
LR
LRR
(K28.0-DX.YB-DX.YC-DX.YD)
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
1001
1010
1011
0000
(3516)
(4916)
(9516)
(XYB)
(8A16)
(BF16)
(BF16)
(XYC)
(5516)
(4916)
(4916)
(XYD)
(K28.1-DX.YB-DX.YC-DX.YD)
(K28.2-DX.YB-DX.YC-DX.YD)
(K28.3-DX.YB-DX.YC-DX.YD)
(K28.4-DX.YB-DX.YC-DX.YD)
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0001
0010
0011
0100
(XYB)
(XYB)
(XYB)
(XYB)
(XYC)
(XYC)
(XYC)
(XYC)
(XYD)
(XYD)
(XYD)
(XYD)
(K28.5-DX.YB-DX.YC-DX.YD)1
(K28.6-DX.YB-DX.YC-DX.YD)
(K28.7-DX.YB-DX.YC-DX.YD)
(K23.7-DX.YB-DX.YC-DX.YD)
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0101
0110
0111
1000
(XYB)
(XYB)
(XYB)
(XYB)
(XYC)
(XYC)
(XYC)
(XYC)
(XYD)
(XYD)
(XYD)
(XYD)
(K27.7-DX.YB-DX.YC-DX.YD)
(K29.7-DX.YB-DX.YC-DX.YD)
(K30.7-DX.YB-DX.YC-DX.YD)
1
1
1
0
0
0
0
0
0
0
0
0
1001
1010
1011
(XYB)
(XYB)
(XYB)
(XYC)
(XYC)
(XYC)
(XYD)
(XYD)
(XYD)
DATACOM
PRODUCTS
Table B-2. TQ9303 Decoding
Notes: 1. Valid for any unrecognized control sequence starting with “K28.5.” Not valid for acquiring Word Sync.
2. BRD – Beginning Running Disparity Negative.
3. BRD + Beginning Running Disparity Positive.
For additional information and latest specifications, see our website: www.triquint.com
23
TQ9303
Mechanical Specifications
Figure 11. TQ9303 PQFP Package Dimensions
(All dimensions are in millimeters)
32.0 ±0.4
28.0 ±0.2
121
160
120
1
PIN 1
32.0
±0.4
28.0
±0.2
40
1.325 TYP.
81
41
80
0.65 TYP.
NON-ACCUM.
0.3 +0.1
+0.2
0.45 -0.1
4.45
MAX
30.4 +0.4
24
For additional information and latest specifications, see our website: www.triquint.com
3.6 +0.2
TQ9303
Ordering Information
TQ9303-QC
Fibre Channel Encoder/Decoder
TQ9501-MC
TQ9502-MC
DATACOM
PRODUCTS
Supporting Products
531/1063 Mbaud Transmitter
531/1063 Mbaud Receiver
Additional Information
For latest specifications, additional product information,
worldwide sales and distribution locations, and information about TriQuint:
Web: www.triquint.com
Email: [email protected]
Tel: (503) 615-9000
Fax: (503) 615-8900
For technical questions and additional information on specific applications:
Email: [email protected]
The information provided herein is believed to be reliable; TriQuint assumes no liability for inaccuracies or
omissions. TriQuint assumes no responsibility for the use of this information, and all such information
shall be entirely at the user's own risk. Prices and specifications are subject to change without notice.
No patent rights or licenses to any of the circuits described herein are implied or granted to any third party.
TriQuint does not authorize or warrant any TriQuint product for use in life-support devices and/or systems.
Copyright © 1997 TriQuint Semiconductor, Inc. All rights reserved.
Revision 1.1.A
November 1997
For additional information and latest specifications, see our website: www.triquint.com
25