TRIQUINT TQ9501

R
I
Q
U
I
N
T
S E M I C O N D U C T O R, I N C .
TQ9501/9502
Data
10
Control
2
Data
32
Parity
TQ9501
Transmitter
Optical Tx
or Copper
Interface
2
2
4
Control
11
TQ9303
ENDEC
HOST
Fiber
Optic
Cable
2
Data
32
Parity
2
4
Control
12
531/1063 Mbaud
Fibre Channel
Transmitter and
Receiver
Data
10
Control
2
TQ9502
Receiver
2
Optical Rx
or Copper
Interface
TriQuint’s Fibre Channel transmitter (TQ9501) and receiver (TQ9502) are
part of the FC531/FC1063 (Fibre Channel 531 and 1063 Megabaud) chip
set. In addition to the transmitter and receiver, TriQuint offers the ENcoder/
DECoder (TQ9303 ENDEC). The TQ9501, TQ9502, TQ9303 and a gigabit
fiber optic module set provide a complete solution for Fibre Channel's FC0
and FC1 layers as well as partial support for the FC2 layer.
Features
The TQ9501 and TQ9502 are designed in TriQuint's proprietary 0.7-micron
GaAs process, enabling the transmitter and receiver to run at higher speeds
and lower power than with conventional processes. The transmitter and
receiver data interface has been selected to be 10 bits in order to conserve
input/output power and to reduce pin count and package size. The transmitter performs the parallel-to-serial conversion and generates the internal
high-speed clock for the serial output. The receiver performs serial-toparallel conversion, recovers the clock and data from the serial input, and
detects the K28.5 character (Fibre Channel standard “SYNC” transmission
character).
• Low power dissipation
(2.25 W, typical)
The TQ9303 ENDEC implements 8b/10b encoding and decoding, ordered
set encoding and decoding, parity checking and generation, 32-bit CRC
checking and generation, and word synchronization as defined in the
Fibre Channel Physical and Signaling Interface Standard (FC-PH).
DATACOM
PRODUCTS
T
• Compliant with ANSI X3T11
Fibre Channel Standard
• Operates at 531.125 Mbaud
and 1.0625 Gigabaud
(1.25 Gigabaud max)
• Low jitter
• No external PLL components
• 10-bit TTL-compatible data bus
• Synchronous Data Bus Interface
• Direct interface to TQ9303 ENDEC
• Single +5 V supply
• 48-pin MQuad package
Fibre Channel provides a high-speed physical layer for Intelligent
Peripheral Interface (IPI) and Small Computer System Interface (SCSI)
upper-layer command sets, High-Performance Parallel Interface (HIPPI)
data link layer, and other user-defined command sets. Fibre Channel
replaces the SCSI, IPI and HIPPI physical interfaces with a higherspeed interface capable of driving longer distances.
For additional information and latest specifications, see our website: www.triquint.com
1
TQ9501/TQ9502
Fibre Channel is optimized for predictable transfers of
large blocks of data, such as those used in file
transfers between processors (super computer,
mainframe, super-mini, etc.), storage systems (disk
and tape), and output-only devices such as laser
printers and raster scan graphics terminals.
TriQuint offers two chip sets for Fibre Channel: the
TQ9501 and TQ9502 chip set for 531.125 Mbaud and
1.0625 Gbaud, and the GA9101 and GA9102 chip set
for the 265.625 Mbaud rate.
The Fibre Channel protocol is implemented in
hardware, making it simple, efficient and robust. The
lower-level physical interface is decoupled from the
higher-level protocol allowing the Fibre Channel to be
configured with various topologies, including point-topoint, multi-drop bus, ring, and cross point switch.
The TQ9501 serializes a 10-bit TTL input into a
differential PECL output. The TQ9501 is composed of
an input register, a parallel-to-serial converter, a PLL
clock generator, a differential output buffer and a PECLto-TTL translator, as illustrated in Figure 1.
Fibre Channel supports distances up to 10 Km at baud
rates of 132.8125 Mbaud to 1.0625 Gbaud. Copper
media such as Coax and STP (Shielded Twisted Pair)
are used for shorter distances while fiber optic cables
are used for longer distances.
Applications for the TQ9501 and TQ9502 include serial
SCSI, IPI, HIPPI, point-to-point serial communication,
ATM and other networking applications.
Functional Description – TQ9501 Transmitter
The self-contained PLL (Phase-Locked Loop) clock
generator requires no external components. It
generates an internal high-speed bit clock for the serial
output, an internal byte clock for the parallel-to-serial
converter and BYTECLK, based on REFCLK (REFerence
CLocK). BYTECLK is used by the TQ9303 ENDEC to
generate TXCLK.
TXD0..9 are latched into the input register on the rising
edge of TXCLK. The parallel-to-serial converter
serializes the data into a differential PECL buffer. TXD9
is sent first and TXD0 is sent last.
Figure 1. TQ9501 Transmitter
LOOPEN
RATESEL
PLL Clock
Generator
REFCLK
(25–31.25 MHz
TLX
Parallelto-Serial
Converter
TX
BYTECLK
(50–62.5 MHz
or 100–125 MH
Byte
Clock
10
Register
Bit
Clock
TLY
TXD0..9
TXCLK
TY
SIG
SIGN
2
10
2
PECL-to-TTL
Converter
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SIGDET
TQ9501/TQ9502
Figure 2. TQ9502 – Receiver
RX, RY
RLX, RLY
2
Mux
Data
Clock/Data
Recovery
(500–625 MBaud Clock
or 1.0–1.25 GBaud)
2
2
Serial-toParallel
Converter
10
Register
SYNCEN
10
RXD0..9
SYNC
LOOPEN
X 40
RATESEL
RX Clock
Generate
REFCLK
(25–31.25 MHz)
RXCLK
(50–62.5 MHz
or 100–125 MH
DATACOM
PRODUCTS
CLKPOL
The LOOPEN (LOOP ENable) pin selects between the
two differential output pairs, TLX and TLY, or TX and
TY. LOOPEN = 1 selects the differential output TLX and
TLY, setting TX = 0 and TY = 1. Conversely, LOOPEN =
0 selects TX and TY, setting TLX = 0 and TLY = 1. This
relationship is shown in Table 1.
The PECL-to-TTL translator block is a differential PECLto-TTL translator. It is normally used for translating
PECL signals generated by optical receivers to TTL
signals to drive control circuitry.
Table 1. LOOPEN Configuration
LOOPEN
Rx Input
Tx Output
0
RX, RY
TX,TY
1
RLX, RLY
TLX, TLY
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3
TQ9501/TQ9502
Functional Description – TQ9502 Receiver
The TQ9502 consists of a clock and data recovery
circuit, a multiplexer, and a serial-to-parallel converter
block, as shown in Figure 3. The multiplexer selects
between the RX and RY inputs or the RLX and RLY
inputs. Outputs RTX, RTY, RLTX and RLTY, not shown
on Figure 3, are provided for Fly-By™ termination,
which allows termination resistors to be placed away
from the chip. The multiplexer output is selected by the
LOOPEN pin as shown in Table 1. The selected data
goes to the CDR (Clock/Data Recovery) block.
The clock and data recovery block has two modes:
clock recovery and frequency acquisition. In the clock
input, it automatically switches to the frequency
acquisition mode which causes the CDR to lock onto
the REFCLK signal. This prevents the PLL from drifting
away from the serial data rate and ensures that the
CDR will properly lock onto the input serial data when it
is reapplied.
The receiver synchronizes 1 ms after applying power,
REFCLK and data. The receiver synchronizes 200 µs
after applying valid data if power and REFCLK has
already been applied. The output of this block is latched
into the output register. When SYNCEN is high
(SYNCronization ENable), the serial-to-parallel
converter monitors the serial data for the K28.5
character. When it sees a K28.5, it realigns the 10-bit
register to the K28.5 character and drives SYNC high.
The clock generate block also detects SYNC going high,
and delays the phase of the output RXCLK to coincide
with the new alignment. Some bits may be lost during
4
the realignment. When SYNCEN is low, SYNC is driven
low and the serial-to-parallel converter ignores the
K28.5 character.
The output register takes in the 10-bit-wide output
from the Serial-to-Parallel Converter and drives the
RXD0..9 outputs. RXD0..9 are strobed on the rising
edge of RXCLK. CLKPOL = 1 results in a longer setup
time and shorter hold time than CLKPOL = 0. The first
serial bit is placed in RXD9 and the tenth bit is placed
in RXD0.
Fibre Channel Interface
Figure 3 illustrates a typical Fibre Channel physical
layer block diagram using the TQ9501, TQ9502 and
TQ9303 chip set. The interface between the host and
ENDEC operates at 26.5625 MHz with a data width of
32-bits for the transmit path and a separate 32-bits for
the receive path. The ENDEC performs the 8b/10b
encoding and decoding; ordered set encoding and
decoding; parity checking and generation; 32-bit CRC
checking and generation; and word synchronization.
The interface between the TQ9303 and the TQ9501/
TQ9502 operates at 531.25 or 106.250 MHz with an
encoded data width of 10-bits. The serial interface
operates from 531.125 Mbaud or 1.0625 Gbaud
respectively, which is connected to an optical, coaxial
or twisted pair interface.
For additional information on the ENDEC, please refer
to the TQ9303 data sheet.
For additional information and latest specifications, see our website: www.triquint.com
TQ9501/TQ9502
Figure 3. System Block Diagram – Fibre Channel
TQ9501 TX
Host
TX, TY
TLX, TLY
TQ9303 ENDEC
RESETN
CRXD0..31
CRXP0..3
BRXD0..9
CRXS0..5
BRXCLK
RAWRX
RXPMODE BRXSYNC
WRDSYNCN
RXCKPH0,1
CRXCLK
TQ9502 RX
RXD0..9
RXCLK
SYNC
RLX, RLY
Out
Optical,
Coaxial, or
Twisted Pair
Interface
In
2
2
RTX
RTY
SYNCEN
CLKPOL
Note that the fast edge rates of the TQ9303 TX bus
outputs can affect the stability of the TQ9501 PLL.
These edge rates can be effectively “slowed” by adding
some series resistance of from 90 to 250 ohms to the
TX data bus lines (TXD0..9) as shown in Figure 4.
Resistance should also be added to TXCLK to maintain
the correct timing relationship with the data lines. The
resistors should be placed near the TQ9303.
RX, RY
Optical,
Coaxial, or
Twisted Pair
Interface
Termination
Network
RLTX
RLTY
Figure 4. Adding resistance and capacitance to
the TX data bus.
TQ9303
...
RATESEL
REFCLK
LOOPEN
BTXD0..9
TXD0..9
CTXD0..31
TXCLK
CTXC0,1
BTXCKOUT
CTXP0..3
BYTECLK
BTXCKIN
CTXRAWA,B
CTXRAW
CTXPENN
SIG, SIGN
CTXPMODE
CTXPERR
RATESEL
CTXCERR
CTXCLK
REFCLK
CTXWREF
LOOPEN
DATACOM
PRODUCTS
SIGDET
TQ9301
In cases where the line capacitance of the bus traces is
less than 3 pF, it may also be necessary to add from
1– 2 pf of capacitance to each trace near the TQ9501.
The purpose is to slow the edge rates enough to
prevent potential undershoot from disturbing the power
supplies in the PLL circuitry of the TQ9501.
For additional information and latest specifications, see our website: www.triquint.com
5
TQ9501/TQ9502
Table 2. Transmitter Pin Descriptions
Symbol
Type
Description
TX, TY
O
Differential Transmitter Outputs connect to an optical transmitter, a coaxial interface or shielded twisted pair
interface. LOOPEN low selects TY and TX outputs. LOOPEN high drives TX low and TY high.
TLX, TLY
O
Loopback Differential Transmitter Outputs connect to the Receiver RLX and RLY inputs. LOOPEN high selects
TLY and TLX outputs. LOOPEN low drives TLX low and TLY high.
LOOPEN
I
Loopback Enable high selects the TLX and TLY as outputs. LOOPEN low selects the TX and TY as outputs.
REFCLK
I
The PLL multiplies the Reference Clock and generates the high speed clock for transmitting serial data.
REFCLK shall be equal to 1/40 of the baud rate. REFCLK shall have a frequency tolerance of 100 ppm to
guarantee clock and data recovery on the receiver. The REFCLK operating range is 25 MHz to 31.25 MHz.
BYTECLK
O
The ENDEC uses Byte Clock to synchronize to the Transmitter. The ENDEC generates TXCLK from BYTECLK
simplifying the synchronization between the Transmitter and ENDEC, as shown on Figure 7.
TXD0..9
I
The Transmitter latches the 10 Encoded Data Bits at the rising edge of TXCLK. The Transmitter serially
sends TXD9 first and TXD0 last.
TXCLK
I
The Transmitter Data Clock strobes TXD0..9 into the Transmitter. The ENDEC generates TXCLK from BYTECLK
simplifying the synchronization between the Transmitter and ENDEC.
SIG, SIGN
I
The Differential Signal Present are inputs to a PECL to TTL translator. The translator is typically used to
convert differential signals from a differential optical receiver output to TTL. The TTL equivalent of SIG and
SIGN is SIGDET.
SIGDET
O
Signal Detect is the output of the PECL to TTL translator. The translator is typically used to convert differential
signals from a differential optical receiver output to TTL. SIGDET is useful when implementing an OFC - Open
Fibre Control protocol where the link activity or optical receiver outputs are monitored continuously.
RATESEL
I
Rate Select is used to select between 531 Mbaud (RATESEL=VDD) and 1063 Mbaud (RATESEL=GND)
operation.
Figure 5. Fly-By ™ Termination Schematic
5V
82 Ω
TQ9502 RX
Z0 = 50 Ω
130 Ω
Figure 6. Transmitter Synchronization Ciruit Block Diagram
RLTY
RLY
TQ9303 ENDEC
5V
82 Ω
TQ9501 TX
RLX
Z0 = 50 Ω
RLTX
130 Ω
BTXD0..9
TXD0..9
5V
82 Ω
Z0 = 50 Ω
130 Ω
BTXCKOUT
RTY
5V
82 Ω
TXCLK
RY
RX
Z0 = 50 Ω
BTXCKIN
RTX
130 Ω
6
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BYTECLK
TQ9501/TQ9502
Table 3. Receiver Pin Descriptions
Symbol
Type
Description
I
The Receiver Differential Inputs connects to an optical, coaxial or shielded twisted pair interface.
LOOPEN low selects the RX and RY inputs. LOOPEN high selects the RLX and RLY inputs.
RTX, RTY
I
The Receiver Differential Termination are used in Fly-By™ termination. RX is internally connected to
RTX and RY is internally connected to RTY. A termination circuit connects to RTX and RTY instead of
RX and RY. With Fly-By™ termination, the termination circuit can be located away from the Receiver
instead of requiring termination directly at RX and RY. Both RTX and RTY must be terminated with a
50Ω chip resistor in series with 3V reference or Thevenin equivalent as shown in Figure 6.
RLX, RLY
I
The Looped Receiver Differential Inputs connect to the Transmitters TLX and TLY outputs providing
a loop back path. LOOPEN high selects the RLX and RLY inputs. LOOPEN low selects the RX and RY
inputs.
RLTX, RLTY
I
The Receiver Differential Termination are used in Fly-By™ termination. RLX is internally connected
to RLTX and RLY is internally connected to RLTY. A termination circuit connects to RLTX and RLTY
instead of RLX and RLY. With Fly-BY™ termination, the termination circuit can be located away from
the Receiver instead of requiring termination directly at the RLX and RLY. Both RLTX and RLTY must
be terminated with a 50Ω chip resistor in series with 3V reference or Thevenin equivalent as shown
on Figure 6.
LOOPEN
I
Loopback Enable high selects the RLX and RLY inputs. LOOPEN low selects the RX and RY inputs.
REFCLK
I
The Reference Clock provides the clock needed by the clock recovery circuit. The REFCLK frequency
shall bE chosen to equal 1/40 of the baud rate. REFCLK shall have a frequency tolerance of 100 ppm
to guarantee clock and data recovery on the receiver. The receiver automatically locks onto the
REFCLK during power-up and/or when no input signals are applied. This prevents the PLL from
drifting away from the input data rate. The PLL automatically locks onto the input data stream when it
is applied. The frequency range of REFCLK is 25 MHz to 31.25 MHz.
SYNCEN
I
When Sync Enable is high, the receiver searches for a K28.5 character from the input data stream and
byte aligns the parallel register to this character as defined in the Fibre Channel standard. SYNCEN
low disables byte alignment to a K28.5 character and drives SYNC low. The K28.5 character has a
pattern of RXD9..0 = 001111 1010 or 110000 0101. Whenever the receiver detects the K28.5 pattern
it byte aligns to this character and drives SYNC high for that byte cycle. SYNC is high only in byte
cycle where a K28.5 character is present.
RXDO..9
O
These are 10 Encoded Data Bits where the first bit received from the serial data stream is RXD9 and
the last bit received is RXD0. The receiver generates RXCLK to strobe RXD0..9.
SYNC
O
If SYNCEN is high, Synchronization to K28.5 goes high for the byte clock cycle in which a K28.5
character is present on the RXD0..9 output. If SYNCEN is low then SYNC is always low.
RXCLK
O
Receiver Data Clock is the strobe for RXD0..9 and SYNC. The phase of RXCLK with respect to
RXD0..9 and SYNC changes depending on CLKPOL. CLKPOL high provides a longer setup time and a
shorter hold time while CLKPOL low provides a shorter setup time and a longer hold time. The
frequency range of RXCLK is 50 MHz to 62.5 MHz in FC531 mode and 100 MHz to 125 MHz in FC1063
mode.
CLKPOL
O
Clock Phase or Polarity controls the phase of RXCLK with respect to RXD0..9 and SYNC. CLKPOL
high provides a longer setup time and a shorter hold time while CLKPOL low provides a shorter setup
time and a longer hold time.
RATESEL
I
Rate Select is used to select between 531 Mbaud (RATESEL=VDD) and 1063 Mbaud
(RATESEL=GND) operation.
For additional information and latest specifications, see our website: www.triquint.com
DATACOM
PRODUCTS
RX, RY
7
TQ9501/TQ9502
Figure 7. Example Top Layer Layout of Power Pins
(Not to scale)
Layout Guidelines
Multiple ground and power pins on the TQ9501/02
reduce ground bounce. Good layout techniques,
however, are necessary to guarantee proper operation
and to meet the specifications across the full operating
range. TriQuint recommends bypassing each of the VDD
supply pins to the nearest ground pin, as close to the
chip as possible.
VDD
C
Pin 1
C
VDD
Ground
Plane
VDD
Figure 7 shows the recommended power layout for the
TQ9501/02. The bypass capacitors should be located
on the same side of the board as the TQ9501/02. The
VDD traces connect to an inner-layer VDD plane. All of
the ground pins (GND) are connected to a small ground
plane on the surface beneath the chip. Multiple
through-holes connect this small surface plane to an
inner-layer ground plane. The capacitors are 0.1 µF.
TriQuint's test board uses X7R temperature-stable
capacitors in 1206 SMD cases.
Table 4. Absolute Maximum Ratings
C
Rx Only
VDD
C
VDD
VDD
VDD
Pin 23
Note:
Series resistors and small capacitors may be needed for the
TX data bus and clock lines. See the previous “Fibre Channel
Interface” section in this datasheet for details.
Table 5. Operating Conditions
Parameter
Range
Parameter
Storage temperature
–65 °C to +150 °C
Supply voltage
Case temperature
–55 °C to +125 °C
Ambient temperature
Supply voltage to ground
–0.5 V to +7.0 V
DC input voltage
–0.5 V to (VDD +0.5 V)
DC input current
30 mA to +5 mA
Package Thermal Resistance
θjA = 40 °C/W; θcA = 8 °C/W
Die Junction Temperature
Tj = 150 °C
Note:
C
C
Note:
Range
5V±5
0 to 70 °C
Proper functionality is guaranteed under these
operating conditions.
Stresses above those listed in Absolute Maximum Rating
may cause permanent damage to the device. This is a
stress-only rating and operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied.
Table 6. Test Loads
Symbol
CIN
COUT
8
Description
Test Conditions
Min.
Typ.
Input capacitance
VIN = 2.0 V at f = 1 MHz
6
pF
Output capacitance
VOUT = 2.0 V at f = 1 MHz
9
pF
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Max.
Unit
TQ9501/TQ9502
Table 7. DC Characteristics—TQ9501 Transmitter TTL Signals
(TXDO..9, TXCLK, BYTECLK, LOOPEN, SIGDET, REFCLK, RATESEL)
(Over operating range unless otherwise specified)
Description
Test Conditions
VOH
Output HIGH voltage
VDD = Min
VIN2 = VIH or VIL
IOH = –1.6 mA
IOH = –3.2 mA3
VOL
Output LOW voltage
VDD = Min
VIN2 = VIH or VIL
IOL = 4 mA
IOL = 8 mA3
ISC4
Min.
Limits 1
Typ.
2.4
3.2
Max.
Unit
V
0.2
V
Output short-circuit current
VDD = Max
VOUT = 0.5 V
–120
mA
IIL
Input LOW current
VDD = Max
VIN = 0.4 V
– 400
µA
IIH
Input HIGH current
VDD = Max
VIN = 2.7 V
25
µA
II
Input HIGH current
VDD = Max
VIN = 5.5 V
1
mA
VIH5
Input HIGH level
Guaranteed input logical HIGH
voltage for all inputs, VDD = Max
VIL5
Input LOW level
Guaranteed input logical LOW
voltage for all inputs
VI
Input clamp voltage
IDD
Power supply current
VDD = Min
–15
0.5
2.0
V
0.8
IIN = –18 mA
VDD = Max, static
175
V
–1.2
V
220
mA
Max.
Unit
DATACOM
PRODUCTS
Symbol
Table 8. DC Characteristics—TQ9501 Transmitter PECL Signals (TX, TY, TLX, TLY, SIG, SIGN)
Symbol
Description
Test Conditions
Min.
Limits 1
Typ.
VOH
Output HIGH voltage
VDD = Min PECL load
VDD – 1.200
VDD – 0.50
V
VOL
Output LOW voltage
VDD = Min PECL load
VDD – 2.00
VDD – 1.60
V
V
VCMO
Output common mode voltage
VDD – 1.60
VDD –1.10
DVOUT
Output differential voltage
0.60
1.2
V
200
µA
250
µA
VDD – 0.5
V
IIL
IIH
Input LOW current
VDD = Max
VIN =2.4 V
VIN = VDD – 0.5 V
Input HIGH current
VDD = Max
VIHS
Highest input HIGH voltage
VDD = Min
VILS
Lowest input LOW voltage
VDD = Max
2.4
V
VDIF
Differential input voltage
VDD = Min
0.4
1.2
V
VICM
Input common mode voltage
VDD = Min
2.8
VDD – 0.7
V
Notes: 1. Typical limits are: VDD = 5.0 V and TA = 25 °C.
2. The TTL inputs could be HIGH or LOW.
3. The IOL and IOH specifications are valid only for the BYTECLK.
4. These are absolute values with respect to device ground.
5. No more than one output should be tested at a time. Duration of the short circuit should not exceed one second.
For additional information and latest specifications, see our website: www.triquint.com
9
TQ9501/TQ9502
Table 9. DC Characteristics—TQ9502 Receiver TTL Signals
(RXD0..9, RXCLK, SYNCEN, REFCLK, LOOPEN, SYNC, CLKPOL, RATESEL)
(Over operating range unless otherwise specified)
Symbol
Description
Test Conditions
Min.
Limits 1
Typ.
VOH
Output HIGH voltage
VDD = Min
IOH␣ = –1.6 mA
VIN2 = VIH or VIL ␣ ␣ ␣ ␣ = –3.2 mA3
2.4
3.2
VOL
Output LOW voltage
VIN2 = VIH or VIL
VDD = Min IOL = 4 mA
␣ ␣ ␣ ␣ ␣ ␣ = 8 mA3
0.2
0.5
ISC5
Max.
Unit
V
V
Output short–circuit current
VDD = Max
VOUT = 0.5 V
–120
mA
IIL
Input LOW current
VDD = Max
VIN = 0.40 V
–15
–400
µA
IIH
Input HIGH current
VDD = Max
VIN = 2.7 V
25
µA
II
Input HIGH current
VDD = Max
VIN = 5.5 V
1
mA
VIH4
Input HIGH level
voltage for all inputs
Guaranteed input logical HIGH
VIL4
Input LOW level
voltage for all inputs
Guaranteed input logical LOW
VI
Input clamp voltage
VDD = Min
IDD
Power supply current
2.0
V
0.8
IIN = –18 mA
VDD = Max, static
280
V
–1.2
V
350
mA
Table 10. DC Characteristics—TQ9502 Receiver PECL Signals (RX, RY, RTX, RTY, RLX, RLY, RLTX, RLTY)
Symbol
Description
Test Conditions
IIL
Input LOW current
VDD = Max
VIN = 2.4 V
IIH
Input HIGH current
VDD = Max
VIN = VDD –0.5 V
VIHS
Highest input HIGH voltage
VDD = Max
VILS
Lowest input LOW voltage
VDD = Min
Min.
Limits 1
Typ.
Max.
Unit
200
µA
250
µA
0.5
VDD – 0.50
2.4
V
V
VDIF
Differential input voltage
VDD = Min
0.4
1.2
V
VICM
Input common mode voltage
VDD = Min
2.8
VDD – 0.7
V
Notes:
10
1. Typical limits are: VDD = 5.0 V and TA = 25 °C.
2. The TTL inputs could be HIGH or LOW.
3. The IOL and IOH specifications are valid only for the RXCLK.
4. These are absolute values with respect to device ground.
5. No more than one output should be tested at a time. Duration of the short circuit should not exceed one second.
For additional information and latest specifications, see our website: www.triquint.com
TQ9501/TQ9502
Table 12. AC Specifications—TQ9501 Transmitter
Parameters with dual values refer to 531Mbaud/1063Mbaud operation respectively.
Description
Min.
Typ.
Max.
Units
T1
REFCLK pulse width HIGH
10.0
ns
T2
REFCLK pulse width LOW
10.0
ns
T31
REFCLK period (T)
32.0
T4
TXD 9..0 setup time
2.0
ns
T5
TXD 9..0 hold time
2.0
ns
T6
BYTECLK, TXCLK pulse width HIGH
6.0/3.0
ns
T7
BYTECLK, TXCLK pulse width LOW
6.0/3.0
T8
BYTECLK, TXCLK period (T)
16.0/8.0
20.0/10.0
ns
T9
TX, TY, TLX, TLY rise time
100
400/300
ps
T10
TX, TY, TLX, TLY fall time
100
400/300
ps
T11
TX ~ TY or TLX ~ TLY skew
100/60
ps
T123
TX , TY or TLX , TLY output jitter – deterministic jitter (DJ)
– random jitter (RJ)
100/75
200/150
ps
ps
40.0
ns
ns
DATACOM
PRODUCTS
Parameter
Notes: 1. REFCLK Tolerance = (20/baud rate) ±0.01%, for baud rate of 500Mbaud to 625Mbaud and
(40/baud rate) ± 0.01%, for baud rate of 1 Gbaud to 1.25 Gbaud.
2. baud time = 1/baud rate
3. The jitter numbers are for a BER of 10–12.
Figure 8. Bus Timing – TQ9501 Transmitter
REFCLK
T1
T2
T3
TXD0..9
T5
T4
TXCLK
BYTECLK
T7
T6
T8
Figure 9.Serial Output Timing – TQ9501
T12
T10
80%
50%
20%
TX, TLX
T11
T12
T9
50%
TY, TLY
T12
T12
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11
TQ9501/TQ9502
Table 12. AC Specifications—TQ9502 Receiver
Parameters with dual values refer to 531Mbaud/1063Mbaud operation respectively.
Parameter
Notes:
Description
Min.
Typ.
Max.
Units
T21
REFCLK pulse width LOW
10.0
T22
REFCLK pulse width HIGH
10.0
T231
REFCLK period
32.0
T24
Setup Time RXD 0..9 & SYNC
CLKPOL=0
CLKPOL=1
4.0/2.0
12.0/6.0
ns
ns
T25
Hold Time RXD 0..9 & SYNC
CLKPOL=0
CLKPOL=1
8.0/4.0
0
ns
ns
T261
RXCLK period
16.0/8.0
T271
RXCLK pulse width HIGH
6.0/4.0
T281
RXCLK pulse width LOW
6.0/4.0
T29
RX, RY, RLX, RLY rise time
0.4 baud time
ns
T30
RX, RY, RLX, RLY fall time
0.4 baud time
ns
T31
RX ~ RY, RLX ~ RLY skew
0.3 baud time
ns
T32
RX, RY, RLX, RLY peak-to-peak input jitter
0.7 baud time
ns
ns
ns
40.0
ns
20.0/10.0
ns
ns
ns
1. REFCLK Tolerance = (20/baud rate) ±0.01%, for baud rate of 500Mbaud to 625Mbaud and (40/baud rate) ± 0.01%,
for baud rate of 1 Gbaud to 1.25 Gbaud.
2. baud time = 1/baud Rate
3. The jitter numbers are for a BER of 10–12.
Table 13. Synchronization Times
Description
Min.
Typ.
Power Up or application of REFCLK to receiver synchronization
Units
1
ms
Application of valid data to receiver synchronization
200
µs
Receiver resynchronization after phase shift on data
2500
bit time
Figure 10. Bus Timing – TQ9502 Receiver
T22
T21
REFCLK
T23
T24
RXD0..9
SYNC
T26
T25
RXCLK
T27
12
Max.
T28
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TQ9501/TQ9502
Figure 11. Serial Input Timing – TQ9502
80%
50%
20%
RX, RTX, RLX, RLTX
T31
T30
T29
50%
RY, RTY, RLY, RLTY
T32
T32
DATACOM
PRODUCTS
Figure 12a. TTL Test Load,RXCLK
VDD
1000 Ω
Figure 12b. TTL Test Load, All Other TLL Outputs
680 Ω
VDD
2000 Ω
1370 Ω
Figure 12c. PECL Test Load
VDD
82 Ω
130 Ω
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13
TQ9501/TQ9502
9
TXD0
5
4
3
2
1 44 43 42 41 40
39
GND
TXD9
TXD8
6
NC
TXD7
TXD6
TXD1
TXD5
8
NC
TXD2
TXD4
7
TXD3
GND
VDD
Figure 13. Pinout for Transmitter
10
Tx
VDD
38
SIGDET
37
BYTECLK
36
RATESEL
35
VDD
34
TXCLK
33
GND
NC
11
NC
12
NC
13
SIG
14
32
REFCLK
NC
15
31
VDD
SIGN
16
30
LOOPEN
TQ9501
VDD
GND
NC
TLY
TLX
NC
GND
NC
TY
TX
GND
NC
29
17
18 19 20 21 22 23 24 25 26 27 28
VDD
Table 14. Pin Definitions – TQ9501 Transmitter
Symbol
I/O
# Pins
Logic Type
Active
Description
TX, TY
20, 21
Output
2
PECL
NRZ
Differential serial data output
TLX, TLY
25, 26
Output
2
PECL
NRZ
Loopback differential serial data output
SIG, SIGN
14, 16
Input
2
PECL
HIGH
Differential optical signal present
34
Input
1
TTL
HIGH
Transmit clock
10, 9, 8, 5, 4,
2, 1, 44, 42, 41
Input
10
TTL
HIGH
Transmit data input
Enable loopback
TXCLK
TXD 0..9
LOOPEN
30
Input
1
TTL
HIGH
SIGDET
38
Output
1
TTL
HIGH
Signal detect
REFCLK
32
Input
1
TTL
HIGH
Oscillator clock (25 to 31.25 MHz)
BYTECLK
37
Output
1
TTL
HIGH
VDD
6, 17, 29, 31, 35, 39
—
6
—
—
+5 Volt Supply
GND
7,18, 23,
28, 33, 40
—
6
—
—
Ground
3,11, 12, 13, 15,
19, 22, 24, 27, 43
—
10
—
—
No Connect
36
Input
1
—
—
VDD (1) for 531Mbaud operation Ground
(0) for 1063Mbaud operation
NC
RATESEL
14
Pin #
Byte clock
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TQ9501/TQ9502
9
RATESEL
10
4
3
2
1 44 43 42 41 40
39
GND
RXD7
RXD6
5
VDD
6
Rx
11
GND
RXD5
RXD4
RXCLK
RXD3
8
GND
RXDO
RXD2
7
RXD1
GND
VDD
Figure 14. Pinout for Receiver
VDD
38
RXD8
37
RXD9
36
SYNC
35
VDD
34
CLKPOL
33
GND
SYNCEN
12
VDD
13
REFCLK
14
32
NC
GND
15
31
VDD
LOOPEN
16
30
NC
VDD
GND
RTX
RX
RY
RTY
GND
RLTX
RLX
RLY
GND
RLTY
29
17
18 19 20 21 22 23 24 25 26 27 28
VDD
DATACOM
PRODUCTS
TQ9502
Table 15. Pin Definitions - TQ9502 Receiver
Symbol
Pin #
I/O
# Pins
Logic Type
Active
RX, RY
26, 25
I
2
PECL
NRZ
RLX, RLY
21, 20
I
2
PECL
NRZ
Differential serial data input, loopback
RTX, RTY
27, 24
I
2
PECL
NRZ
For fly-by termination
RLTX, RLTY
Description
Differential serial data input
22, 19
I
2
PECL
NRZ
For fly-by termination
8, 5, 4, 2, 1,
44, 42, 41, 38, 37
O
10
TTL
HIGH
Receive output data
RXCLK
9
O
1
TTL
HIGH
Receive clock
REFCLK
14
I
1
TTL
HIGH
Oscillator clock (25 MHz to 31.25 MHz)
SYNC
36
O
1
TTL
HIGH
Receive byte sync
SYNCEN
12
I
1
TTL
HIGH
Sync Enable or Align to K28.5
RXD 0..9
LOOPEN
16
I
1
TTL
HIGH
Enable loopback
CLKPOL
34
I
1
TTL
LOW
RXCLK Clock Phase
VDD
6, 13, 17, 29,
31, 35, 39, 43
—
8
—
—
+5 V supply
GND
3, 7, 11, 15, 18,
23, 28, 33, 40
—
9
—
—
Ground
30, 32
—
2
—
—
No connect
10
I
1
—
—
VDD(1) for 531Mbaud operation
Ground(0) for 1063 Mbaud operation
NC
RATESEL
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15
TQ9501/TQ9502
Figure 15. 44-Pin MQuad J-leaded Package
.172 ± .0125
.104 ± .01
.030 ± .01
.690 ± .005
.645
.045
X 45°
PIN 1
.018 ± .004
12
34
.050 TYP
.645
.690
± .005
0.125
VENT PLUG
.028
23
.015
X 45°
.050
BSC
.132
Ordering Information
TQ9501-MC
TQ9502-MC
FC531/1063 Transmitter
FC531/1063 Receiver
Additional Information
For latest specifications, additional product information,
worldwide sales and distribution locations, and information about TriQuint:
Web: www.triquint.com
Email: [email protected]
Tel: (503) 615-9000
Fax: (503) 615-8900
For technical questions and additional information on specific applications:
Email: [email protected]
The information provided herein is believed to be reliable; TriQuint assumes no liability for inaccuracies or
omissions. TriQuint assumes no responsibility for the use of this information, and all such information
shall be entirely at the user's own risk. Prices and specifications are subject to change without notice.
No patent rights or licenses to any of the circuits described herein are implied or granted to any third party.
TriQuint does not authorize or warrant any TriQuint product for use in life-support devices and/or systems.
Copyright © 1997 TriQuint Semiconductor, Inc. All rights reserved.
Revision 1.1.A
November 1997
16
For additional information and latest specifications, see our website: www.triquint.com
.610
± .015