VITESSE VSC6048

VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
High-Speed Octal
Programmable Timing Generator
VSC6048
Features
• 8 Fully Integrated Timing Generators for ATE
Applications
• 10/5ns Delay Range, 10ps Resolution
• Fully Digital Interface. No Off-Chip DACs or
Trim Components Required
• ± 4 LSB Differential Non-Linearity
• 100MHz/200MHz Dynamic Reprogram Frequency
for Incrementing and Decrementing
• Internal or External High-Speed Clock Option
• Low Power: 8 Watts, max
• Low Cost 160-Pin PQFP Packaging
VSC6048 Block Diagram
6
CAL_DAT
Register
6
SPAN
CAL
DAC
DAC_WR
IN0A
Input
Interleve
IN0B
400MHz
Clock
800MHz
Clock
Variable
Shift
Register
3
Register
TEST[0:9]
Vernier
Delay
Element
Out 0
7
Register
10
7
Channel 0
Channel 1
Channel 2
Channel 7
DIN
Calibration
Register
ADR[0:2]
6
CAL_DAT
DCLK
SHIFT
RCK
RCKN
BYP
PLL
Clock Multiplier
Unit
x8, x16
400MHz Clock
800MHz Clock
FSEL
PLLRST
G52335-0, Rev. 4.0
8/28/00
 VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 1
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
High-Speed Octal
Programmable Timing Generator
VSC6048
Functional Description
Reference Clock Selection
Clock multiplication of x8 or x16 may be selected via the FSEL pin, requiring a reference clock of 100
±2.5MHz or 50 ±1.25MHz, respectively. For system applications with 800MHz on board clock, the CMU can
be bypassed by asserting BYP signal and RCK will accept an external 800MHz clock.
In Bypass mode (BYP = 1, RCK = 800MHz) the skew from INX to RCK at the pin is 550ps +/-250ps.
Table 1: Reference Clock Selection
BYP
FSEL
RCK
0
0
100MHz
0
1
50MHz
1
X
800MHz
X = don’t care.
Mode of Operations
There are 6 basic modes of operation. These modes are based on two inputs per channel (INA and INB) that
can be interleaved and refire rate. The maximum refire rate for full 10ns span is 100MHz, where the maximum
refire rate for 5ns span is 200MHz. The maximum refire rate at the input to the fine vernier must not be sooner
than 4 cycles of the high-speed clock (800MHz).
Table 2: Suggested Operating Modes
Program Rate
Interleaved
INA
INB
TSET[0:9] Range
200Mbps
Yes
100MHz
100MHz
000 to 1FF
100Mbps
Yes
50MHz
50MHz
000 to 3FF
200Mbps
No
200MHz
Low
000 to 1FF
100Mbps
No
100MHz
Low
000 to 3FF
200Mbps
No
Low
200MHz
000 to 1FF
100Mbps
No
Low
100MHz
000 to 3FF
Data Input (INA, INB)
There are two interleaved inputs per channel. Each input is capable of running at full rate (200MHz). The
input is first retimed off of the internal 400MHz clock generated from the PLL. This means there is a 2.5ns edge
placement window that defines the setup time. This also means that the input pulse must span at least one
400MHz clock edge.
The inputs are low to high edge sensitive. Figure 1 illustrates an equivalent circuit of the input structure for
each channel. Note that the TSET input clock is generated based on the input data.
Page 2
 VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52335-0,Rev.4.0
8/28/00
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
High-Speed Octal
Programmable Timing Generator
VSC6048
Figure 1: Input Interleave
INxA
D
SET Q
D
CLR Q
D
INxB
D
TSET_CLK
D
SET Q
D
CLR Q
DATA
SET Q
CLR Q
400MHz
PLL
RCK
800MHz
FSEL
BYP
Figure 2: Functional Timing Diagram
tRATETS
TSET[0:9]
tSETSU
tSETH
INA
INSU
INH
INB
OUT
TSET (0000000000)
tPDTG(MIN)
tOPW
tPDV(SPAN)
tPDTG(SPAN)
OUT
TSET (1111111111)
RCK
Time Set Input (TSET<0:9>)
This is a 10-bit TTL bus that controls the delay value of the vernier. The 3 MSBs control the 800MHz shift
register and the 7 LSBs control the fine delay element. The TSET data is clocked in by a pulse generated from
the input data. The setup time of the TSET data is the same as the input signals (INA, INB). The TSET data
must be stable by the time the input edge arrives at the input pin and data must then be held stable for at least
3.5ns after the input edge arrives at the pin.
G52335-0, Rev. 4.0
8/28/00
 VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 3
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
High-Speed Octal
Programmable Timing Generator
VSC6048
Figure 3: Fine Vernier Calibration DAC Programming
One Test/Calibration Cycle
Shift Data Into
Calibration Register
Hold Data In
Calibration Register
SHIFT
2
1
3
4
5
6
1
2
3
4
5
6
DCLK
DIN
5
4
3
2
1
0
X
X
X
X
X
5
4
3
2
1
0
X
X
X
X
DAC_WR
Vernier 1 DAC Data
Vernier 0 DAC Data
CAL_DAT
(internal)
Address for Vernier 0
ADR[2:0]
Address for Vernier 1
DAC Calibration
Each fine vernier must be calibrated to a 1240ps span, one step (10ps) shorter than the 800MHz period
(1.25ns). This is accomplished by setting the fine vernier to maximum delay and adjusting the 6-bit calibration
DAC until the desired range has been achieved.
The calibration data is transferred into the device through a 3-bit serial interface. Refer to Figure 3 for the
programming sequence. Typical DCLK frequencies are 1MHz to 10MHz. Once the calibration value has been
transferred into the device, the data is written into the specified DAC by the rising edge of DCLK when
DAC_WR is HIGH. The address lines must remain stable from the enable of SHIFT to one cycle after the disable of DAC_WR.
DAC Application
There are three DAC_REF pins on this device. Each pin supplies the reference for two or three calibration
DACs. In order to reduce crosstalk between verniers through the DAC_REF supply, it is recommended that
each DAC_REF pin be isolated from each other. This will reduce crosstalk between the the three channel
groups, however, it will not effect crosstalk between verniers within each group.
Table 3: DAC Reference Pin Identification
DAC_REF Pin #
Vernier Channels
1
0, 1, 2
18
3, 4
40
5, 6, 7
Outputs
Each channel has a differential ECL output. The output of the verniers is falling edge active. The shift register propagates a 2ns pulse. The fine vernier then stretches the pulse width based on the programmed delay.
Page 4
 VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52335-0,Rev.4.0
8/28/00
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
High-Speed Octal
Programmable Timing Generator
VSC6048
DC Characteristics
Table 4: Single Ended ECL Inputs and Outputs
Parameter
Description
Min
Typ
Max
Units
VOH
Output HIGH Voltage
-1020
VOL
Output LOW Voltage
-2000
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IIH
IIL
Conditions
-
-700
mV
-
-1620
mV
-1165
-
-700
mV
-2000
-
-1475
mV
Input HIGH Current
-
-
200
uA
VIN = VIH (max)
Input LOW Current
-50
-
-
uA
VIN = VIL (min)
NOTE: VTT = -2.0V ± 5%, VCC = VCCA = GND, RLOAD = 50Ω to -2.0V.
Table 5: Differential ECL Inputs and Outputs
Parameter
Description
Min
Typ
Max
Units
VDIFF
Input Voltage Differential
200
-
-
mV
VCM
Common-Mode Voltage
-1.5
-
-0.5
V
Conditions
Required for full output
swing
Common-mode range
required for full output swing
with VDIFF applied
Figure 4: Differential ECL Input Voltages
Pad
PadN
VDIFF/2
VDIFF/2
VCM
G52335-0, Rev. 4.0
8/28/00
 VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 5
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
High-Speed Octal
Programmable Timing Generator
VSC6048
Table 6: TTL Inputs and Outputs
Parameter
Description
Min
Typ
Max
Units
Conditions
VOH
Output HIGH Voltage
2.4
-
-
V
IOH = -2.4mA
VOL
Output LOW Voltage
0
-
0.4
V
IOL = 16 mA
VIH
Input HIGH Voltage
2.0
-
VTTL+1.0V
V
-
VIL
Input LOW Voltage
0
-
0.8
V
-
IIH
Input HIGH Current
-
-
50
µA
VIN = 2.4V
IIL
Input LOW Current
-500
-
-
µA
VIN = 0.4V
IOZH
Tri-State Output OFF Current HIGH
-
-
200
µA
VOUT = 2.4V
IOZL
Tri-State Output OFF Current LOW
-100
-
-
µA
VOUT = 0.4V
IOZLB
Tri-State Output OFF Current Low for
Bi-directs
-600
-
-
µA
VOUT = 0.4V
IOCZ
Open Collector Output Leakage
Current
-
-
200
µA
VOUT = 2.4V
NOTE: All specifications are over recommended commercial operating conditions, TTL/GND = GND.
Table 7: Power Supply Requirements
Parameter
ITT
IDACREF
ITTL
Description
Max
Units
Power Supply Current from VTT
3.4
mA
Power Supply Current from
VDACREF
80
mA
Power Supply Current from VTTL
250
mA
8
W
Min
PD
Power Dissipation(1)
NOTE: (1) Output power dissipation does not include load power.
Page 6
Typ
 VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Conditions
G52335-0,Rev.4.0
8/28/00
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
High-Speed Octal
Programmable Timing Generator
VSC6048
Table 8: AC Characteristics
Parameter
Description
Min
Typ
Max
Units
tRATE IN
INA and INB Reprogram Rate
5
ns
tRATE TS
TSET Reprogram Rate, 200MHz Application
5
ns
tRATE TS
TSET Reprogram Rate, 100MHz Application
10
tRES
Nominal Resolution (tPDV(SPAN)/ 127)
tSPAN
Propagation Delay, 200MHz Application
Full TG Span (TSET = 0011111111)
After Vernier Span DAC Calibration
tPDTG(SPAN)
ns
10
ps
4980
4990
ps
Propagation Delay, 100MHz Application
Full TG Span (TSET = 1111111111)
After Vernier Span DAC Calibration
9980
9990
ps
tPDV(SPAN)
Propagation Delay
Vernier Delay Element Span (TSET=0001111111)
After Vernier Span DAC Calibration
1230
1240
ps
tPDTG(MIN)
Propagation Delay
TG Minimum Delay (TSET=000000000)
11.0
14.0
ns
tPDV(MIN)
Propagation Delay
Vernier Delay Element Zero Delay
1300
1700
ps
INL
Integral Non-Linearity
Dynamic on-the-fly TSET Switching
-4
+4
LSBs
DNL
Differential Non-Linearity
Dynamic on-the-fly TSET Switching
-4
+4
LSBs
DCV
Variation in Delay vs. Duty Cycle and Frequency
Full TG Span (TSET=1111111111)
-40
+40
ps
DTCO
Variation in Delay vs. Temperature
Full TG Span (TSET=1111111111)
-6
+6
ps/°C
PSRR
Variation in Delay vs. Supply Voltage
Full TG Span (TSET=1111111111)
-8
+8
ps/100mV
OSJ
Random Output Signal Jitter
10
ps rms
DACRES
Calibration DAC Resolution
25
ps
tOPW
Width of the Output Pulse
tR/tF
Output Rise/Fall Times (20% to 80%)
INSU
IN0 - IN7 to REF_CLK Setup(1)
250
Hold(1)
1750
800
2500
300
ps
ps
1250
ps
INH
IN0 - IN7 to REF_CLK
ps
tSETSU
TSET [0:9] Setup with Respect to IN
250
ps
tSETH
TSET [0:9] Hold with Respect to IN
3500
ps
INPW
IN0 - IN7 Pulse Width
2
ns
NOTE: (1) The rising edge of the input (INA, INB) must fall in the setup region defined from 250ps to 1250ps before the rising
edge of the reference clock (RCK, RCKN).
G52335-0, Rev. 4.0
8/28/00
 VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 7
VITESSE
SEMICONDUCTOR CORPORATION
High-Speed Octal
Programmable Timing Generator
Data Sheet
VSC6048
Absolute Maximum Ratings(1)
Power Supply Voltage (VTT) ..........................................................................................................-2.5V to +0.5V
Power Supply Voltage (VDACREF) .................................................................................................-0.5V to +4.3V
Power Supply Voltage (VTTL) ........................................................................................................-0.5V to +4.3V
ECL Input Voltage Applied, (VIN ECL) ................................................................................+0.5V to VTT + -0.5V
TTL Input Voltage Applied, (VIN TTL)................................................................................. -0.5V to VTTL + 1.0V
Output Current (IOUT) ................................................................................................................................... 50mA
Case Temperature Under Bias (TC)............................................................................................. -55oC to + 125oC
Storage Temperature (TSTG)........................................................................................................ -65oC to + 150oC
Recommended Operating Conditions
Power Supply Voltage (VTT) ..................................................................................................................-2.0V ± 5 %
Power Supply Voltage (VDACREF) ........................................................................................................ +3.0V ± 5 %
Power Supply Voltage (VTTL) ............................................................................................................... +3.3V ± 5 %
Commercial Operating Temperature Range(2) (T) .............................................................................. 0oC to 70oC
NOTES: (1) Caution: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without causing
permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended
periods may affect device reliability.
(2) Lower limit of specification is ambient temperature and upper limit is case temperature.
ESD Ratings
Proper ESD procedures should be used when handling this product. The VSC6048 is rated to the following
ESD voltages based on the human body model:
1. All pins are rated at or above 1500V.
Page 8
 VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52335-0,Rev.4.0
8/28/00
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
High-Speed Octal
Programmable Timing Generator
VSC6048
Package Pin Description
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
TSET34
TSET33
TSET32
TSET31
TSET30
VTT
TSET29
TSET28
TSET27
TSET26
TSET25
TSET24
TSET23
VCC
TSET22
TSET21
TSET20
TSET19
TSET18
TSET17
VTT
TSET16
TSET15
TSET14
TSET13
TSET12
TSET11
TSET10
VTTL
TSET09
TSET08
TSET07
TSET06
TSET05
TSET04
TSET03
TSET02
TSET01
VCC
VTT
Figure 5: Pin Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
VITESSE
VSC6048
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
TSET00
VCC
BYP
FSEL
ADR2
ADR1
ADR0
OUT0N
OUT0
VCC
OUT1N
OUT1
VTT
OUT2N
OUT2
VCC
OUT3N
OUT3
NC
OUT4N
OUT4
VTT
OUT5N
OUT5
VTT
OUT6N
OUT6
VTT
OUT7N
OUT7
DCLK
SHIFT
VCC
DAC_WR
PLLRST
DIN
VCC
TSET79
TSET78
TSET77
TSET43
TSET44
TSET45
TSET46
TSET47
TSET48
TSET49
TSET50
VCC
TSET51
TSET52
TSET53
TSET54
TSET55
TSET56
TSET57
VTT
TSET58
TSET59
TSET60
TSET61
TSET62
TSET63
VCC
TSET64
TSET65
TSET66
TSET67
TSET68
TSET69
TSET70
VTTL
TSET71
TSET72
TSET73
TSET74
TSET75
TEST76
VTT
VCC
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
DAC_REF
VCC
TSET35
TSET36
TSET37
TSET38
TSET39
VTT
IN0A
IN0B
IN1A
IN1B
IN2A
IN2B
IN3A
IN3B
VCC
DAC_REF
VPLL
VGND
RCK
RCKN
VCC
VGND
VPLL
VTT
IN4A
IN4B
IN5A
IN5B
IN6A
IN6B
IN7A
IN7B
VCC
TSET40
TSET41
TSET42
VTT
DAC_REF
G52335-0, Rev. 4.0
8/28/00
 VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 9
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
High-Speed Octal
Programmable Timing Generator
VSC6048
Table 9: Pin Identifications
Page 10
Pin #
Signal Name
Signal Type
Levels
1
DAC_REF
—
+3.0V
Description
DAC Reference Supply
2
VCC
—
0V
3
TSET35
TTL
I
Timeset Data for Channel 3, Bit 5
4
TSET36
TTL
I
Timeset Data for Channel 3, Bit 6
5
TSET37
TTL
I
Timeset Data for Channel 3, Bit 7
6
TSET38
TTL
I
Timeset Data for Channel 3, Bit 8
7
TSET39
TTL
I
Timeset Data for Channel 3, Bit 9
8
VTT
—
-2.0V
9
IN0A
ECL
I
Ground
Power Supply
Channel 0, Input A
10
IN0B
ECL
I
Channel 0, Input B
11
IN1A
ECL
I
Channel 1, Input A
12
IN1B
ECL
I
Channel 1, Input B
13
IN2A
ECL
I
Channel 2, Input A
14
IN2B
ECL
I
Channel 2, Input B
15
IN3A
ECL
I
Channel 3, Input A
16
IN3B
ECL
I
Channel 3, Input B
17
VCC
—
0V
18
DAC_REF
—
+3.0V
DAC Reference Supply
19
VPLL
—
-2.0V
PLL Power Supply
20
VGND
—
0V
21
RCK
ECL
I
PLL Reference Clock
22
RCKN
ECL
I
PLL Reference Clock, Complementary
23
VCC
—
0V
24
VGND
—
0V
25
VPLL
—
-2.0V
PLL Power Supply
Power Supply
26
VTT
—
-2.0V
27
IN4A
ECL
I
Ground
PLL Ground
Ground
PLL Ground
Channel 4, Input A
28
IN4B
ECL
I
Channel 4, Input B
29
IN5A
ECL
I
Channel 5, Input A
30
IN5B
ECL
I
Channel 5, Input B
31
IN6A
ECL
I
Channel 6, Input A
32
IN6B
ECL
I
Channel 6, Input B
33
IN7A
ECL
I
Channel 7, Input A
34
IN7B
ECL
I
Channel 7, Input B
35
VCC
—
0V
36
TSET40
TTL
I
Timeset Data for Channel 4, Bit 0
37
TSET41
TTL
I
Timeset Data for Channel 4, Bit 1
Ground
 VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52335-0,Rev.4.0
8/28/00
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
High-Speed Octal
Programmable Timing Generator
VSC6048
Pin #
Signal Name
Signal Type
38
TSET42
TTL
I
39
VTT
—
-2.0V
40
DAC_REF
—
+3.0V
41
TSET43
TTL
I
Timeset Data for Channel 4, Bit 3
42
TSET44
TTL
I
Timeset Data for Channel 4, Bit 4
43
TSET45
TTL
I
Timeset Data for Channel 4, Bit 5
44
TSET46
TTL
I
Timeset Data for Channel 4, Bit 6
45
TSET47
TTL
I
Timeset Data for Channel 4, Bit 7
46
TSET48
TTL
I
Timeset Data for Channel 4, Bit 8
47
TSET49
TTL
I
Timeset Data for Channel 4, Bit 9
48
TSET50
TTL
I
Timeset Data for Channel 5, Bit 0
49
VCC
—
0V
50
TSET51
TTL
I
Timeset Data for Channel 5, Bit 1
51
TSET52
TTL
I
Timeset Data for Channel 5, Bit 2
52
TSET53
TTL
I
Timeset Data for Channel 5, Bit 3
53
TSET54
TTL
I
Timeset Data for Channel 5, Bit 4
54
TSET55
TTL
I
Timeset Data for Channel 5, Bit 5
55
TSET56
TTL
I
Timeset Data for Channel 5, Bit 6
56
TSET57
TTL
I
Timeset Data for Channel 5, Bit 7
57
VTT
—
-2.0V
58
TSET58
TTL
I
Timeset Data for Channel 5, Bit 8
59
TSET59
TTL
I
Timeset Data for Channel 5, Bit 9
60
TSET60
TTL
I
Timeset Data for Channel 6, Bit 0
61
TSET61
TTL
I
Timeset Data for Channel 6, Bit 1
62
TSET62
TTL
I
Timeset Data for Channel 6, Bit 2
63
TSET63
TTL
I
Timeset Data for Channel 6, Bit 3
Description
Timeset Data for Channel 4, Bit 2
Power Supply
DAC Reference Supply, +3.0V
Ground
Power Supply
64
VCC
—
0V
65
TSET64
TTL
I
Timeset Data for Channel 6, Bit 4
66
TSET65
TTL
I
Timeset Data for Channel 6, Bit 5
67
TSET66
TTL
I
Timeset Data for Channel 6, Bit 6
68
TSET67
TTL
I
Timeset Data for Channel 6, Bit 7
69
TSET68
TTL
I
Timeset Data for Channel 6, Bit 8
70
TSET69
TTL
I
Timeset Data for Channel 6, Bit 9
71
TSET70
TTL
I
Timeset Data for Channel 7, Bit 0
Ground
72
VTTL
—
+3.3V
73
TSET71
TTL
I
Timeset Data for Channel 7, Bit 1
74
TSET72
TTL
I
Timeset Data for Channel 7, Bit 2
75
TSET73
TTL
I
Timeset Data for Channel 7, Bit 3
G52335-0, Rev. 4.0
8/28/00
Levels
TTL Power Supply
 VITESSE SEMICONDUCTOR CORPORATION
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Page 11
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
High-Speed Octal
Programmable Timing Generator
Page 12
VSC6048
Pin #
Signal Name
Signal Type
Levels
Description
76
TSET74
TTL
I
Timeset Data for Channel 7, Bit 4
77
TSET75
TTL
I
Timeset Data for Channel 7, Bit 5
78
TSET76
TTL
I
Timeset Data for Channel 7, Bit 6
79
VTT
—
-2.0V
Power Supply
80
VCC
—
0V
81
TSET77
TTL
I
Timeset data for Channel 7, Bit 7
Ground
82
TSET78
TTL
I
Timeset data for Channel 7, Bit 8
83
TSET79
TTL
I
Timeset data for Channel 7, Bit 9
84
VCC
—
0V
85
DIN
TTL
I
Serial Calibration Data for Vernier Delay Setting
86
PLLRST
TTL
I
Resets PLL Feedback Counter
87
DAC_WR
TTL
I
Write Pulse for DAC Register
Ground
88
VCC
—
0V
89
SHIFT
TTL
I
Enables Shift of Data in the Calibration Register
Ground
90
DCLK
TTL
I
Clock for Serial Data Shift for Calibration Register
91
OUT7
ECL
O
Delayed Signal Output Channel 7
92
OUT7N
ECL
O
Delayed Signal Output Channel 7, Complementary
93
VTT
—
-2.0V
Power Supply
94
OUT6
ECL
O
Delayed Signal Output Channel 6
95
OUT6N
ECL
O
Delayed Signal Output Channel 6, Complementary
96
VCC
—
0V
Ground
97
OUT5
ECL
O
Delayed Signal Output Channel 5
98
OUT5N
ECL
O
99
VTT
—
-2.0V
100
OUT4
ECL
O
Delayed Signal Output Channel 4
101
OUT4N
ECL
O
Delayed Signal Output Channel 4, Complementary
Delayed Signal Output Channel 5 Complementary
Power Supply
102
NC
—
—
Not Connected
103
OUT3
ECL
O
Delayed Signal Output Channel 3
104
OUT3N
ECL
O
Delayed Signal Output Channel 3, Complementary
105
VCC
—
0V
Ground, 0V
106
OUT2
ECL
O
Delayed Signal Output Channel 2
107
OUT2N
ECL
O
Delayed Signal Output Channel 2, Complementary
108
VTT
—
-2.0V
Power Supply
 VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52335-0,Rev.4.0
8/28/00
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
High-Speed Octal
Programmable Timing Generator
VSC6048
Pin #
Signal Type
Levels
Description
109
OUT1
ECL
O
Delayed Signal Output Channel 1
110
OUT1N
ECL
O
Delayed Signal Output Channel 1 Complementary
111
VCC
—
0V
Ground
112
OUT0
ECL
O
Delayed Signal Output Channel 0
113
OUT0N
ECL
O
Delayed Signal Output Channel 0, Complementary
114
ADR0
TTL
I
Address Bit 0 for Vernier Calibration
115
ADR1
TTL
I
Address Bit 1 for Vernier Calibration
116
ADR2
TTL
I
Address Bit 2 for Vernier Calibration
117
FSEL
TTL
I
Selects Reference Clock Frequency
118
BYP
TTL
I
PLL Bypass Mode
119
VCC
—
0V
120
TSET00
TTL
I
Ground
Timeset Data for Channel 0, Bit 0
121
VTT
—
-2.0V
122
VCC
—
0V
123
TSET01
TTL
I
Timeset Data for Channel 0, Bit 1
124
TSET02
TTL
I
Timeset Data for Channel 0, Bit 2
125
TSET03
TTL
I
Timeset Data for Channel 0, Bit 3
126
TSET04
TTL
I
Timeset Data for Channel 0, Bit 4
127
TSET05
TTL
I
Timeset Data for Channel 0, Bit 5
128
TSET06
TTL
I
Timeset Data for Channel 0, Bit 6
129
TSET07
TTL
I
Timeset Data for Channel 0, Bit 7
130
TSET08
TTL
I
Timeset Data for Channel 0, Bit 8
131
TSET09
TTL
I
Timeset Data for Channel 0, Bit 9
132
VTTL
—
+3.3V
133
TSET10
TTL
I
Timeset Data for Channel 1, Bit 0
134
TSET11
TTL
I
Timeset Data for Channel 1, Bit 1
135
TSET12
TTL
I
Timeset Data for Channel 1, Bit 2
136
TSET13
TTL
I
Timeset Data for Channel 1, Bit 3
137
TSET14
TTL
I
Timeset Data for Channel 1, Bit 4
138
TSET15
TTL
I
Timeset Data for Channel 1, Bit 5
139
TSET16
TTL
I
Timeset Data for Channel 1, Bit 6
140
VTT
—
-2.0V
141
TSET17
TTL
I
Timeset Data for Channel 1, Bit 7
142
TSET18
TTL
I
Timeset Data for Channel 1, Bit 8
143
TSET19
TTL
I
Timeset Data for Channel 1, Bit 9
144
TSET20
TTL
I
Timeset Data for Channel 2, Bit 0
145
TSET21
TTL
I
Timeset Data for Channel 2, Bit 1
146
TSET22
TTL
I
Timeset Data for Channel 2, Bit 2
147
VCC
—
0V
G52335-0, Rev. 4.0
8/28/00
Signal Name
Power Supply
Ground
TTL Power Supply
Power Supply
Ground,
 VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 13
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
High-Speed Octal
Programmable Timing Generator
VSC6048
Pin #
Signal Name
Signal Type
Levels
Description
148
TSET23
TTL
I
Timeset Data for Channel 2, Bit 3
149
TSET24
TTL
I
Timeset Data for Channel 2, Bit 4
150
TSET25
TTL
I
Timeset Data for Channel 2, Bit 5
151
TSET26
TTL
I
Timeset Data for Channel 2, Bit 6
152
TSET27
TTL
I
Timeset Data for Channel 2, Bit 7
153
TSET28
TTL
I
Timeset Data for Channel 2, Bit 8
154
TSET29
TTL
I
Timeset Data for Channel 2, Bit 9
155
VTT
—
-2.0V
156
TSET30
TTL
I
Timeset Data for Channel 3, Bit 0
157
TSET31
TTL
I
Timeset Data for Channel 3, Bit 1
158
TSET32
TTL
I
Timeset Data for Channel 3, Bit 2
159
TSET33
TTL
I
Timeset Data for Channel 3, Bit 3
160
TSET34
TTL
I
Timeset Data for Channel 3, Bit 4
Power Supply
Ground and Power Supply Pins
2, 17, 23, 35, 49,
64 80, 84, 88, 96,
105, 111, 119,
122, 147
VCC
8, 26, 39, 57, 79,
93, 99, 108, 121,
140, 155
VTT
72, 132
VTTL
19, 25
VPLL
Page 14
20, 24
VGND
1, 18, 40
DAC_REF
 VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52335-0,Rev.4.0
8/28/00
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
High-Speed Octal
Programmable Timing Generator
VSC6048
Package Information
The VSC6048 is packaged in a thermally-enhanced 160-pin PQFP with an embedded heat sink.
SYMBOL
E
D
AMAX
A1
A2
e
b1
c1
θ
L
L1
L2
HE
HD
θ2
θ3
R
R1
G52335-0, Rev. 4.0
8/28/00
Dimensions in Millimeters
Min
27.9
27.9
3.25
0.2
0
0.6
30.8
30.8
Nom
28
28
0.35
3.35
0.65
0.3
0.15
0.8
1.6
0.8
31.2
31.2
15
15
0.2
0.2
Max
28.1
28.1
4
NOTES:
E, D
b1
c1
Excluding the tie bar cutting stub
Lead width of basemetal.
Lead thickness of basemetal.
3.45
0.4
10
1
31.6
31.6
 VITESSE SEMICONDUCTOR CORPORATION
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Page 15
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
High-Speed Octal
Programmable Timing Generator
VSC6048
Package Thermal Characteristics
The VSC6048 is packaged in an 160-pin, 28x28mm thermally-enhanced PQFP with an internal heat
spreader. These packages use industry-standard EIAJ footprints, which have been enhanced to improve thermal
dissipation. The construction of the packages are as shown in Figure 6. The VSC6048 is designed to operate
with a case temperature up to 70oC. The user must guarantee that the temperature specification is not violated.
Figure 6: Package Cross Section
Plastic Molding Compound
Exposed Heat Slug
Insulator
Lead
Wire Bond
Thermal Epoxy
Die
Table 10: Thermal Resistance
Symbol
Value
Units
Thermal resistance from junction-to-case
1.3
oC/W
Thermal resistance from case-to-ambient, still air
16.5
oC/W
θCA-100
Thermal resistance from case-to-ambient, 100 LFPM air
14.1
oC/W
θCA-200
Thermal resistance from case-to-ambient, 200 LFPM air
12.3
oC/W
θCA-400
Thermal resistance from case-to-ambient, 400 LFPM air
10.7
oC/W
θCA-600
Thermal resistance from case-to-ambient, 600 LFPM air
9.3
oC/W
θCA-800
Thermal resistance from case-to-ambient, 800 LFPM air
7.9
oC/W
θJC
θCA-0
Page 16
Description
 VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52335-0,Rev.4.0
8/28/00
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
High-Speed Octal
Programmable Timing Generator
VSC6048
Ordering Information
The order number for this product is formed by a combination of the device number, and package type.
VSC6048
xx
Device Type
High-Speed Octal
Programmable Timing Generator
Package
QV: 160-Pin PQFP, 28x28mm Body
Notice
This document contains information about a product during its fabrication or early sampling phase of
development. The information contained in this document is based on design targets, simulation results or early
prototype test results. Characteristic data and other specifications are subject to change without notice. Therefore the reader is cautioned to confirm that this datasheet is current prior to design or order placement.
Warning
Vitesse Semiconductor Corporation’s product are not intended for use in life support appliances, devices or
systems. Use of a Vitesse product in such applications without written consent is prohibited.
G52335-0, Rev. 4.0
8/28/00
 VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 17
VITESSE
SEMICONDUCTOR CORPORATION
High-Speed Octal
Programmable Timing Generator
Page 18
 VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Data Sheet
VSC6048
G52335-0,Rev.4.0
8/28/00