VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC8132 2.488Gb/s 1:32 SONET/SDH Demux Features • 2.488Gb/s 1:32 Demultiplexer • 77.76, 51.84, and 38.88MHz TTL Clock Outputs • SONET STS-48/SDH STM-16 • Single 3.3V supply • HSPECL Differential Serial Data and Clock Inputs • Loss of Clock Alarm • 32-Bit TTL Parallel Data Outputs with Odd/ Even Parity Check • 2.05W Max Power Dissipation • Loss of Data Alarm • 128-Pin PQFP Package • Frame Detect Synchronization General Description The VSC8132 demultiplexes a 2.488Gb/s HSPECL serial input datastream (DI+) to 32-bit wide, TTL 77.76Mb/s parallel data outputs D[31:0] for SONET/SDH applications. A 2.488GHz HSPECL input clock (CLKI+) is used to time the incoming data and 3 TTL clock outputs, at frequencies of 77.76MHz, 51.84MHz, and 38.88MHz, are generated for upstream devices (DATACLK78, CLK51, CLK38). Odd or even parity is performed on the incoming high-speed data via the TTL Parity Select input (PARSEL), and a TTL Parity output (PARITY) is provided to indicate parity of the input data. Frame Detect on the incoming data is controlled via the Frame Detect Inhibit (OOFN) and Reset (RESET) TTL inputs. A frame detect monitors the incoming data steam and screens for 2 bits in A1 byte out of the 8 bits and 2 bits of A2 byte out of the 8 bits. When a Frame Detect occurs, a synchronization TTL output (SYNC) will be set. Alarm indicators are used to monitor the activity of the clock and data with TTL compatible control inputs (ALMRESET) and outputs (DTALARM, CKALARM). Only a single 3.3V power supply is required for device operation. The VSC8132 is packaged in a thermally-enhanced 128-pin, 14x20x2mm PQFP package. VSC8132 Block DIagram OOFN Framing and Parity RESET PARSEL DATA[3:0] SYNC PARITY DI+ DI– DATACLK78 1:32 Demux Clock Generation CLKI+ CLK51 CLK38 CLKI– DTALARM Alarms ALMRESET G52250-0, Rev 3.1 12/7/00 CKALARM © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Page 1 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC8132 2.488Gb/s 1:32 SONET/SDH Demux Functional Description High-Speed Clock and Data Interface The incoming high-speed data and high-speed clock are received by high-speed inputs DI+ and CLKI+. The inputs are internally biased to accommodate AC-coupling. The data and clock inputs are internally terminated by a center-tapped resistor network. For differential input DC-coupling, the network is terminated to the appropriate termination voltage, VTERM providing a 50Ω to VTERM termination for both true and complement inputs. For differential input AC-coupling, the network is terminated to VTERM via a blocking capacitor. In most situations, these inputs will have high transition density and little DC offset. However, in cases where this does not hold, direct DC connection is possible. All serial data and clock inputs have the same circuit topology as shown in Figure 1. The reference voltage is created by a resistor divider as shown. If the input signal is driven differentially and DC-coupled to the part, the mid-point of the input signal swing should be centered about this reference voltage and not exceed the maximum allowable amplitude. For single-ended, DCcoupling operations, it is recommended that the user provides an external reference voltage which has better temperature and power supply noise rejection than the on-chip resistor divider. The external reference should have a nominal value equivalent to the common mode switch point of the DC-coupled signal, and can be connected to either side of the differential gate. Figure 1: High-Speed Clock and Data Inputs Chip Boundary VCC = 3.3V 1.65V 1.65V CIN 100nF Z0 CAC 100nF 50Ω 3kΩ 3kΩ 3kΩ 3kΩ VTERM Z0 CIN 100nF II 50Ω VEE = 0V Page 2 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com G52250-0, Rev 3.1 12/7/00 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC8132 2.488Gb/s 1:32 SONET/SDH Demux Low-Speed Data Interface The 77.76Mb/s parallel data outputs D[31:0] are clocked out of the VSC8132 on the falling clock edge of the 77.76MHz output clock (DATA78CLK). The data and clock are TTL levels. The MSB (D31) bit is the first bit into the serial interface. Parity Selection The parity output bit (PARITY) is clocked out on the falling edge of the 77.76MHz clock (DATA78CLK). This bit indicates the parity of the 32 bits of data along with the frame sync bit. The parity of the output is determined by the parity select input (PARSEL). When the parity select input is LOW, the output parity is odd. When the parity select is HIGH, the output parity is even. The parity inputs and outputs are TTL levels. See Figure 2 for output timing relationship. Framing Logic Interface When a frame detect occurs and the frame detect inhibit input (OOFN) is set LOW, the frame detect output (SYNC) is set HIGH on the negative edge of the 77.76MHz clock and on the 3rd set of four A2 bytes at the 32bit data output. The frame detect mechanism is inhibited when the frame detect inhibit (OOFN) input is set HIGH. The frame detect output and frame detect inhibit are TTL levels. NOTE: The 77.76MHz clock misses one clock cycle during a frame detect. This missed cycle occurs one clock period before the Sync pulse is set HIGH (see Figure 4). To use as a framer: Step 1: Set OOFN LOW Step 2:Wait for Sync pulse Step 3:When Sync Pulse goes HIGH, set OOFN HIGH Chip Reset Chip reset (RESET) will reset the framing logic so that no frame detection barrel shifting is performed. Therefore, if the frame detect inhibit input is set high, the chip will act as a simple demux after reset. The reset should be set high for 16 clock cycles of the high speed clock input. The chip reset is a TTL level. Alarm Logic Interface The Loss of Clock (CKALARM) and Loss of Data (DTALARM) alarms monitor the activity of the clock and data. The Alarm Reset (ALMRESET) input controls the alarm activity. Polling of the alarms signals are initiated by toggling the Alarm Reset input HIGH and then LOW one time. To reset both alarm outputs, the Alarm Reset should be toggled HIGH to LOW two times. All alarm logic interface signals are TTL levels. Supplies The VSC8132 is specified as a HSPECL/TTL device with a single positive 3.3V supply. Normal operation is to have VCC = +3.3V and VEE = ground. Should the user desire to use the device in a ECL environment with a negative 3.3V supply, VCC will be ground and VEE will be -3.3V. If used with VEE tied to -3.3V, the TTL output signals are still referenced to VEE. G52250-0, Rev 3.1 12/7/00 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Page 3 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC8132 2.488Gb/s 1:32 SONET/SDH Demux Decoupling of the power supplies is a critical element in maintaining the proper operation of the part. It is recommended that the VCC power supply be decoupled using a 0.1µF and 0.01µF capacitor placed in parallel on each VCC power supply pin as close to the package as possible. If room permits, a 0.001µF capacitor should also be placed in parallel with the 0.1µF and 0.01µF capacitors mentioned above. Recommended capacitors are low-inductance ceramic SMT X7R devices. For the 0.1µF capacitor, a 0603 package should be used. The 0.01µF and 0.001µF capacitors can be either 0603 or 0402 packages. For low frequency decoupling, 47µF tantalum, low-inductance SMT caps should be sprinkled over the board’s main +3.3V power supply and placed close to the C-L-C pi filter. If the device is being used in an ECL environment with a -3.3V supply, all references to decoupling VCC must be changed to VEE, and all references to decoupling 3.3V must be changed to -3.3V. AC Characteristics Figure 2: Output Timing tPD1 tPD2 78MHz CLK 78MHz DATA SYNC PULSE PARITY Figure 3: Data Output Timing tSERSU DI+ Differential Serial Data Input tSERHO D31 D0 LSB MSB Time CLKI+ Differential Clock Input NOTE: Bit 31 (MSB) is received first, Bit 0 (LSB) is received last. Page 4 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com G52250-0, Rev 3.1 12/7/00 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC8132 2.488Gb/s 1:32 SONET/SDH Demux Figure 4: Framing Sequence Missed Clock Pulse(1) Approximately <110µs CLK78 (Out)(1) SYNC PULSE (Out) OOFN (In) (asynchronous) Set HIGH, less than 110µs after SYNC goes HIGH NOTE: (1) No missing clock pulse for CLK78 when VSC8132 is working as a dumb demux. Once frame occurs and OOFN is set HIGH, the no framing will occur until OOFN is set LOW again. The VSC8132 will remain framed with SONET frame. Table 1: AC Characteristics Parameters Description Min Typ Max Units Conditions tDATApd Data Valid From Falling Edge of 77.76MHz 230 1250 ps External load = 5pf tCLKRpd High-speed Clock Rising Edge to 77.76MHz Clock Rising Edge 2.5 8.0 ns External load = 5pf tCLKFpd High-Speed Clock Rising Edge to 77.76MHz Clock Falling Edge 2.3 7.1 ns External load = 5pf tDEDGE D[0:31] Edge Rate (10%-90%) - 2.0 ns External load = 5pf tCLKEDGE 77.76, 51.84, 38.88MHz Edge Rates (10%-90%) - 2.0 ns External load = 5pf tCONEDGE Control Signals (SYNC, PARITY, DTALARM, and CKALARM) Edge Rate (10%-90%) - 2.0 ns tSERSU DI+ Setup Time with Respect to Falling Edge of CLKI+ 100 - ps See Figure 3 tSERHO DI+ Hold Time with Respect to Falling Edge of CLKI+ 75 - ps See Figure 3 fMAX Demux Input Maximum Clock Frequency - 2.9 GHz tCLK38Rpd High-Speed Clock Rising Edge to 38.88MHz Clock Rising Edge. 2.0 6.3 ns External load = 5pf tCLK38Fpd High-Speed Clock Rising Edge to 38.88MHz Clock Falling Edge 2.0 5.9 ns External load = 5pf tCLK51Rpd High-Speed Clock Rising Edge to 51.84MHz Clock Rising Edge 2.0 6.0 ns External load = 5pf tCLK51Fpd High-Speed Clock Rising Edge to 51.84MHz Clock Falling Edge 2.0 5.9 ns External load = 5pf tPD1, tPD2 Data Invalid Window 0, 230 0, 1250 ps G52250-0, Rev 3.1 12/7/00 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com External load = 5pf Page 5 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC8132 2.488Gb/s 1:32 SONET/SDH Demux DC Characteristics Table 2: DC Characteristics (Over recommended operating conditions) Parameters Description Min Typ Max Units Conditions VOHttl Output HIGH Voltage (TTL) 2.4 — — V IOH = -1.0mA VOLttl Output LOW Voltage (TTL) — — 0.5 V IOL = +1.0mA VIHttl Input HIGH Voltage (TTL) 2.0 — — V IIH = 300µA VILttl Input LOW Voltage (TTL) — — 0.8 V IIL = -50µA VOHpecl Output HIGH Voltage (HSPECL) VCC1.02 — VCC0.7 V Output tied to 50Ω to VCC-2.0V VOLpecl Output LOW Voltage (HSPECL) VCC2.0 — VCC1.62 V Output tied to 50Ω to VCC-2.0V 1200 mV AC-coupled, internally biased to VCC/2 1200 mV AC-coupled, internally biased to VCC/2 Demux Clock Input Absolute Voltage ∆VDIFF(CLKI) Differential Peak-to-Peak Swing (CLKI+) 400 — ∆VDIFF(DI) Demux Serial Input Absolute Voltage Differential Peak-to-Peak Swing (DI+) 400 VCC Supply Voltage 3.14 — 3.47 V 3.3V± +5% PD Power Dissipation — 1.6 2.05 W Outputs open, VCC = VCC max IDD Supply Current — 489 591 mA Outputs open, VCC = VCC max — Absolute Maximum Ratings (1) Power Supply Voltage (VCC)...........................................................................................................-0.5V to +3.8V DC Input Voltage (differential inputs).....................................................................................-0.5V to VCC +0.5V Output Current (differential outputs)........................................................................................................... ±50mA Case Temperature Under Bias ...................................................................................................... -55oC to +125oC Storage Temperature..................................................................................................................... -65oC to +150oC Maximum Input ESD (Human Body Model)............................................................................................... 1500V NOTE: (1) CAUTION: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without causing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended periods may affect device reliability. Recommended Operating Conditions Power Supply Voltage (VCC)................................................................................................................. +3.3V+5% Operating Temperature Range ............................................................. 0oC Ambient to +85oC Case Temperature Figure 5: Parametric Measurement Information TTL Rise and Fall Time 90% 10% tR Page 6 tF © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com G52250-0, Rev 3.1 12/7/00 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC8132 2.488Gb/s 1:32 SONET/SDH Demux Package Pin Descriptions 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 VCC VEE VEE THTRIST6 DTALARM VCC VEE ALMRESET THRIST4 VEE VCC THRIST1 PARSEL THRIST5 THPAR VCC SYNC DATACLK78 VEE TH78DT0 (LSB) TH78DT1 VCC TH78DT2 TH78DT3 NC VCC Figure 6: Pin Diagram 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 VCC TH78DT4 TH78DT5 VCC TH78DT6 TH78DT7 VEE TH78DT8 TH78DT9 VCC TH78DT10 TH78DT11 VCC TH78DT12 TH78DT13 VEE TH78DT14 TH78DT15 VCC TH78DT16 TH78DT17 VCC TH78DT18 TH78DT19 VEE TH78DT20 TH78DT21 VCC TH78DT22 TH78DT23 VCC TH78DT24 TH78DT25 VEE TH78DT26 TH78DT27 VCC NC VCC VEE CKALARM VEE VCC OOFN NC NC NC CLK51CLK51+ VCC VEE CLK38CLK38+ VCC THTRIST2 THTRIST3 VEE TH78DT31 (MSB) TH78DT30 VCC TH78DT29 TH78DT28 NC VCC 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 VITESSE VSC8132 NC NC NC VCC NC VEECTERM NC VCC CLKI+ CLKINC VEE DI+ DIVEEDTERM VEE VEE NC NC NC VCC NC VCC VCC VCC VEE VEE VEE VEE VEE NC NC NC RESET NC NC NC NC G52250-0, Rev 3.1 12/7/00 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Page 7 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC8132 2.488Gb/s 1:32 SONET/SDH Demux Table 3: Pin Identifications Page 8 Pin Name I/O Level Description 1 NC - - No Connect, Leave Unconnected 2 NC - - No Connect, Leave Unconnected 3 NC - - No Connect, Leave Unconnected 4 VCC - +3.3V 5 NC - - 6 VEECTERM - GND 7 NC - - 8 VCC - +3.3V 9 CLKI+ I HSPECL High-Speed Clock Input, True 10 CLKI- I HSPECL High-Speed clock Input, Complement 11 NC - - 12 VEE - 0V 13 DI+ I HSPECL High-Speed Serial Data Input, True. PECL levels, AC-coupled, internally biased to VCC/2. 14 DI- I HSPECL High-Speed Serial Data Input, Complement. PECL levels, ACcoupled, internally biased to VCC/2. 15 VEEDTERM - GND 16 VEE - 0V Ground 17 VEE - 0V Ground 18 NC - - No Connect, Leave Unconnected 19 NC - - No Connect, Leave Unconnected 20 NC - - No Connect, Leave Unconnected 21 VCC - +3.3V 22 NC - - 23 VCC - +3.3V Power Supply 24 VCC - +3.3V Power Supply 25 VCC - +3.3V Power Supply 26 VEE - 0V Ground 27 VEE - 0V Ground 28 VEE - 0V Ground 29 VEE - 0V Ground 30 VEE - 0V Ground 31 NC - - No Connect, Leave Unconnected 32 NC - - No Connect, Leave Unconnected 33 NC - - No Connect, Leave Unconnected 34 RESET I/O TTL Power Supply No Connect, Leave Unconnected 50Ω Termination Ground for CLK± No Connect, Leave Unconnected Power Supply No Connect, Leave Unconnected Ground 50Ω Termination Ground for DI± Power Supply No Connect, Leave Unconnected Resets Framing Logic and Output Clocks © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com G52250-0, Rev 3.1 12/7/00 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC8132 2.488Gb/s 1:32 SONET/SDH Demux Pin Name I/O Level Description 35 NC - - No Connect, Leave Unconnected 36 NC - - No Connect, Leave Unconnected 37 NC - - No Connect, Leave Unconnected 38 NC - - No Connect, Leave Unconnected 39 VCC - +3.3V Power Supply 40 VEE - 0V 41 CKALARM O TTL 42 VEE - 0V 43 VCC - +3.3V 44 OOFN I TTL 45 NC - - No Connect, Leave Unconnected 46 NC - - No Connect, Leave Unconnected 47 NC - - NNo Connect, Leave Unconnected 48 CLK51- O HSPECL Low-Speed Clock Output (51.84MHz), Complement 49 CLK51+ O HSPECL Low-Speed Clock Output (51.84MHz), True 50 VCC - +3.3V 51 VEE - 0V 52 CLK38- O HSPECL Low-Speed Clock Output (38.88MHz), Complement 53 CLK38+ O HSPECL Low speed Clock Output (38.88MHz), True 54 VCC - +3.3V Ground Loss of clock output. Stays HIGH when loss of clock is detected. Ground Power Supply Frame Detect Disable Input. Disables frame detection if set HIGH. Power Supply Ground Power Supply 55 THTRIST2 I TTL Tri-State Inputs. Allows tri-stating of all output signals. Used for test only. Should be tied to VEE during normal operation. 56 THTRIST3 I TTL Tri-State Inputs. Allows tri-stating of all output signals. Used for test only. Should be tied to VEE during normal operation. 57 VEE - 0V 58 TH78DT31 O TTL Low-Speed Parallel Data (MSB) 59 TH78DT30 O TTL Low-Speed Parallel Data 60 VCC - +3.3V 61 TH78DT29 O TTL Low-Speed Parallel dData 62 TH78DT28 O TTL Low-Speed Parallel Data 63 NC - - 64 VCC - +3.3V 65 NC - - Ground Power Supply No connect, leave unconnected Power Supply No Connect, Leave Unconnected 66 VCC - +3.3V 67 TH78DT27 O TTL Low-Speed Parallel Data 68 TH78DT26 O TTL Low-Speed Parallel Data G52250-0, Rev 3.1 12/7/00 Power Supply © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Page 9 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC8132 2.488Gb/s 1:32 SONET/SDH Demux Page 10 Pin Name I/O Level Description 69 VEE - 0V 70 TH78DT25 O TTL Low-Speed Parallel Data 71 TH78DT24 O TTL Low-Speed parallel Data 72 VCC - +3.3V 73 TH78DT23 O TTL Low-Speed Parallel Data 74 TH78DT22 O TTL Low-Speed Parallel Data 75 VCC - +3.3V 76 TH78DT21 O TTL Low-Speed Parallel Data 77 TH78DT20 O TTL Low-Speed Parallel Data Ground Power Supply Power Supply 78 VEE - 0V 79 TH78DT19 O TTL Low-Speed Parallel Data 80 TH78DT18 O TTL Low-Speed Parallel Data 81 VCC - +3.3V 82 TH78DT17 O TTL Low-Speed Parallel Data 83 TH78DT16 O TTL Low-Speed Parallel Data 84 VCC - +3.3V 85 TH78DT15 O TTL Low-Speed Parallel Data 86 TH78DT14 O TTL Low-Speed Parallel Data 87 VEE - 0V 88 TH78DT13 O TTL Low-Speed Parallel Data 89 TH78DT12 O TTL Low-Speed Parallel Data Ground Power Supply Power Supply Ground 90 VCC - +3.3V 91 TH78DT11 O TTL Low-Speed Parallel Data 92 TH78DT10 O TTL Low-Speed Parallel Data 93 VCC - +3.3V 94 TH78DT9 O TTL Low-Speed Parallel Data 95 TH78DT8 O TTL Low-Speed Parallel Data 96 VEE - 0V 97 TH78DT7 O TTL Low-Speed Parallel Data 98 TH78DT6 O TTL Low-Speed Parallel Data 99 VCC - +3.3V 100 TH78DT5 O TTL Low-Speed Parallel Data 101 TH78DT4 O TTL Low-Speed Parallel Data 102 VCC - +3.3V Power Supply 103 VCC - +3.3V Power Supply 104 NC - - Power Supply Power Supply Ground Power Supply No Connect, Leave Unconnected © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com G52250-0, Rev 3.1 12/7/00 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC8132 2.488Gb/s 1:32 SONET/SDH Demux Pin Name I/O Level 105 TH78DT3 O TTL Low-Speed Parallel Data 106 TH78DT2 O TTL Low-Speed Parallel Data 107 VCC - +3.3V 108 TH78DT1 O TTL Low-Speed Parallel Data 109 TH78DT0 O TTL Low-Speed Parallel Data (LSB) 110 VEE - 0V 111 DATACLK78 O TTL Low-Speed Clock Output (77.76MHz). A divide-by-32 version of the CLKI± input clock. 112 SYNC O TTL Frame Detect Output. Set HIGH when frame detect occurs. 113 VCC - +3.3V Power Supply 114 THPAR O TTL Parity Output 115 THTRIST5 I TTL Tri-State Inputs. Allows tri-stating of all output signals. Used for test only. Should be tied to VEE during normal operation. 116 PARSEL I TTL Parity Select Input. HIGH for even; LOW for odd. 117 THTRIST1 I TTL Tri-State Inputs. Allow tri-stating of all output signals. Used for test only. Should be tied to VEE during normal operation. 118 VCC - +3.3V 119 VEE - 0V 120 THTRIST4 I TTL Tri-State Inputs. Allow tri-stating of all output signals. Used for test only. Should be tied to VEE during normal operation. 121 ALMRESET I TTL Alarm Reset. Resets and clocks out Loss of Clock and Loss of Data alarms. 122 VEE - 0V 123 VCC - +3.3V 124 DTALARM O TTL Loss of Data Output. Stays HIGH when loss of data is detected. 125 THTRIST6 I TTL Tri-state Inputs. Allow tri-stating of all output signals. Used for test only. Should be tied to VEE during normal operation. 126 VEE - 0V Ground 127 VEE - 0V Ground 128 VCC - +3.3V G52250-0, Rev 3.1 12/7/00 Description Power Supply Ground Power Supply Ground Ground Power Supply Power Supply © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Page 11 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC8132 2.488Gb/s 1:32 SONET/SDH Demux Package Information 128-Pin PQFP Package Drawing PIN 128 PIN 1 RAD. 2.92 ± .50 (2) E1 E 2.54 ± .50 EXPOSED HEATSINK EXPOSED INTRUSION 0.127 MAX. D1 D TOP VIEW 10° TYP. A2 Key mm Tolerance A 2.35 MAX A1 0.25 MAX A2 2.00 +.10 D 17.20 ±.20 D1 14.00 ±.10 E 23.20 ±.20 E1 20.00 ±.10 L .88 +.15/-.10 e .50 BASIC b .22 ±.05 θ 0°-7° R .30 TYP R1 .20 TYP A e A1 10° TYP. R R1 θ1 A Notes: 1) 2) 3) Page 12 Drawing is not to scale All dimensions in mm Package represented is also used for the 64, 80, & 100 PQFP packages. Pin count drawn does not reflect the 128 Package. STANDOFF A1 .25 θ 0.17 MAX. b NOTES: LEAD COPLANARITY L © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Package #: 101-267-7 Issue #: 1 G52250-0, Rev 3.1 12/7/00 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC8132 2.488Gb/s 1:32 SONET/SDH Demux Package Thermal Considerations The VSC8132 has been enhanced with a copper heat slug to provide a low thermal resistance path from the die to the exposed surface of the heat spreader. The thermal resistance is shown in Table 4. Table 4: Thermal Resistance Symbol Description °C/W θJC Thermal resistance from junction-to-case. 2.2 θJA Thermal resistance from junction-to-ambient with no airflow, including conduction through the leads. 26.8 Thermal Resistance with Airflow Thermal resistance with airflow is shown in Table 5. The thermal resistance value reflects all the thermal paths including through the leads in an environment where the leads are exposed. The temperature difference between the ambient airflow temperature and the case temperature should be the worst-case power of the device multiplied by the thermal resistance. Table 5: Thermal Resistance with Airflow Airflow θCA (oC/W) 100 lfpm 19.8 200 lfpm 16.7 400 lfpm 14.6 600 lfpm 13.0 Maximum Ambient Temperature without Heatsink The worst case ambient temperature without use of a heatsink is given by the equation: T A ( MAX ) = T C ( MAX ) – P ( MAX ) θ CA where: TA(MAX) ΤC(MAX) P(MAX) θCA G52250-0, Rev 3.1 12/7/00 Ambient air temperature Case temperature (+85oC) Power (2.05W) Theta case-to-ambient at appropriate airflow © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Page 13 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC8132 2.488Gb/s 1:32 SONET/SDH Demux The results of this calculation are listed in Table 6. Table 6: Maximum Ambient Air Temperature without Heatsink Airflow Max Ambient Temperature (oC) None 35.6 100 lfpm 44.4 200 lfpm 50.8 400 lfpm 55.1 600 lfpm 58.4 Note that ambient air temperature varies throughout the system based on the positioning and magnitude of heat sources and the direction of air flow. Ordering Information The order number for this product is formed by a combination of the device type and package type VSC8132 xx Device Type 2.488Gb/s 1:32 Demux, 3.3V Package QR: 128-Pin PQFP, 14x20x2mm Body Notice Vitesse Semiconductor Corporation (“Vitesse”) provides this document for informational purposes only. This document contains pre-production information about Vitesse products in their concept, development and/or testing phase. All information in this document, including descriptions of features, functions, performance, technical specifications and availabiity, is subject to change without notice at any time. Nothing contained in this document shall be construed as extending any warranty or promise, express or implied, that any Vitesse product will be available as described or will be suitable for or will accomplish any particular task. Warning Vitesse Semiconductor Corporation’s products are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without written consent is prohibited. Page 14 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com G52250-0, Rev 3.1 12/7/00