VITESSE VSC7122

VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
Quad Port Bypass Circuit for 1.0625 Gbit/sec
Fibre Channel Arbitrated Loop Disk Arrays
VSC7122
Features
• Supports ANSI X3T11 1.0625 Gbit/sec
FC-AL Disk Attach for Resiliency
• TTL Bypass Select
• Fully Differential for Minimum
Jitter Accumulation.
• 0.35W Typical Power Dissipation
• Quad PBC’s in Single Package
• 44-Pin, 10mm PQFP
• High Speed, PECL I/O’s Referenced to VDD.
• 3.3V Power Supply
General Description
The VSC7122 is a Quad Port Bypass Circuit (PBC). Four Fibre Channel PBC’s are cascaded into a single
part to minimize part count, cost, high frequency routing, and jitter accumulation. Port Bypass Circuits are used
to provide resiliency in Fibre Channel Arbitrated Loop (FC-AL) architectures. PBC’s are used within FC-AL
disk arrays to allow for resiliency and hot swapping of FC-AL drives.
A Port Bypass Circuit is a 2:1 Multiplexer with two modes of operation: NORMAL and BYPASS. In NORMAL mode, the disk drive is connected to the loop. Data goes from the 7122’s L_SOn pin to the Disk Drive RX
input and data from the disk drive TX output goes to the 7122’s L_SIn pin. Refer to Figure 2 for disk drive
application. In BYPASS mode, the disk drive is either absent or non-functional and data bypasses to the next
available disk drive. Normal mode is enabled with a HIGH on the SEL pin and BYPASS mode is enabled by a
LOW on the SEL pin. Direct Attach Fibre Channel Disk Drives have an “LRC Interlock” signal defined to control the SEL function.
Using a VSC7122 in a single loop of a disk array is illustrated in Figure 2: “Disk Array Application”. FCAL drives are all expected to be dual loop. The VSC7122 is cascaded in a manner such that all the 7122’s internal PBC’s are used in the same loop. For dual loop implementations, two or more VSC7122’s should be used.
Allocating each VSC7122 to only one of two loops preserves redundancy, prevents a single point of failure and
lends itself to on-line maintainability.
The VSC7122 is very similar to the VSC7121 except that LSO+ outputs are all full power outputs identical
to OUT. This is useful in passive backplanes to provide additional amplitude on long traces.
IN+
IN-
PBC1
G52155-0, Rev. 2.1
8/31/98
SEL4
LSI4+
LSI4-
LSO4+
LSO4-
SEL3
LSI3+
LSI3-
LSO3+
LSO3-
SEL2
LSI2+
LSI2-
LSO2+
LSO2-
SEL1
LSI1+
LSI1-
LSO1+
LSO1-
7122 Block Diagram
1
1
1
1
0
0
0
0
PBC2
PBC3
OUT+
OUT-
PBC4
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741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 1
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
Quad Port Bypass Circuit for 1.0625 Gbit/sec
Fibre Channel Arbitrated Loop Disk Arrays
VSC7122
The VSC7122 can be cascaded through the IN and OUT pins for arrays of disk drives greater than 4. For
disk arrays with a noninteger multiple of 4 disk drives, the unused PBC’s can be hardwired to bypass with a
external pulldown resistor.
Table 1 is a truth table detailing the data flow through the VSC7122. Figure 1 shows a timing diagram of the
data relationship in the VSC7122. There are no critical timing (setup, hold, or delay) parameters for the
VSC7122 as this part routes the serial data encoded with the baud clock that is extracted by a Fibre Channel
receiver. The primary AC parameter of importance is the jitter or data eye degradation inserted by the port
bypass circuit. The design of the VSC7122 minimizes jitter accummulation by using fully differential circuits.
This provides for symmetric rise and fall delays as well as noise rejection.
Table 1: Truth Table
DATA OUTPUTS
SELECT STATE
SEL1
SEL2
SEL3
SEL4
OUT
SO4
SO3
SO2
L
L
L
L
IN
IN
IN
IN
L
L
L
H
SI4
IN
IN
IN
L
L
H
L
SI3
SI3
IN
IN
L
H
L
L
SI2
SI2
SI2
IN
H
L
L
L
SI1
SI1
SI1
SI1
H
H
H
H
SI4
SI3
SI2
SI1
SO1
IN
IN
IN
IN
IN
IN
Figure 1: Timing Waveforms
IN+/LSI1+/LSI2+/LSI3+/LSI4+/-
OUT+/LSO1+/LSO2+/LSO3+/LSO4+/T1
Page 2
T2
Tjitter
 VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52155-0, Rev. 2.1
8/31/98
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
Quad Port Bypass Circuit for 1.0625 Gbit/sec
Fibre Channel Arbitrated Loop Disk Arrays
VSC7122
Figure 2: Disk Array Application
7120
normal
FC-AL DISK DRIVE
LRC Interlock
1
0
TX
E_STORE
RX
normal
FC-AL DISK DRIVE
LRC Interlock
1
7120
0
Optics
or
Copper
VSC7122 QUAD PORT BYPASS CIRCUIT
Dual SC
or
DB-9
TX
E_STORE
RX
1
0
bypass
Pulldown for Bypass
in Absense of Disk Drive
FC-AL DISK DRIVE
LRC Interlock
1
0
normal
TX
E_STORE
RX
JBOD
G52155-0, Rev. 2.1
8/31/98
 VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 3
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
Quad Port Bypass Circuit for 1.0625 Gbit/sec
Fibre Channel Arbitrated Loop Disk Arrays
VSC7122
Table 2: AC Characteristics (Over recommended operating conditions).
Parameters
Description
Min.
Max.
Units
Conditions
T1
Flow-Through Propagation Delay
Rising Edge to Rising Edge
7.0
ns
Delay with all circuits bypassed. 75
Ohm Load
T2
Flow through Propagation Delay
Falling Edge to Falling Edge
7.0
ns
Delay with all circuits bypassed. 75
Ohm load.
300
ps.
20% to 80%, tested on a sample basis
TSDR, TSDF
Serial data rise and fall time
—
Table 3: DC Characteristics (Over recommended operating conditions).
Parameters
Min
Typ
Max
Units
2.0
—
5.5
V
Conditions
VIH(TTL)
Input HIGH voltage (SEL - TTL)
VIL(TTL)
Input LOW voltage (SEL - TTL)
0
—
0.8
V
—
IIH(TTL)
Input HIGH current (SEL- TTL)
—
50
500
µA
VIN = 2.4 V
IIL(TTL)
IIH < 6.6 mA @ VIH = 5.5 V
Input LOW current (SEL - TTL)
—
—
-500
µA
VIN = 0.5 V
VDD
Supply voltage
3.10
—
3.50
V
VDD = 3.30V + 5%
IDD
Supply current
—
—
150
mA
Outputs open, VDD = VDD max
PD
Power Dissipation
0.35
0.5
W
Outputs open, VDD = VDD max
2600
mVp-p
AC Coupled.
Internally biased at VDD/2
2200
mVp-p
50Ω to VDD – 2.0 V
2200
mVp-p
75Ω to VDD – 2.0 V
Receiver differential peak-to-peak
Input Sensitivity, IN+/- & L_SIn+/-
300
∆VOUT50
Output differential peak-to-peak
voltage swing
1000
∆VOUT75
Output differential peak-to-peak
voltage swing
1200
∆VIN
Page 4
Description
—
 VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52155-0, Rev. 2.1
8/31/98
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7122
Quad Port Bypass Circuit for 1.0625 Gbit/sec
Fibre Channel Arbitrated Loop Disk Arrays
Absolute Maximum Ratings (1)
TTL Power Supply Voltage, (VDD) ..................................................................................................... 0.5V to +4V
PECL DC Input Voltage, (VINP)............................................................................................. -0.5V to VDD +0.5V
TTL DC Input Voltage, (VINT) ..........................................................................................................-0.5V to 5.5V
DC Voltage Applied to Outputs for High Output State, (VIN TTL)........................................ -0.5V to VDD + 0.5V
TTL Output Current (IOUT), (DC, Output High)........................................................................................... 50mA
PECL Output Current, (IOUT), (DC, Output High) ......................................................................................-50mA
Case Temperature Under Bias, (TC)............................................................................................... -55° to +125oC
Storage Temperature, (TSTG)......................................................................................................... -65° to + 150oC
Maximum Input ESD .................................................................................................................................. 1500 V
Recommended Operating Conditions(2)
Power Supply Voltage, (VDD) ...........................................................................................................+3.1V to 3.5V
Ambient Operating Temperature Range, (T) .....................................................................................0°C to +70°C
Notes:
1) CAUTION: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without causing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended periods may
affect device reliability.
2) Vitesse guarantees the functional and parametric operation of the part under “Recommended Operating Conditions: except
where specifically noted in the AC and DC Parametric Tables
G52155-0, Rev. 2.1
8/31/98
 VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 5
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
Quad Port Bypass Circuit for 1.0625 Gbit/sec
Fibre Channel Arbitrated Loop Disk Arrays
VSC7122
Input Structures
Two input structures exist in this part; TTL and High Speed, Differential Inputs. The TTL Inputs will interface with any TTL or 3.3V or 5V CMOS outputs. The High Speed, Differential Inputs are intended to be AC
Coupled per the FC-PH specification. Being AC Coupled, the High Speed, Differential Input buffers are biased
at VDD/2. Refer to Figure 3 for High Speed, Differential Input structure.
Figure 3: High Speed, Differential Inputs (L_SIn/IN)
VDD
+3.3 V
3.3K
VDD/2
INPUT+
3.3K
3.3K
INPUT3.3K
0V
GND
Because the VSC7122 output buffers are PECL outputs referenced to VDD, the High Speed Differential outputs may not be direct coupled to the high speed differential inputs. One example of how to differentially cascade the two VSC7122 is shown in Figure 4.
Figure 4: Cascading Two VSC7122
VDD
191
VSC7122
191
VSC7122
.01
IN+
OUT+
OUT 124
124
IN .01
75 Ohm Board/Termination Example
Page 6
 VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52155-0, Rev. 2.1
8/31/98
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
Quad Port Bypass Circuit for 1.0625 Gbit/sec
Fibre Channel Arbitrated Loop Disk Arrays
VSC7122
43
VSS
41
39
37
35
1
L_SI3-
L_SI3+
VDDP
L_SO3-
L_SO3+
VSS
L_SI2-
L_SI2+
VDDP
L_SO2-
L_SO2+
Figure 5: Pin Diagram
33
VDD
VDD
L_SI1-
31
3
29
5
VSC7122
L_SO1L_SO1+
7
25
9
OUTOUT+
23
11
VSS
VSS
VDD
21
VDD
VSS
19
SEL4
SEL3
17
SEL2
SEL1
15
VDD
VSS
13
VSS
G52155-0, Rev. 2.1
8/31/98
L_SI4VDDP
IN+
VSS
VDDP
L_SI4+
27
VSS
IN-
L_SO4+
L_SO4-
L_SI1+
VDDP
VSS
 VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
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VITESSE
SEMICONDUCTOR CORPORATION
Quad Port Bypass Circuit for 1.0625 Gbit/sec
Fibre Channel Arbitrated Loop Disk Arrays
Advance Product Information
VSC7122
Table 4: Pin Description
Pin #
Name
Description
9, 10
IN-, IN+
INPUT - Differential (Biased at VDD/2). Serial inputs from the downstream PBC port.
3, 4
L_SI1-, L_SI1+
INPUT - Differential (Biased at VDD/2). Serial input from the local transmitter on PBC
port 1.
40, 41
L_SI2-, L_SI2+
INPUT - Differential (Biased at VDD/2). Serial input from the local transmitter on PBC
port 2.
34, 35
L_SI3-, L_SI3+
INPUT - Differential (Biased at VDD/2). Serial input from the local transmitter on PBC
port 3.
27, 28
L_SI4-, L_SI4+
INPUT - Differential (Biased at VDD/2). Serial input from the local transmitter on PBC
port 4.
15-18
SEL1, SEL2,
SEL3, SEL4
INPUT - TTL. A LOW selects the “BYPASS” mode causing the output of the previous
port to propagate to next port or OUT. When HIGH, this signal selects “NORMAL”
mode which routes the previous port to the local output, L_SOn, and routes the local
input, L_SIn, to the next port or OUT .
6, 7
L_SO1-,
L_SO1+
OUTPUT - Differential Serial output driving the local receiver corresponding to PBC
port 1.
43, 44
L_SO2-,
L_SO2+
OUTPUT - Differential Serial output driving the local receiver corresponding to PBC
port 2.
37, 38
L_SO3-,
L_SO3+
OUTPUT - Differential Serial output driving the local receiver corresponding to PBC
port 3.
30, 31
L_SO4-,
L_SO4+
OUTPUT - Differential Serial output driving the local receiver corresponding to PBC
port 4.
25, 24
OUT-, OUT+
2, 14, 20-21,
32
VDD
Digital Logic Power Supply. 3.3V Supply for digital logic.
5, 26, 29 36,
42
VDDP
High-Speed Output Power Supply. 3.3V Supply for PECL drivers.
1, 8, 11-13,
19, 22-23,
33, 39
VSS
Page 8
OUTPUT - Differential Serial output driving the upstream PBC port.
Ground. Ground pins are physically attached to the die mounting surface, and are an
important part of the thermal path. For best thermal performance, all ground pins should
be connected to a ground plane, using multiple vias if possible.
 VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52155-0, Rev. 2.1
8/31/98
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
Quad Port Bypass Circuit for 1.0625 Gbit/sec
Fibre Channel Arbitrated Loop Disk Arrays
VSC7122
Package Information
44-Pin PQFP 10 x 10 mm
F
G
44
34
1
33
I
H
23
11
12
Item
mm
Tol.
A
2.35
MAX
D
2.00
+0.10
E
0.35
+.05
F
13.20
+.25
G
10.00
+.10
H
13.20
+.25
I
10.00
+.10
J
0.8
+.15 / -.10
K
0.80
BASIC
22
12o TYP
D
12o TYP
K
0.30 RAD. TYP.
A
0.25 MAX.
0.20 RAD. TYP.
NOTES:
Drawing not to scale.
Cavity up
All units in mm unless otherwise noted.
G52155-0, Rev. 2.1
8/31/98
0 o- 8 o
0.17 MAX.
0.25
0.102 MAX. LEAD
COPLANARITY
E
J
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741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
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VITESSE
SEMICONDUCTOR CORPORATION
Quad Port Bypass Circuit for 1.0625 Gbit/sec
Fibre Channel Arbitrated Loop Disk Arrays
Advance Product Information
VSC7122
Package Thermal Characteristics
The VSC7122 is packaged into a standard plastic quad flatpack with an embedded, but unexposed thermal
slug. This package adheres to industry standard EIAJ footprints for a 10x10mm body, 44 lead PQFP. The package construction is as shown in Figure 6. The 44 PQFP with embedded slug has the thermal properties shown in
Table 5. This package allows the VSC7122 to operate with ambient temperatures up to 70oC in still air.
Figure 6: Package Cross Reference
Wire Bond
Die
Plastic Molding Compound
Lead
Insulator
Table 5: 44 PQFP Thermal Resistance
Symbol
Value
Units
Thermal resistance from case to ambient, still air
50
oC/W
θca-100
Thermal resistance from case to ambient, 100 LFPM air
43
oC/W
θca-200
Thermal resistance from case to ambient, 200 LFPM air
39
oC/W
θca-400
Thermal resistance from case to ambient, 400 LFPM air
36
oC/W
θca-600
Thermal resistance from case to ambient, 600 LFPM air
34
oC/W
θca-0
Description
Moisture Sensitivity Level
This device is rated with a moisture sensitivity level 3 rating. Refer to Application Note AN-20 for appropriate handling procedures.
Page 10
 VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52155-0, Rev. 2.1
8/31/98
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
Quad Port Bypass Circuit for 1.0625 Gbit/sec
Fibre Channel Arbitrated Loop Disk Arrays
VSC7122
Ordering Information
The order number for this product is formed by a combination of the device number and package type.
VSC7122
QM
Device Type
VSC7122 - 1.0625 Gbits/sec Port Bypass Circuit
Package Type
QM: 44 Pin PQFP, 10x10mm Body
Marking Information
The package is marked with three lines of text as shown below (QM Package):
Pin Identifier
VITESSE
VSC7122QM
Part Number
####AAAA
Date Code
Package Suffix
Lot Tracking Code
Notice
This document contains information about a new product during its fabrication or early sampling phase of
development. The information in this document is based on design targets, simulation results or early prototype
test results. Characteristic data and other specifications are subject to change without notice. Therefore the
reader is cautioned to confirm that this datasheet is current prior to design or order placement.
Warning
Vitesse Semiconductor Corporation’s product are not intended for use in life support appliances, devices or
systems. Use of a Vitesse product in such applications without the written consent is prohibited.
G52155-0, Rev. 2.1
8/31/98
 VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 11
VITESSE
SEMICONDUCTOR CORPORATION
Quad Port Bypass Circuit for 1.0625 Gbit/sec
Fibre Channel Arbitrated Loop Disk Arrays
Page 12
Advance Product Information
 VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
VSC7122
G52155-0, Rev. 2.1
8/31/98