INFINEON HYB39S13620TQ-

Overview
HYB 39S13620TQ-6/-7/-8
• Special Mode Registers
• High Performance:
-6
-7
-7
-8
Units
fCK
166
125
125
125
MHz
latency
3
2
3
3
−
tCK3
6
8
7
8
ns
tAC3
5.5
5.5
5.5
6
ns
• Two color registers
• Burst Read with Single Write Operation
• Block Write and Write-per-Bit Capability
• Byte controlled by DQM0-3
• Auto Precharge and Auto Refresh Modes
• Suspend Mode and Power Down Mode
• Single Pulsed RAS Interface
• 2k refresh cycles/32 ms
• Programmable CAS Latency: 2, 3
• tAC = 5 ns
• Fully Synchronous to Positive Clock Edge
• tSETUP/tHOLD = 2 ns/1 ns
• Programmable Wrap Sequence:
Sequential or Interleave
• Latency 2 @ 125 MHz
•
• Random Column Address every CLK
(1-N Rule)
Programmable Burst Length:
1, 2, 4, 8 and full page for sequential
1, 2, 4, 8 for interleave
• Single 3.3 V ± 0.3 V Power Supply
• LVTTL compatible inputs and outputs
The HYB 39S163200TQ are dual bank Synchronous Graphics DRAM’s (SGRAM) organized as
2 banks × 256 Kbit × 32 with built-in graphics features. These synchronous devices achieve high
speed data transfer rates up to 143 MHz by employing a chip architecture that prefetches multiple
bits and then synchronizes the output data to a system clock. The chip is fabricated with an
advanced 64MBit DRAM process technology.
The device is designed to comply with all JEDEC standards set for synchronous graphics DRAM
products, both electrically and mechanically.
RAS, CAS, WE, DSF and CS are pulsed signals which are examined at the positive edge of each
externally applied clock. Internal chip operating modes are defined by combinations of these
signals. A ten bit address bus accepts address data in the conventional RAS/CAS multiplexing
style. Ten row address bits (A0 - A9) and a bank select BA are strobed with RAS. Column address
bits plus a bank select are strobed with CAS.
Prior to any access operation, the CAS latency, burst length and burst sequence must be
programmed into the device by address inputs during a mode register set cycle. An Auto Precharge
function may be enabled to provide a self-timed row precharge. This is initiated at the end of the
burst sequence. In addition, it features the write per bit, the block write and the masked block write
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HYB 39S16320TQ-6/-7/-8
functions. By having a programmable Mode register and Special Mode register, the system can
select the best suitable modes to maximize its performance.
Operating the two memory banks in an interleave fashion allows random access operation to occur
at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to
143 MHz is possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported.
These devices operate with a single 3.3 V ± 0.3 V power supply and are available in 100 pin TQFP
package.
Ordering Information
Type
Ordering Code
Package
Description
HYB 39S16320TQ-6
on request
TQFP-100-1
256k × 2 × 32 SGRAM
HYB 39S16320TQ-7
on request
TQFP-100-1
256k × 2 × 32 SGRAM
HYB 39S16320TQ-8
on request
TQFP-100-1
256k × 2 × 32 SGRAM
HYB 39S16320TQ-10
on request
TQFP-100-1
256k × 2 × 32 SGRAM
SDR LVTTL-Version
Features
• All signals fully synchronous to the positiv edge of the system clock
• Programmable burst lengths: 1, 2, 4, 8 or full page
• Burst data transfer in sequential or interleaved order
• Burst read with single write
• Programmable CAS latency: 2, 3
• 8 column block write and write-per-bit modes
• Independent byte operation via DQM 0 …3 interface
• Auto precharge and auto refresh modes
• 2k refresh cycles/32 ms
• LVTTL compatible I/O
• Hidden auto precharge for read bursts
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HYB 39S16320TQ-6/-7/-8
DQ2
V SSQ
DQ1
DQ0
V DD
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
V SS
DQ31
DQ30
V SSQ
DQ29
100 pin TQFP
20 × 14 mm2
0.65 mm pitch
(Marking side)
100
1
95
90
85
80
5
75
10
70
15
65
20
60
25
55
35
40
45
50
V DD
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
V SS
A4
A5
A6
A7
30
A0
A1
A2
A3
DQ3
V DDQ
DQ4
DQ5
V SSQ
DQ6
DQ7
V DDQ
DQ16
DQ17
V SSQ
DQ18
DQ19
V DDQ
V DD
V SS
DQ20
DQ21
V SSQ
DQ22
DQ23
V DDQ
DQM0
DQM2
WE
CAS
RAS
CS
BA
A9
DQ28
V DDQ
DQ27
DQ26
V SSQ
DQ25
DQ24
V DDQ
D15
D14
V SSQ
D13
D12
V DDQ
V SS
V DD
DQ11
DQ10
V SSQ
DQ9
DQ8
V DDQ
MCH
DQM3
DQM1
CLK
CKE
DSF
N.C.
A8 / AP
SPP03942
Pin Configuration
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Pin Definitions and Functions
CLK
Clock Input
DQ0 to DQ31
CKE
Clock Enable
DQM0 to DQM3 Data Mask
CS
Chip Select
VDD
Power (+ 3.3 V)
RAS
Row Address Strobe
VSS
Ground
CAS
Column Address Strobe
VDDQ
Power for DQ’s (+ 3.3 V)
WE
Write Enable
VSSQ
Ground for DQ’s
A0 - A9
Address Inputs
NC
Not connected
A8 - AP
Auto Precharge
DSF
Special Function Enable
BA
Bank Select
MCH
Must Connect High
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DataInput/Output
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HYB 39S16320TQ-6/-7/-8
Signal Pin Description
Pin
Type
Signal Polarity Function
CLK
Input
Pulse
Positive The system clock input. All of the SGRAM inputs are
Edge
sampled on the rising edge of the clock.
CKE
Input
Level
Active
High
Activates the CLK signal when high and deactivates the
CLK signal when low. By deactivating the clock, CKE low
initiates the Power Down mode, Suspend mode, or the Self
Refresh mode.
CS
Input
Pulse
Active
Low
CS enables the command decoder when low and disables
the command decoder when high. When the command
decoder is disabled, new commands are ignored but
previous operations continue.
RAS
CAS
WE
Input
Pulse
Active
Low
When sampled at the positive rising edge of the clock,
CAS, RAS, and WE define the operation to be executed by
the SGRAM.
A0 - A9
Input
Level
–
During a Bank Activate command cycle, A0-A9 defines the
row address (RA0-RA9) when sampled at the rising clock
edge.
During a Read or Write command cycle, A0-A7 defines the
column address (CA0-CA7) when sampled at the rising
clock edge.
In addition to the column address, CA8 is used to invoke
autoprecharge operation at the end of the burst read or
write cycle. If A8 is high, autoprecharge is selected and BA
defines the bank to be precharged (low = bank A,
high bank B). If A8 is low, autoprecharge is disabled.
During a Precharge command cycle, A8 is used in
conjunction with BA to control which bank(s) to precharge.
If A8 is high, both bank A and bank B will be precharged
regardless of the state of BA. If A8 is low, then BA is used
to define which bank to precharge.
BA
Input
Level
–
Selects which bank is activated. BA low selects bank A and
BA high selects bank B.
DQ0 DQ31
Input Level
Output
–
Data Input/Output pins operate in the same manner as on
conventional DRAMs, with the exception of the Block Write
function. In this case, the DQx pins perform a masking
operation.
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Signal Pin Description (cont’d)
Pin
Type
Signal Polarity Function
DQM0 DQM3
Input
Pulse
VDD
VSS
–
During Read, DQM = 1 turns off the output buffers.
During Write, DQM = 1 prevents a write to the current
memory location.
DQM0 corresponds to DQ0 - DQ7
DQM1 corresponds to DQ8 - DQ15
DQM2 corresponds to DQ16 - DQ23
DQM3 corresponds to DQ24 - DQ31
Supply –
–
Power and ground for the input buffers and the core logic.
VDDQ
VSSQ
Supply –
–
Isolated power supply and ground for the output buffers to
provide improved noise immunity.
DSF
Input
–
DSF is part of the input command to the SGRAM. If DSF is
low, SGRAM operates in the same way as SDRAMs. When
DSF is high it enables the block write and masked write
and special mode register setup cycle.
Level
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Functional Block Diagrams
Row Addresses
A0 - A7,
AP, BA
A0 - A9,
BA
Column
Address Buffer
Row Address
Buffer
Row
Decoder
Memory
Array
Memory
Array
Bank 0
1024 x
256 x
32 Bit
Color Register
Sense Amplifier & I(O) Bus
Row
Decoder
Column Decoder
Sense Amplifier & I(O) Bus
Column Decoder
Column
Address Counter
Column Addresses
Refresh
Counter
Bank 1
1024 x
256 x
32 Bit
Control Logic & Timing Generator
Mask Register
Input Buffer
Output Buffer
DQ0 - DQ31
DQMx DSF CLK CKE CS RAS CAS WE
SPB03936
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Functional Description
General
The 16 Mbyte SGRAM is a dual bank 1024 × 256 × 32 DRAM with graphics features of Block Write
and Masked Write. It consists of two banks. Each bank is organized as 1024 rows
× 256 columns × 32 bits.
Read and Write accesses are burst oriented. Accesses begin with the registration of an Activate
command which is then followed by a Read or Write command. The address bits registered
coincident with the Active command are used to select the bank and the row to be accessed. BA
selects the bank and address bits A9 - A0 select the row. Address bits A7 - A0 registered coincident
with the Read or Write command are used to select the starting column location for the burst
access.
Block Writes are not burst oriented and always apply to eight column locations selected by A7 - A3.
DQs registered at Block Write command are used to mask the selected columns. DQs registered
coincident with the Load Special Mode Register command are used as Color Data (LC-Bit = 1) or
Persistent Mask (LM = 1). If LC and LM are both 1 in the same Load Special Mode Register
command cycle, the data of the Mask and the Color Register will be unknown.
Initialization
The default power on state of the mode register is supplier specific and may be undefined. The
following power on and initialization sequence guarantees, that the device is preconditioned to each
users specific needs.
The following sequence is recommended:
• During power on, all VDD and VDDQ pins must be built up simultaneously to the specified voltage
when the input signals are held in the “NOP” state.
• The power on voltage must not exceed VDD + 0.3 V on any of the input pins or VDD supplies.
• The CLK signal must be started at the same time.
• After power on, an initial pause of 200 µs is required.
• The pause is followed by a precharge of both banks using the precharge command.
• To prevent data contention on the DQ bus during power on, it is required that the DQM and
CKE pins be held high during the initial pause period.
• Once all banks have been precharged, the Mode Register Set Command must be issued to
initialize the Mode Register.
• A minimum of eight Auto Refresh cycles (CBR) are also required.
It is also possible to reverse the last two steps of the initialization procedure:
First send at least 8 CBR commands, then the LMR command.
Failure to follow these steps may lead to unpredictable start-up modes.
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Mode Register Programming
The Mode Register is used to define: a Burst Length, a Burst type, a Read Latency and an operating
mode. The mode register is programmed via the Load Mode Register command and will retain the
stored information until it is programmed again or the device looses power. The mode register must
be loaded when both banks are idle and the controller must wait the specified time before initiating
the subsequent command. Violating either of these requirements may result in unknown operation.
Burst Length
Read and Write operations to the SGRAM are burst oriented, with the burst length being
programmable. The burst length determines the maximum number of column locations that can be
accessed for a given Read or Write command. Burst lengths of 1, 2, 4, or 8 locations are available
for both the sequential and the interleaved burst types and a Full Page Burst is available for the
sequential type. The Full Page Burst is used in conjunction with the Burst Terminate command to
generate arbitrary burst lengths.
When a Read or Write command is issued, a block of columns equal to the burst length is selected.
The block is defined by address bits A7 - A1 when the burst length is set to 2, by A7-A2 for burst
length set to 4 and by A7 - A3 for burst length set to 8. The lower order bit(s) are used to select the
starting location within the block. The burst will wrap within the block if a boundary is reached.
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved and the
type is selected based on the setting of BT bit in the mode register. If BT is set to “0”, the burst type
is sequential, if BT is “1”, the burst type is interleave.
Read Latency
The Read Latency is the delay in clock cycles between the registration of a Read command and the
availability of the first piece of output data. The latency can be set to 2 or 3 clocks. If a Read
command is registered at clock edge n and the Read Latency is 2 clocks, the data will be available
by clock edge n + 2. The DQs will start driving already one cycle earlier (n + 1).
Color Register
The Siemens 16M SGRAM offers two Color Registers. If Bit M7 is set to “1”, two Color Register
mode is specified.
Operation Mode
In normal operation, the bits M8 and M9 of Mode Register (MR) are set “0”. The programmed burst
length applies to both read and write bursts. When bit M8 is set to “1”, burst read and single write
mode is selected.
Test modes and reserved states should not be used because unknown operation or incompatibility
with future versions may result.
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Load Special Mode Register (LSMR)
The Special Mode Register command is used to load the mask and color registers, which are used
in Block Write and Masked Write cycles.The data to be written to either the color registers or the
Mask Register is applied to the DQs and the control information is applied to the address inputs.
During a LSMR cycle, if the address bit A6 is “1”, and all other address inputs are “0”, the Color
Register 0 will be loaded with the data on the DQs. If the address bits A6 and A7 are both set equal
to “1” and Mode Register M7 bit was already set to “1”, Color Register 1 will be loaded with the data
on the DQs.This color data is used for Block Write cycles. Similarly, when input A5 is “1”, and all
other address inputs are “0” during a LSMR cycle, the mask register will be loaded with the data on
the DQs. Never Set bit A5 to “1” when A6 and/or A7 are set equal to “1” in the same Load Special
Mode Register cycle to avoid unknown operation.
Color Registers
Two Color Registers (Color Register 0 and Color Register 1) are available in the devices. Each color
register is a 32-bit register which supplies the data during Block Write cycles. The Color Register is
loaded via a Load Special Mode Register command, as shown in the Function Truth table and will
retain data until loaded again with a new data or until power is removed from the SGRAM.
Mask Register
The Mask Register (or the Write-per-Bit mask register) is a 32-bit register which acts as a per-bit
mask during Masked Write and Masked Block Write cycles. The Mask Register is loaded via the
Load Special Mode Register command and will retain data until loaded again or until power is
removed from the SGRAM.
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Commands
The Function Truth Table provides a quick reference of available commands.
Operation
CKE
n−1
CKE
n
CS
RAS
CAS
WE
DSF
DQM
BA
A8
A0 A7
Device Deselect
(INHBT)
H
X
H
X
X
X
X
X
X
X
X
No Operation (NOP)
H
X
L
H
H
H
X
X
X
X
X
Load Mode Register
(LMR)
H
X
L
L
L
L
L
X
X
OPCODE
Load Special Mode
Register (LSMR)
H
X
L
L
L
L
H
X
X
OPCODE
Row Activate (ACT)
H
X
L
L
H
H
L
X
BA
Row Addr
Row Active with WpB
(ACTM)
H
X
L
L
H
H
H
X
BA
Row Addr
Read (RD)
H
X
L
H
L
H
X
X
BA
L
Col.
Read with Auto
Precharge (RDA)
H
X
L
H
L
H
X
X
BA
H
Col.
Write Command
(WR)
H
X
L
H
L
L
L
X
BA
L
Col.
Write Command with
Auto Precharge
(WRA)
H
X
L
H
L
L
L
X
BA
H
Col.
Block Write (BW)
H
X
L
H
L
L
H
X
BA
L
Col.
Block Write with Auto
Precharge (BWA)
H
X
L
H
L
L
H
X
BA
H
Col.
Burst Terminate
(BST)
H
X
L
H
H
L
X
X
X
X
X
Precharge Single
Bank (PRE)
H
X
L
L
H
L
X
X
BA
L
X
Precharge All Banks
(PREAL)
H
X
L
L
H
L
X
X
X
H
X
Auto Refresh (REF)
H
H
L
L
L
H
X
X
X
X
X
Self Refresh Entry
(SREF (EN)
H
L
L
L
L
H
X
X
X
X
X
Self Refresh Exit
(SREF (EX)
L
L
H
H
H
L
X
H
X
H
X
H
X
X
X
X
X
X
X
X
X
X
Power Down Mode
Entry (PDN-EN)
H
H
L
L
H
L
X
H
X
H
X
H
X
X
X
X
X
X
X
X
X
X
Power Down Mode
Exit (PDN-EX)
L
H
X
X
X
X
X
X
X
X
X
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Notes
1. All inputs are latched on the rising edge of the CLK.
2. LMR, REF and SREF commands should be issued only after both banks are deactivated
(PREAL command).
3. ACT and ACTM command should be issued only after the corresponding bank has been
deactivated (PRE command).
4. WR, WRA, RD, RDA should be issued after the corresponding bank has been activated
(ACT command).
5. Auto Precharge command is not valid for full-page burst.
6. BW and BWA commands use mask register data only after ACTM command. DQM byte masking
is active regardless of WPB mask.
7. Loading Mask Register: Initiate an LSMR cycle with address pin A5 = 1 to load the mask register
with the mask data present on DQ pins. Except A5, all other address pins must be “0” during
LSMR cycle while loading the mask register.
8. Loading Color Register: Initiate an LSMR cycle with address pin A6 = 1 to load the color register
with the color input data on DQ pins. Address pin A7 selects color register. Except A6 and A7, all
other address pins must be “0” during LSMR cycle while loading a color register. If one color
register mode is enabled, all address pins, except A6, must be “0” during LSMR cycle.
9. If BW or BWA operation is initiated and 2-Color Register Mode is initialized by the mode register,
address A0 selects the desired color register for the operation. If A0 = 0, color register 0 will be
used, if A0 = 1, color register 1.
10.Any Write or Block Write cycles to the selected bank/row while active will be masked according
to the contents of the mask register, in addition to the DQM signals and the column/byte mask
information (the later for Block Writes only).
11.Block Writes are not burst oriented and always apply to the eight column locations selected by
A7 - A3.
12.Addressline A9 is always “X” with the exception of two commands:
In LMR and LSMR commands it provides opcode (see description Mode and Special Mode
Register). In ACT and ACTM commands it provides the address bit 9 of the row address.
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Address Input for Mode Set (Mode Register Functions)
A9
A8
A7
A6
A5
A3
A4
A2
A0
A1
Address Bus (Ax)
Write Mode
CR
Burst Length
BT
CAS Latency
Mode Register (Mx)
Operation Mode
Burst Type
Mode
M3
Type
Normal
0
Sequential
Multiple Burst
1
Interleave
M9 M8
0
0
0
1
with Single Write
Color Register
Burst Length
Registers
M7
Length
0
One Color register
1
Two Color register
M2
CAS Latency
M6 M5 M4
Latency
0
0
0
Reserved
0
0
1
Reserved
0
1
0
2
0
1
1
3
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
M1 M0
Sequential
Interleave
0
0
0
1
1
0
0
1
2
2
0
1
0
4
4
0
1
1
8
8
1
0
0
Reserved
Reserved
1
0
1
Reserved
Reserved
1
1
0
Reserved
Reserved
1
1
1
Full Page
Reserved
SPB03935
Address Input for Mode Set (Mode Register Functions)
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Burst Length and Sequence
Burst of two
Starting Address
(Column Address A0)
Sequential Addressing
Sequence (decimal)
Interleave Addressing
Sequence (decimal)
0
0, 1
0, 1
1
1, 0
1, 0
Starting Address
(Column Address A1 - A0)
Sequential Addressing
Sequence (decimal)
Interleave Addressing
Sequence (decimal)
0
0, 1, 2, 3
0, 1, 2, 3
1
1, 2, 3, 0
1, 0, 3, 2
2
2, 3, 0, 1
2, 3, 0, 1
3
3, 0, 1, 2
3, 2, 1, 0
Starting Address
(Column Address A1 - A0)
Sequential Addressing
Sequence (decimal)
Interleave Addressing
Sequence (decimal)
0
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
1
1, 2, 3, 4, 5, 6, 7, 0
1, 0, 3, 2, 5, 4, 7, 6
2
2, 3, 4, 5, 6, 7, 0, 1
2, 3, 0, 1, 6, 7, 4, 5
3
3, 4, 5, 6, 7, 0, 1, 2
3, 2, 1, 0, 7, 6, 5, 4
4
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
5
5, 6, 7, 0, 1, 2, 3, 4
5, 4, 7, 6, 1, 0, 3, 2
6
6, 7, 0, 1, 2, 3, 4, 5
6, 7, 4, 5, 2, 3, 0, 1
7
7, 0, 1, 2, 3, 4, 5, 6
7, 6, 5, 4, 3, 2, 1, 0
Burst of four
Burst of eight
Full page Burst
Full Page Burst is an extension of the above tables of sequential addressing with the burst length
being 256.
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Special Mode Register Functions
Address Bits
Functions
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
0
0
0
1
0
0
0
0
0
Load Mask Register
0
0
0
1
0
0
0
0
0
0
Load Color Register 0
0
0
1
1
0
0
0
0
0
0
Load Color Register 1
Note: If only one Color Register is in use, A7 is Don’t Care.
Special Mode Register Naming Conventions
Address bit name
Special name
Function
A5
LM
Load Mask Enable
A6
LC
Load Color Enable
A7
SCR
Select Color Register
Device Deselect (INHBT)
The device deselect or inhibit function prevents commands from being executed by the SGRAM,
regardless of whether the CLK signal is enabled. The device is effectively deactivated (CS is high).
No Operation (NOP)
The NOP command is used to perform a no operation to an SGRAM which is selected (CS is low).
This prevents unwanted commands being registered during idle or wait states. The execution of the
command(s) already in progress will not be affected.
Load Mode Register (LMR)
The Mode Register is loaded via address input pins A9 - A0 . The LMR command can only be issued
when both banks are idle, and a subsequent executable command can not be issued until 2 CLK
cycle Latency is met.
Load Special Mode Register (LSMR)
LSMR command is used to load either the Color Register(s) or the Mask Register at a time. The
control information is provided on inputs A9 - A0, while the data for the Color or Mask Register is
provided on the DQs. The LSMR command can be issued when both banks are idle, or one or both
are active but with no Read, Write or Block Write accesses in progress.
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Active (ACT)
The ACT command is used to open (or activate) a row in a particular bank. The value on BA selects
the bank and the address provided on input pins A9 - A0 selects the row. This row remains open
for accesses until a Precharge command is issued to the bank. A Precharge command must be
issued before opening a different row in the same bank.
Active with WPB (ACTM)
ACTM command is similar to the ACT command, except that the Write-per-Bit mask is activated.
Any Write or Block Write cycles to the selected bank/row while active will be masked according to
the contents of the Mask Register.
Read (RD)
The Read command is used to initiate a burst read access from an active row. The value on BA
selects the bank and the address provided on inputs A7 - A0 selects the starting column location.
The value on A8 determines whether or not Auto Precharge is used. If A8 is “1”, Auto Precharge is
used. If Auto Precharge is selected, the row being accessed will be precharged at the end of the
read burst; if Auto Precharge is not selected, the row will remain open for subsequent accesses. If
a particular DQM was registered high, the corresponding DQs appearing 2 clocks later on the
output pins will be High-Z.
Write (WR)
The Write command is used to initiate a burst write access to an active row. The value on BA selects
the bank and the address provided on inputs A7 -A0 selects the starting column location. The value
on A8 determines whether or not Auto Precharge is used. If A8 is “1”, Auto Precharge is used. If
Auto Precharge is selected, the row being accessed will be precharged at the end of write burst; if
Auto Precharge is not selected, the row will remain open for subsequent accesses. If a particular
DQM is registered high, the corresponding data inputs will be ignored and the write will not be
executed to that byte location.
Block Write (BW)
The Block Write command is used to write a single data value to the block of eight consecutive
column locations addressed by inputs A7 - A3 . The data is provided by the Color Register which
must be loaded prior to the Block Write cycle by invoking LSMR cycle. If the two Color Register
option is enabled, the address line A0 is used to select the desired Color Register. A “0” at A0
selects Color Register 0, a “1” Color Register 1. The input data on DQs which is registered
coincident with the Block Write command is used to mask specific column/byte combinations within
the block. The DQM signals operate the same way as for Write cycles, but are applied to all eight
columns in the selected block.
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HYB 39S16320TQ-6/-7/-8
Precharge (PRE)
The Precharge command is used to deactivate the open row in a particular bank or the open row in
both banks. The bank(s) will be available for row access some specified time (tRP) after the
Precharge command is issued. Input A8 determines whether one or both banks are to be
precharged, input BA selects the bank. If A8 is “1”, both banks are to be precharged and BA is “don't
care.” Once a bank is precharged (or deactivated), it is in the idle state and must be activated prior
to any Read, Write, or Block Write commands being issued to that bank.
Auto Precharge (PREA)
The Auto Precharge feature allows the user to issue a Read, Write, or Block Write command that
automatically performs a precharge upon the completion of the Block Write access or Read or Write
burst, except in the Full Page Burst mode, where it has no effect. The use of this feature eliminates
the need to “manually” issue a Precharge command during the functional operation of the SGRAM.
Burst Terminate (BST)
The Burst Terminate command is used to truncate either fixed-length or Full Page Bursts.
Auto Refresh (REF)
Auto Refresh is used to refresh the various rows in the SGRAM and is analogous to CAS-beforeRAS (CBR) in DRAMs. This command must be issued each time a refresh is required. The
addressing is generated by the internal refresh counter, therefore, the address bits are “don't care”
during a CBR cycle. The SGRAM requires that 2048 rows to be refreshed every 32 ms (tREF). This
refresh can be accomplished either by providing an Auto Refresh command every 15.6 µs or all
2048 Auto Refresh commands can be issued in a burst at the minimum cycle rate (tRC) once every
32 ms.
Self Refresh (SREF)
The Self Refresh command can be used to retain data in the SGRAM, even if the rest of the system
is powered down. When in the Self Refresh mode, the SGRAM retains data without external
clocking. Once the SREF command is registered, all the inputs to the SGRAM become “don't care”
with the exception of CKE, which must remain low. Once SREF mode is engaged, the SGRAM
provides its own internal clocking, causing it to perform its own Auto Refresh cycles. The SGRAM
may remain in Self Refresh mode for an indefinite period. The procedure for exiting requires a
sequence of commands. First, the system clock must be stable prior to CKE going high. Once CKE
is high, the SGRAM must have NOP commands issued for tSRX, because of the time required for the
completion of any bank currently being internally refreshed.
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HYB 39S16320TQ-6/-7/-8
Detailed Description of WRITE COMMANDS (WR, Masked Writes, Block Write)
Write Command (WR)
The following pages illustrate the Write operations for various cases.
Summary Write Commands
Mnemonic
CKE
CS
RAS
CAS
WE
DSF
DQM
BA
A8
Address
Lines
WR
H
L
H
L
L
L
0
BA
L
Column
WRA
H
L
H
L
L
L
0
BA
H
Column
BW
H
L
H
L
L
H
0
BA
L
Column
BWA
H
L
H
L
L
H
0
BA
H
Column
Notes
1. Input data at DQ pins at Block Write command is registed as a column mask for that block of
columns
2. Explanation of Mnemonics:
WR:
Write Command
WRA: Write Command with Auto Precharge
BW:
Block Write
BWA:
Block Write with Auto Precharge
BA:
Bank Select
Write bursts are initiated with a Write command. The starting column and bank address is provided
with the Write command, normal or Block Write is selected, and Auto Precharge is either enabled
or disabled for that access. If Auto Precharge is enabled, the row being accessed is precharged
automatically at the completion of the burst.
During Write bursts, the first valid data-in element will be registered coincident with the Write
command. Sub-sequent data elements will be registered on successive positive clock edge. Upon
completion of a fixed-length burst, assuming no other commands have been initiated, the DQs will
remain High-Z, and any additional data will be ignored. A full-page burst will continue until
terminated (at the end of the page, it will wrap to column 0 and continue).
A fixed-length Write burst may be followed by, or truncated with a subsequent Write burst or Block
Write command (provided that Auto Precharge was not activated) and a full page Write burst can
be truncated with a subsequent Write burst or Block Write command. The new Write or Block Write
command can be issued on any clock following the previous Write command, and the data provided
coincident with the new command applies to the new command. To truncate a Block Write, the tBWC
parameter has to be met.
A fixed-length Write burst may be followed by, or truncated with a subsequent Read burst (provided
that Auto Precharge was not activated) and a full-page Write burst can be truncated with a
subsequent Read burst. Once the Read command is registered, the data inputs will be ignored, and
writes will not be executed.
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A fixed-length Write burst may be followed by, or truncated with a Precharge command to the same
bank (provided that Auto Precharge was not activated) and a full-page Write burst may be truncated
with a Precharge command to the same bank. The Precharge command should be issued x cycles
(x = tWR/tCK rounded up to the next whole number) after the clock edge at which the last desired
input data element is registered. In addition, the DQM signals must be used to mask input data,
starting with the clock edge following the last desired data element and ending with the clock edge
on which the Precharge command is entered. A Precharge command issued at the optimum time
provides the same operation that would result from the same fixed-length Burst with Auto
Precharge.
Disadvantages of Write Command with Auto Precharge
1. Back to back Read/Write bursts can not be initiated. The Read/Write command with Auto
Precharge will automatically initiate a precharge of the row in the selected bank. Most of the
applications require subsequent Read/Write bursts in the same page.
2. The Auto Precharge command does not allow truncation of fixed-length bursts. It also does not
apply to Full Page bursts.
Terminating a Write Burst
The fixed-length or Full-Page Write bursts can be truncated with the Burst Terminate command.
When truncating a Write burst, the input data applied one clock edge prior to the Burst Terminate
command will be the last data written.
Masked Writes
Any Write performed to a row that was activated via an Active with WPB command is a Write-perBit-Mask (WPBM). Data is written to the 32 cells at the selected column location subject to the mask
stored in the WPB mask register. The data to be written in the DRAM cell will be according to the
following mask:
Write Masking Function Representation
DQM
MR
DRAM Cell
0
0
Mask
1
0
Mask
1
1
Mask
0
1
Write
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HYB 39S16320TQ-6/-7/-8
Symbolic Representation of Write Masking Function
DQ
DQM
DRAM
Cell
&
MR
SPS03710
If a particular bit in the WPB mask register is a “0”, the data appearing on the corresponding DQ
input will be ignored, and the existing data in the corresponding DRAM cell will remain unchanged.
If a mask data is a “1”, the data appearing on the corresponding DQ input will be written to the
corresponding DRAM cell. The overall Write mask consists of a combination of the DQM inputs,
which will mask on a per-byte basis, and the WPB mask register, which masks on a per-bit basis.
If a particular DQM signal was registered high, the corresponding byte will be masked. A given bit
is written if the corresponding DQM signal registered is “0”and the corresponding WPB mask
register bit is “1”.
Note that the DQM Latency for Write is zero.
Block Write (BW)
Each Block Write cycle writes a single data value from a Color Register to the block of eight
consecutive column locations addressed by A7 - A3. If Single Color Register Mode is enabled, the
content of Color Register 0 is written. If both Color Registers are enabled, address pin A0 selects
the desired Color Register. Address A0 = 0 selects Color Register 0, address pin A0 = 1 Color
Register 1. The information on the DQs which is registered coincident with the Block Write
command is used to mask specific column/byte combinations within the block.
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HYB 39S16320TQ-6/-7/-8
Bit Mask mapping of DQ bits
Address
within Written
Block
Byte within Data Word
Byte 3
Byte 2
Byte 1
Byte 0
0
DQ24
DQ16
DQ8
DQ0
1
DQ25
DQ17
DQ9
DQ1
2
DQ26
DQ18
DQ10
DQ2
3
DQ27
DQ19
DQ11
DQ3
4
DQ28
DQ20
DQ12
DQ4
5
DQ29
DQ21
DQ13
DQ5
6
DQ30
DQ22
DQ14
DQ6
7
DQ31
DQ23
DQ15
DQ7
The table shows the masking of data caused by the registered value on the DQ pins, when data is
transfered from Color Register to the 8 succeeding memory locations addressed in the Write Block
command.
When a “1” is registered, the Color Register data will be written to the corresponding DRAM cells,
subject to the DQM and the WPB masking. The overall Block Write mask consists of a combination
of the DQM signals, the WPB mask register and the column/byte mask information.
Block Write Timing Considerations
A Block Write access requires a time period of tBWC to execute, so in general, the cycle after the
Block Write command should be a NOP. However, Active or Precharge commands to the other
bank are allowed. When following a Block Write with a Precharge command to the same bank, tBPL
must be met.
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HYB 39S16320TQ-6/-7/-8
Write Data
Color Register
Mask write, keep original data
MDQ0 = 1
MDQ1 = 1
MDQ2 = 0
MDQ3 = 1
MDQ4 = 0
MDQ6 = 1
MDQ7 = 0
DQ0 = 1
i
DQ1 = 1
i+1
DQ2 = 1
i+2
DQ3 = 0
i+3
DQ4 = 0
i+4
DQ5 = 1
i+5
DQ6 = 1
i+6
DQ7 = 0
Write-per-Bit
Mask Data = Mask Register + DQMi
Column Address
Column address mask
from DQ pins
MDQ7 - MDQ0
01001011
MDQ5 = 0
Color Data
Mask Register
i+7
SPS03711
Block Write Illustration
Note: Only single Color Register and Byte 0 of Color Register is used in this example.
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HYB 39S16320TQ-6/-7/-8
Electrical Characteristics
Absolute Maximum Ratings
Operating temperature range .........................................................................................0 to + 70 °C
Storage temperature range..................................................................................... – 55 to + 150 °C
Input/output voltage .......................................................................................... – 0.3 to VDD + 0.3 V
Power supply voltage VDD/VDDQ ............................................................................... – 0.3 to + 4.6 V
Power Dissipation ....................................................................................................................... 1 W
Data out current (short circuit) ................................................................................................ 50 mA
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Recommended Operation and DC Characteristics
TA = 0 to 70 °C; VSS = 0 V; VDD,VDDQ = 3.3 V ± 0.3 V
Parameter
Symbol
Limit Values
min.
max.
Unit Notes
Input high voltage
VIH
2.0
VDD + 0.3
V
1, 2
Input low voltage
VIL
– 0.3
0.8
V
1, 2
Output high voltage (IOUT = – 2.0 mA)
VOH
2.4
–
V
Output low voltage (IOUT = 2.0 mA)
VOL
–
0.4
V
Input leakage current, any input
(0 V < VIN < 3.6 V, all other inputs = 0 V)
II(L)
–5
5
µA
Output leakage current
(DQ is disabled, 0 V < VOUT < VDD)
IO(L)
–5
5
µA
Notes
1. All voltages are referenced to VSS
2. VIH may overshoot to VDD + 2.0 V for pulse width of < 4 ns with 3.3 V. VIL may undershoot to
–2.0 V for pulse width < 4 ns with 3.3 V. Pulse width measured at 50% points with amplitude
measured peak to DC reference.
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HYB 39S16320TQ-6/-7/-8
Capacitance
TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz
Parameter
Symbol
max. Values
Unit
Input capacitance (A0 to A9, BA)
CI1
4
pF
Input capacitance
(RAS, CAS, WE, CS, CLK, CKE, DQM, DSF)
CI2
4
pF
Output capacitance (DQ)
CIO
6
pF
Operating Currents
TA = 0 to 70 °C, VDD = 3.3 V ± 0.3 V
(Recommended Operating Conditions unless otherwise noted)
Parameter & Test
Condition
Symb. -6
-7
-8
Unit
Note
max.
Operating current
CAS Latency = 3 tRC ≥tRC(MIN.),
CAS Latency = 2 tCK ≥ tCK(MIN.), IO = 0 mA
2
ICC1
200 200 180 mA
180 180 170
Precharge standby current CKE ≤ VIL(MAX.) tCK = tCK(MIN.) ICC2P
in Power Down Mode
CKE ≤ VIL(MAX.), tCK = infinite ICC2PS
3
2
3
2
3
2
mA
2
Precharge standby current CKE ≥ VIH(MIN.) tCK ≥ tCK(MIN.), ICC2N
in Non Power Down Mode input changed once in 30 ns
CKE ≥ VIH(MIN.), tCK = infinite, ICC2NS
no input change
60
60
60
mA
2
15
15
15
mA
3
3
3
3
3
3
mA
mA
90
90
90
mA
30
30
25
mA
Active standby current in
Power Down Mode
CKE ≤ VIL(MAX.), tCK ≥tCK(MIN.)
CKE ≤ VIL(MAX.), tCK = infinite
Active standby current in
Non-Power Down Mode
CKE ≥ VIH(MIN.), tCK ≥ tCK(MIN.) ICC3N
input changed every 30 ns
CKE ≥ VIH(MIN.), tCK = infinite, ICC3NS
no input change
Burst Operating Current
CAS Latency = 3 Burst Length = full page
tRC = infinite
CAS Latency = 2 tCK ≥ tCK(MIN.), IO = 0 mA,
2 banks interleave
ICC3P
ICC3PS
2, 3
ICC4
200 200 190 mA
200 200 190 mA
2
Auto (CBR) Refresh
Current
CAS Latency = 3 tRC ≥ tRC(MIN.)
CAS Latency = 2
ICC5
170 170 160 mA
160 160 160
Self Refresh Current
CKE ≤ 0,2 V
2
Operating Current
(Block Write)
tCK ≥ tCK(MIN.), IO = 0 mA
tBWC = tBWC(MIN.)
200 200 190 mA
Semiconductor Group
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2
2
mA
1998-10-01
HYB 39S16320TQ-6/-7/-8
Notes
1. All values are preliminary and subject to future change
2. These parameters depend on the cycle rate and these values are measured by the cycle rate
under the minimum value of tCK and tRC. Input signals are changed one time during tCK.
3. These parameters depend on output loading. Specified values are obtained with output open.
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HYB 39S16320TQ-6/-7/-8
AC Characteristics
TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns
Parameter
Symb.
Limit Values
-6
-7
Unit
Note
-8
min.
max.
min.
max.
min.
max.
Clock Cycle Time
CAS Latency = 3 tCK3
CAS Latency = 2 tCK2
6
8
–
–
7
8
–
–
8
10
–
–
ns
ns
System frequency
CAS Latency = 3 –
CAS Latency = 2 –
–
–
166
125
–
–
143
125
–
–
125
100
MHz
MHz
Clock Access time
(for 30 pF load)
CAS Latency = 3 tAC3
CAS Latency = 2 tAC2
–
–
5.5
5.5
–
–
5.5
5.5
–
–
6
6
ns
ns
Clock and Clock Enable
Clock High Pulse width
tCH
2.5
–
3
–
3
–
ns
Clock Low Pulse width
tCL
2.5
–
2.5
–
3
–
ns
CKE Setup time
tCKS
2
–
2
–
2.5
–
ns
CKE Hold time
tCKH
1
–
1
–
1
–
ns
0.5
10
0.5
10
0.5
10
ns
Transition time (rise and fall) tT
2
2
Common Parameters
3
Command Setup time
tCS
2
–
2
–
2.5
–
ns
Command Hold time
tCH
1
–
1
–
1
–
ns
Address Setup time
tAS
2
–
2
–
2.5
–
ns
Address Hold time
tAH
1
–
1
–
1
–
ns
Active to Read or Write
delay
tRCD
18
–
21
–
24
–
ns
4
Cycle time
tRC
66
–
70
–
80
–
ns
4
Active to Precharge
command period
tRAS
48
100k
49
100k
56
100k
ns
4
Row Precharge time
tRP
18
–
21
–
24
–
ns
4
Active Bank A to Active
Bank B command period
tRRD
12
–
14
–
16
–
ns
4
CAS to CAS delay time
(same bank)
tCCD
1
–
1
–
1
–
CLK
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HYB 39S16320TQ-6/-7/-8
AC Characteristics (cont’d)
TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns
Parameter
Symb.
Limit Values
-6
-7
Unit
Note
CLK
5
–
5
6
-8
min.
max.
min.
max.
min.
max.
2
–
2
–
2
–
Refresh Cycle
Self Refresh Exit time
tSREX
Total Self Refresh Exit time
–
Refresh Period for
Non-Self Refresh
tREF
–
32
–
32
–
32
ms
Data Out Hold time
tOH
2.5
–
2.5
–
3
–
ns
Data Out to Low Impedance
time
tLZ
0
–
0
–
0
–
ns
Data Out to High Impedance tHZ
time
3
8
3
8
3
8
ns
2 CLKs + tRC
Read Cycle
7
Write Cycle
Data In Setup time
tDS
3
–
2
–
2.5
–
ns
Data In Hold time
tDH
1
–
1
–
1
–
ns
Write recovery time
tWR
6
–
7
–
8
–
ns
Block Write Cycle Time
tBWC
12
–
14
–
16
–
ns
Block Write to Precharge
delay
tBWR
12
–
14
–
16
–
ns
tRSC
2
–
2
–
2
–
CLK
Block Write Cycle
Miscellaneous
Mode Register command to
command
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HYB 39S16320TQ-6/-7/-8
Notes
1. AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover
point. The transition time is measured between VIH and VIL. All AC measurements assume
tT = 1 ns with the AC output load circuit shown.
t CH
2.4 V
0.4 V
CLOCK
t CL
t SETUP
tT
t HOLD
INPUT
1.4 V
t AC
t LZ
t AC
t OH
OUTPUT
1.4 V
t HZ
SPT03404
I/O
50 pF
Measurement conditions for
tAC and tOH
2. If clock rising time is longer than 1ns, a time (tT/2 − 0.5) ns has to be added to this parameter.
3. If tT is longer than 1 ns, a time (tT − 1) ns has to be added to this parameter.
4. These parameter account for the number of clock cycle and depend on the operating frequency
of the clock, as follows: Number of clock cycle = specified value of timing period (counted in
fractions as a whole number)
5. Self Refresh Exit is a synchronous operation and begins on the second positiv edge after CKE
returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the
Self Refresh Exit command is registered.
6. Any time that the refresh Period has been exceeded, a minimum of two Auto (CRB) Refresh
commands must be given to “wake-up“ the device.
7. Referenced to the time which the output achieves the open circuit condition, not to output voltage
levels.
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HYB 39S16320TQ-6/-7/-8
Clock Frequency and Latency
Parameter
Symbol
Speed Sort
-6
Unit
-7
-8
Clock Frequency
max.
−
166
125
143
125
125
MHz
Clock Cycle time
min.
tCK
6
8
7
8
8
ns
CAS Latency
min.
tAA
3
2
3
2
3
CLK
RAS to CAS delay
min.
tRCD
3
3
3
3
3
CLK
Bank Active Cycle time
min.
tRAS
8
6
7
6
7
CLK
Bank Active Cycle time
max.
tRAS
100
100
100
100
100
µs
Precharge time
min.
tRP
3
3
3
3
3
CLK
Bank Cycle time
min.
tRC
11
9
10
9
10
CLK
Last Data In to Precharge
min.
tWR
1
1
1
1
1
CLK
Last Data In to Active/Refresh
min.
tWR + tRP
4
4
4
4
4
CLK
Bank to Bank delay time
min.
tRRD
2
2
2
2
2
CLK
CAS to CAS delay time
min.
tCCD
1
1
1
1
1
CLK
Write Latency
fixed
tWL
0
0
0
0
0
CLK
DQM Write Mask Latency
fixed
tDQW
0
0
0
0
0
CLK
DQM Data Disable Latency
fixed
tDQZ
2
2
2
2
2
CLK
Clock Suspend Latency
fixed
tCSL
1
1
1
1
1
CLK
Block Write Cycle time
fixed
tBWC
2
2
2
2
2
CLK
Semiconductor Group
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HYB 39S16320TQ-6/-7/-8
Package Outlines
Plastic Package, P-TQFP-100
(20 × 14 mm2, 0.65 mm lead pitch)
Thin Small Outline Package, SMD
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device
Semiconductor Group
30
Dimensions in mm
1998-10-01
HYB 39S16320TQ-6/-7/-8
Timing Diagrams
1
Bank Activate Command Cycle
2
Burst Read Operation
3
Read Interrupted by a Read
4
4.1
4.2
4.3
4.4
Read to Write Interval
Read to Write Interval
Minimum Read to Write Interval
Non-Minimum Read to Write Interval
Single Bit Write Cycle
5
5.1
5.2
5.3
5.4
Burst Write Operation
Burst Write
Load Mode Register and Block Write Cycle
Read and DQM Function
Write and DQM Function
6
6.1
6.2
Write and Read Interrupt
Write Interrupted by a Write
Write Interrupted by a Read
7
7.1
7.2
Burst Write and Read with Auto Precharge
Burst Write with Auto Precharge
Burst Read with Auto Precharge
8
8.1
8.2
Burst Termination
Termination of a Full Page Burst Read Operation
Termination of a Full Page Burst Write Operation
9
9.1
9.2
AC Parameters
AC Parameters for Write Timing
AC Parameters for Read Timing
10
Mode Register Set
11
Power on Sequence and Auto Refresh (CBR)
12
12.1
12.2
12.3
12.4
Clock Suspension (Using CKE)
Clock Suspension During Burst Read CAS Latency = 2
Clock Suspension During Burst Read CAS Latency = 3
Clock Suspension During Burst Write CAS Latency = 2
Clock Suspension During Burst Write CAS Latency = 3
13
Power Down Mode and Clock Suspend
14
Self Refresh (Entry and Exit)
Semiconductor Group
31
1998-10-01
HYB 39S16320TQ-6/-7/-8
Timing Diagrams (cont’d)
15
Auto Refresh (CBR)
16
16.1
16.2
Random Column Read (Page within same Bank)
CAS Latency = 2
CAS Latency = 3
17
17.1
17.2
Random Column Write (Page within same Bank)
CAS Latency = 2
CAS Latency = 3
18
18.1
18.2
Random Row Read (Interleaving Banks) with Precharge
CAS Latency = 2
CAS Latency = 3
19
19.1
19.2
Random Row Write (Interleaving Banks) with Precharge
CAS Latency = 2
CAS Latency = 3
20
20.1
20.2
Full Page Read Cycle
CAS Latency = 2
CAS Latency = 3
21
21.1
21.2
Full Page Write Cycle
CAS Latency = 2
CAS Latency = 3
22
22.1
Precharge Termination of a Burst
CAS Latency = 2
Semiconductor Group
32
1998-10-01
HYB 39S16320TQ-6/-7/-8
1. Bank Activate Command Cycle
(CAS latency = 3)
T0
T1
T
T
T
T
T
CLK
Address
Bank B
Col. Addr.
Bank B
Row Addr.
Bank A
Row Addr.
t RCD
Command
Bank B
Activate
NOP
Bank B
Row Addr.
t RRD
NOP
Write B
with Auto
Precharge
Bank A
Activate
NOP
Bank B
Activate
t RC
"H" or "L"
Semiconductor Group
SPT03784
33
1998-10-01
HYB 39S16320TQ-6/-7/-8
2. Burst Read Operation
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
Read A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CLK
Command
CAS
latency = 2
t CK2 , DQ’s
CAS
latency = 3
t CK3 , DQ’s
Semiconductor Group
DOUT A0 DOUT A1 DOUT A2 DOUT A3
DOUT A0 DOUT A1 DOUT A2 DOUT A3
SPT03712
34
1998-10-01
HYB 39S16320TQ-6/-7/-8
3. Read Interrupted by a Read
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
Read A
Read B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CLK
Command
CAS
latency = 2
t CK2 , DQ’s
CAS
latency = 3
t CK3 , DQ’s
Semiconductor Group
DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3
DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3
SPT03713
35
1998-10-01
HYB 39S16320TQ-6/-7/-8
4. Read to Write Interval
4.1. Read to Write Interval
(Burst Length = 4, CAS latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Minimum delay between the Read and Write
Commands = 4 + 1 = 5 cycles
Write latency t DQW of DQMx
DQMx
t DQZ
Command
NOP
Read A
DQ’s
NOP
NOP
NOP
DOUT A0
NOP
Write B
NOP
NOP
DIN B0
DIN B1
DIN B2
Must be Hi-Z before
the Write Command
"H" or "L"
Semiconductor Group
SPT03787
36
1998-10-01
HYB 39S16320TQ-6/-7/-8
4.2. Minimum Read to Write Interval
(Burst Length = 4, CAS latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Write latency t DQW of DQMx
DQMx
t DQZ
1 Clk Interval
Command
NOP
Bank A
Activate
NOP
NOP
Read A
Write A
NOP
NOP
NOP
DIN A0
DIN A1
DIN A2
DIN A3
Must be Hi-Z before
the Write Command
CAS
latency = 2
t CK2 , DQ’s
"H" or "L"
Semiconductor Group
SPT03413
37
1998-10-01
HYB 39S16320TQ-6/-7/-8
4.3. Non-Minimum Read to Write Interval
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Write latency t DQW of DQMx
DQMx
t DQZ
Command
NOP
Read A
NOP
NOP
Read A
NOP
Write B
NOP
NOP
Must be Hi-Z before
the Write Command
CAS
latency = 2
t CK2 , DQ’s
DOUT A0 DOUT A1
DIN B0
DIN B1
DIN B2
CAS
latency = 3
t CK3 , DQ’s
DOUT A0
DIN B0
DIN B1
DIN B2
"H" or "L"
Semiconductor Group
SPT03714
38
1998-10-01
HYB 39S16320TQ-6/-7/-8
4.4. Single Bit Write Cycle
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
NOP
NOP
Write B
NOP
NOP
NOP
NOP
DIN B1
DIN B2
DIN B3
CLK
DSF
Command
NOP
Bank Activ.
DQ’s
DIN B0
SPT03715
Bank Activate
with Write per Bit Enable
Burst Write
"H" or "L"
Semiconductor Group
39
1998-10-01
HYB 39S16320TQ-6/-7/-8
5. Burst Write Operation
5.1. Burst Write
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
NOP
Write A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DIN A0
DIN A1
DIN A2
DIN A3
don’t care
CLK
Command
DQ’s
The first data element and the Write
are registered on the same clock edge.
Semiconductor Group
Extra data is ignored after
termination of a Burst.
40
SPT03790
1998-10-01
HYB 39S16320TQ-6/-7/-8
5.2. Load Mode Register and Block Write Cycle
(Burst Length = 8, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t RSC
t RCD
t BWC
DSF
Command
LMR
NOP
ACT
NOP
DQx
NOP
Block Write
NOP
Block Write
Column
Mask
Column
Mask
Block Write
with Color Reg. 0
Block Write
with Color Reg. 1
A0
Load Mode Register
Burst Length set
Both Banks must be idle
Bank Activate
"H" or "L"
Semiconductor Group
SPT03716
41
1998-10-01
HYB 39S16320TQ-6/-7/-8
5.3. Read and DQM Function
(Burst Length = 4, CAS latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
NOP
Read
NOP
NOP
NOP
NOP
NOP
NOP
Data 2
Data 3
T8
CLK
Command
t DQZ
DQ 7...0
Data 0
DQM0
DQ 15...8
Data 0
Data 1
Data 3
DQM1
DQ 23...16
Data 1
Data 2
Data 1
Data 2
Data 3
DQM2
DQ 31...24
Data 0
DQM3
SPT03717
Semiconductor Group
42
1998-10-01
HYB 39S16320TQ-6/-7/-8
5.4. Write and DQM Function
(Burst Length = 4, CAS latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
NOP
NOP
NOP
Write
NOP
NOP
NOP
NOP
Data 2
Data 3
CLK
Command
DQ 7...0
Data 0
DQM0
DQ 15...8
Data 0
Data 1
Data 3
DQM1
DQ 23...16
Data 1
Data 2
Data 1
Data 2
Data 3
DQM2
DQ 31...24
Data 0
DQM3
SPT03718
Semiconductor Group
43
1998-10-01
HYB 39S16320TQ-6/-7/-8
6. Write and Read Interrupt
6.1. Write Interrupted by a Write
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
NOP
Write A
Write B
NOP
NOP
NOP
NOP
NOP
NOP
DIN B1
DIN B2
DIN B3
CLK
Command
1 Clk Interval
DQ’s
DIN A0
DIN B0
SPT03791
6.2. Write Interrupted by a Read
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
NOP
Write A
Read B
NOP
NOP
NOP
NOP
NOP
NOP
CLK
Command
CAS
latency = 2
t CK2 , DQ’s
DIN A0
don’t care
CAS
latency = 3
t CK3 , DQ’s
DIN A0
don’t care
DOUT B0 DOUT B1 DOUT B2 DOUT B3
don’t care
DOUT B0 DOUT B1 DOUT B2 DOUT B3
Input data must be removed from the DQ’s
at least one clock cycle before the Read data
appears on the outputs to avoid data contention.
Input data for the Write is ignored.
SPT03719
Semiconductor Group
44
1998-10-01
HYB 39S16320TQ-6/-7/-8
7. Burst Write and Read with Auto Precharge
7.1. Burst Write with Auto Precharge
(Burst Length = 2, CAS latency = 2, 3)
T0
T1
T2
T3
Bank A
Active
NOP
NOP
T4
T5
T6
T7
T8
NOP
NOP
NOP
NOP
NOP
CLK
Command
Write A
Auto Precharge
t WR
CAS
latency = 2
DQ’s
DIN A0
t RP
DIN A1
t WR
CAS
latency = 3
DQ’s
DIN A0
t RP
DIN A1
Begin Auto Precharge
Bank can be reactivated after t RP
SPT03720
7.2. Burst Read with Auto Precharge
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
Read A
with AP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CLK
Command
t RP
CAS
latency = 2
t CK2 , DQ’s
CAS
latency = 3
t CK3 , DQ’s
DOUT A0 DOUT A1 DOUT A2 DOUT A3
t RP
DOUT A0 DOUT A1 DOUT A2 DOUT A3
Begin Auto Precharge
Bank can be reactivated after t RP
Semiconductor Group
45
SPT03721
1998-10-01
HYB 39S16320TQ-6/-7/-8
8. Burst Termination
8.1. Termination of a Full Page Burst Read Operation
(CAS latency = 2, 3)
T0
T1
T2
T3
Read A
NOP
NOP
NOP
T4
T5
T6
T7
T8
NOP
NOP
NOP
NOP
CLK
Command
CAS
latency = 2
t CK2 , DQ’s
Burst
Terminate
DOUT A0 DOUT A1 DOUT A2 DOUT A3
CAS
latency = 3
t CK3 , DQ’s
DOUT A0 DOUT A1 DOUT A2 DOUT A3
The burst ends after a delay equal to the CAS latency.
SPT03722
8.2. Termination of a Full Page Burst Write Operation
(CAS latency = 2, 3)
T0
T1
T2
T3
T4
NOP
Write A
NOP
NOP
Burst
Terminate
DIN A0
DIN A1
DIN A2
don’t care
T5
T6
T7
T8
NOP
NOP
NOP
NOP
CLK
Command
CAS
latency = 2, 3
DQ’s
Input data for the Write is masked.
Semiconductor Group
46
SPT03419
1998-10-01
HYB 39S16320TQ-6/-7/-8
9. AC Parameters
9.1. AC Parameters for a Write Timing
Burst Length = 4, CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CH
t CK2
t CL
CKE
t CKS
Begin Auto
Precharge
Bank A
t CS
t CH
t CKH
Begin Auto
Precharge
Bank B
CS
RAS
CAS
WE
BA
t AH
A8/AP
RAx
RBx
RAy
RAz
t AS
Addr.
RAx
CAx
RBx
CBx
RAy
RAy
RAz
DQMx
t DS
t RCD
DQ
Hi-Z
Ax0 Ax1 Ax2 Ax3
Activate
Command
Bank A
Write with
Activate
Auto Precharge Command
Command
Bank B
Bank A
Semiconductor Group
t WR
t DH
t RC
Bx0 Bx1 Bx2 Bx3
Activate
Write with
Auto Precharge Command
Bank A
Command
Bank B
47
t RP
Ay0 Ay1 Ay2 Ay3
Write
Command
Bank A
Precharge
Command
Bank A
Activate
Command
Bank A
SPT03723
1998-10-01
HYB 39S16320TQ-6/-7/-8
9.2. AC Parameters for a Read Timing
y
Burst Length = 2, CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
CLK
t CH
t CK2
t CL
CKE
t CKH
t CS
Begin Auto
Precharge
Bank A
t CKS
t CH
Begin Auto
Precharge
Bank B
CS
RAS
CAS
WE
BA
t AH
RAx
A8/AP
RBx
RAy
t AS
RAx
Addr.
CAx
RBx
RBx
RAy
t RRD
t RAS
t RC
DQMx
t AC2
t LZ
t OH
t RCD
DQ
t HZ
Hi-Z
t AC2
Ax0
Activate
Command
Bank A
Semiconductor Group
Read with
Auto Precharge
Command
Bank A
Activate
Command
Bank B
48
t HZ
Ax1
Bx0
Read with
Auto Precharge
Command
Bank B
Bx1
Activate
Command
Bank A
SPT03724
1998-10-01
HYB 39S16320TQ-6/-7/-8
10. Mode Register Set
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t RSC
CS
RAS
CAS
WE
DSF
A8/AP
Address Key
A0-A7
Precharge
Command
All Banks
Any
Command
Mode Register
Set Command
Semiconductor Group
SPT03725
49
1998-10-01
HYB 39S16320TQ-6/-7/-8
11. Power on Sequence and Auto Refresh (CBR)
T2
T3
T4
T5
CKE
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
~
~
~
~
~
~
CLK
T1
~
~
T0
High Level
is required
2 Clock min.
~
~
~
~
Minimum of 8 Refresh Cycles are required
~
~ ~
~
~
~
~ ~
~
~
A8/AP
~
~
BA
~ ~
~
~
~
~ ~
~
WE
~
~ ~
~
~
~ ~
~
CAS
~
~ ~
~
~
~
~ ~
RAS
~
~
~
~
CS
~
~ ~
~
Addr.
~ ~
~
~
~
~
~
~
Address Key
DQMx
~
~
DQ
t RC
~
~
t RP
Hi-Z
Precharge
Command
All Banks
1st Auto Refresh
Command
2nd Auto Refresh
Command
Inputs must be
stable for 200 µs
Semiconductor Group
Mode Register
Set Command
Any
Command
SPT03726
50
1998-10-01
HYB 39S16320TQ-6/-7/-8
12. Clock Suspension (Using CKE)
12.1. Clock Suspension During Burst Read CAS Latency = 2
Burst Length = 4, CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK2
CKE
CS
RAS
CAS
WE
BA
A8/AP
RAx
Addr.
RAx
CAx
DQMx
t CSL
t CSL
DQ
Hi-Z
Activate
Command
Bank A
Ax0
Read
Command
Bank A
Semiconductor Group
t HZ
t CSL
Ax1
Ax2
Ax3
Clock
Suspend
1 Cycle
Clock
Suspend
2 Cycles
Clock
Suspend
3 Cycles
51
SPT03727
1998-10-01
HYB 39S16320TQ-6/-7/-8
12.2. Clock Suspension During Burst Read CAS Latency = 3
Burst Length = 4, CAS Latency = 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK3
CKE
CS
RAS
CAS
WE
BA
A8/AP
RAx
Addr.
RAx
CAx
t CSL
t CSL
DQMx
t CSL
t HZ
DQ
Hi-Z
Ax0
Activate
Command
Bank A
Semiconductor Group
Read
Command
Bank A
Ax1
Ax2
Ax3
Clock
Suspend
1 Cycle
Clock
Suspend
2 Cycles
Clock
Suspend
3 Cycles
52
SPT03425
1998-10-01
HYB 39S16320TQ-6/-7/-8
12.3. Clock Suspension During Burst Write CAS Latency = 2
Burst Length = 4, CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK2
CKE
CS
RAS
CAS
WE
BA
A8/AP
RAx
Addr.
RAx
CAx
DQMx
DQ
Hi-Z
DAx0
Activate
Command
Bank A
DAx1
Clock
Suspend
1 Cycle
DAx2
Clock
Suspend
2 Cycles
DAx3
Clock
Suspend
3 Cycles
Write
Command
Bank A
Semiconductor Group
SPT03728
53
1998-10-01
HYB 39S16320TQ-6/-7/-8
12.4. Clock Suspension During Burst Write CAS Latency = 3
Burst Length = 4, CAS Latency = 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK3
CKE
CS
RAS
CAS
WE
BA
A8/AP
RAx
Addr.
RAx
CAx
DQMx
DQ
Hi-Z
DAx0
Activate
Command
Bank A
DAx1
Clock
Suspend
1 Cycle
DAx2
Clock
Suspend
2 Cycles
DAx3
Clock
Suspend
3 Cycles
Write
Command
Bank A
Semiconductor Group
SPT03427
54
1998-10-01
HYB 39S16320TQ-6/-7/-8
13. Power Down Mode and Clock Suspend
Burst Length = 4, CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK2
CKE
CS
RAS
CAS
WE
BA
A8/AP
RAx
Addr.
RAx
CAx
DQMx
t HZ
DQ
Hi-Z
Ax0 Ax1
Activate
Command
Bank A
Active
Standby
Clock Suspend
Mode Entry
Read
Command
Bank A
Ax2
Clock Mask
Start
Clock Mask
End
Clock Suspend
Mode Exit
Ax3
Precharge
Command
Bank A
Precharge
Standby
Power Down
Mode Entry
Any
Command
Power Down
Mode Exit
SPT03938
Semiconductor Group
55
1998-10-01
HYB 39S16320TQ-6/-7/-8
14. Self Refresh (Entry and Exit)
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
~
~
T0
~
~
CLK
~
~
CKE
t CKS
~
~
t CKH
~
~ ~
~
CS
~
~ ~
~
RAS
~
~ ~
~
CAS
~
~ ~
~
WE
~
~ ~
~
BA
~
~ ~
~
A8/AP
~
~
Addr.
~
~
t RC
Hi-Z
All Banks
must be idle
~
~
DQ
t SREX
t SB
DQMx
Self Refresh
Entry
Begin Self Refresh
Exit Command
Self Refresh Exit
Command issued
Any
Command
Self Refresh
Exit
SPT03429
Semiconductor Group
56
1998-10-01
HYB 39S16320TQ-6/-7/-8
15. Auto Refresh (CBR)
Burst Length = 4, CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK2
CKE
CS
RAS
CAS
WE
BA
A8/AP
RAx
Addr.
RAx
t RP
t RC
(Minimum Interval)
CAx
t RC
DQMx
DQ
Hi-Z
Precharge
Command
All Banks
Ax0 Ax1 Ax2 Ax3
Auto Refresh
Command
Auto Refresh
Command
Activate
Command
Bank A
Read
Command
Bank A
SPT03729
Semiconductor Group
57
1998-10-01
HYB 39S16320TQ-6/-7/-8
16. Random Column Read (Page within same Bank)
16.1. CAS Latency = 2
Burst Length = 4, CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK2
CKE
CS
RAS
CAS
WE
BA
A8/AP
RAw
Addr.
RAw
RAz
CAw
CAx
CAy
RAz
CAz
DQMx
DQ
Hi-Z
Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3
Activate
Command
Bank A
Semiconductor Group
Read
Command
Bank A
Read
Command
Bank A
Read
Command
Bank A
58
Precharge
Command
Bank A
Az0 Az1
Activate
Command
Bank A
Read
Command
Bank A
SPT03730
1998-10-01
HYB 39S16320TQ-6/-7/-8
16.2. CAS Latency = 3
Burst Length = 4, CAS Latency = 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK3
CKE
CS
RAS
CAS
WE
BA
A8/AP
RAw
Addr.
RAw
RAz
CAw
CAx
CAy
RAz
CAz
Activate
Command
Bank A
Read
Command
Bank A
DQMx
DQ
Hi-Z
Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3
Activate
Command
Bank A
Read
Command
Bank A
Read
Command
Bank A
Read
Command
Bank A
Precharge
Command
Bank A
SPT03432
Semiconductor Group
59
1998-10-01
HYB 39S16320TQ-6/-7/-8
17. Random Column Write (Page within same Bank)
17.1. CAS Latency = 2
Burst Length = 4, CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK2
CKE
CS
RAS
CAS
WE
BA
A8/AP
RBz
Addr.
RBz
RBz
CBz
CBx
CBy
RBz
CBz
DQMx
DQ
Hi-Z
DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3
Activate
Command
Bank B
Semiconductor Group
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
60
Precharge
Command
Bank B
DBz0 DBz1 DBz2 DBz3
Activate
Command
Bank B
Write
Command
Bank B
SPT03731
1998-10-01
HYB 39S16320TQ-6/-7/-8
17.2. CAS Latency = 3
Burst Length = 4, CAS Latency = 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK3
CKE
CS
RAS
CAS
WE
BA
A8/AP
RBz
Addr.
RBz
RBz
CBz
CBx
CBy
RBz
CBz
DQMx
DQ
Hi-Z
DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3
Activate
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
DBz0 DBz1
Precharge
Command
Bank B
Activate
Command
Bank B
Write
Command
Bank B
SPT03434
Semiconductor Group
61
1998-10-01
HYB 39S16320TQ-6/-7/-8
18. Random Row Read (Interleaving Banks) with Precharge
18.1. CAS Latency = 2
Burst Length = 8, CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK2
CKE
High
CS
RAS
CAS
WE
BA
A8/AP
RBx
Addr.
RBx
RAx
CBx
RAx
RBy
CAx
RBy
t RCD
CBy
t RP
DQMx
t AC2
DQ
Hi-Z
Activate
Command
Bank B
Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3 Ax4 Ax5 Ax6 Ax7
Read
Command
Bank B
Activate
Command
Bank A
Precharge
Command
Bank B
Read
Command
Bank A
Semiconductor Group
62
Activate
Command
Bank B
By0 By1
Read
Command
Bank B
SPT03732
1998-10-01
HYB 39S16320TQ-6/-7/-8
18.2. CAS Latency = 3
Burst Length = 8, CAS Latency = 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK3
CKE
High
CS
RAS
CAS
WE
BA
A8/AP
RBx
Addr.
RBx
RAx
CBx
RBy
RAx
CAx
RBy
t AC3
t RCD
CBy
t RP
DQMx
DQ
Hi-Z
Activate
Command
Bank B
Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3 Ax4 Ax5 Ax6 Ax7 By0
Read
Command
Bank B
Activate
Command
Bank A
Read
Command
Bank A
Precharge
Command
Bank B
Activate
Command
Bank B
Read
Command
Bank B
Precharge
Command
Bank A
SPT03436
Semiconductor Group
63
1998-10-01
HYB 39S16320TQ-6/-7/-8
19. Random Row Write (Interleaving Banks) with Precharge
19.1. CAS Latency = 2
Burst Length = 8, CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK2
CKE
High
CS
RAS
CAS
WE
BA
A8/AP
RAx
Addr.
RAx
RBx
CAx
RAy
RBx
t RCD
CBx
RAy
t WR
t RP
CAy
t WR
DQMx
DQ
Hi-Z
Activate
Command
Bank A
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3 DAy4
Write
Command
Bank A
Activate
Command
Bank B
Write
Command
Bank B
Precharge
Command
Bank A
Semiconductor Group
64
Activate
Command
Bank A
Precharge
Command
Bank B
Write
Command
Bank A
SPT03733
1998-10-01
HYB 39S16320TQ-6/-7/-8
19.2. CAS Latency = 3
Burst Length = 8, CAS Latency = 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK3
CKE
High
CS
RAS
CAS
WE
BA
A8/AP
RAx
Addr.
RAx
RBx
CAx
RBx
RAy
CBx
t RCD
RAy
t WR
t RP
CAy
t WR
DQMx
DQ
Hi-Z
Activate
Command
Bank A
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3
Write
Command
Bank A
Activate
Command
Bank B
Write
Command
Bank B
Precharge
Command
Bank A
Activate
Command
Bank A
Write
Command
Bank A
Precharge
Command
Bank B
SPT03438
Semiconductor Group
65
1998-10-01
HYB 39S16320TQ-6/-7/-8
20. Full Page Read Cycle
20.1. CAS Latency = 2
Burst Length = Full Page, CAS Latency = 2
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
~
~
T0
~
~
CLK
~
~
t CK2
High
~
~
CKE
~
~
CS
~
~ ~
~
RAS
~
~ ~
~
CAS
~
~ ~
~
WE
~
~ ~
~
BA
RAx
Addr.
RAx
RBy
RBx
~
~ ~
~
A8/AP
RBx
CBx
RBy
~
~
CAx
t RP
Hi-Z
Ax Ax +1 Ax + 2 Ax - 2
~
~
DQ
~ ~
~
~
DQMx
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank B
Ax -1
Ax+1 Bx
Read
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval.
Semiconductor Group
Ax
Bx+1 Bx+2 Bx + 3 Bx+ 4 Bx+ 5 Bx + 6
Burst Stop Precharge
Command Command
Bank B
Full Page burst operation does not
terminate when the burst length is satisfied;
the burst counter increments and continues
bursting beginning with the starting address.
66
Activate
Command
Bank B
SPT03734
1998-10-01
HYB 39S16320TQ-6/-7/-8
20.2. CAS Latency = 3
Burst Length = Full Page, CAS Latency = 3
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
~
~
T0
~
~
CLK
~
~
t CK3
High
~
~
CKE
~
~
CS
~ ~
~
~
RAS
~ ~
~
~
CAS
~ ~
~
~
WE
~ ~
~
~
BA
RAx
Addr.
RAx
RBx
RBy
~ ~
~
~
A8/AP
RBx
CBx
RBy
~
~
CAx
t RP
Hi-Z
Ax
Activate
Command
Bank A
Activate
Command
Bank B
Read
Command
Bank A
Semiconductor Group
Ax +1 Ax+ 2 Ax - 2
~
~
DQ
~ ~
~
~
DQMx
Ax -1
Ax
Read
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval.
67
Ax +1 Bx
Bx +1 Bx +2 Bx + 3 Bx+ 4 Bx + 5
Burst Stop Precharge
Command Command
Bank B
Full Page burst operation does not
terminate when the burst length is satisfied;
the burst counter increments and continues
bursting beginning with the starting address.
Activate
Command
Bank B
SPT03440
1998-10-01
HYB 39S16320TQ-6/-7/-8
21. Full Page Write Cycle
21.1. CAS Latency = 2
Burst Length = Full Page, CAS Latency = 2
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
~
~
T0
~
~
CLK
~
~
t CK2
High
~
~
CKE
~
~
CS
~
~
~ ~
RAS
~
~
~ ~
CAS
~
~ ~
~
WE
~
~
~ ~
BA
RAx
Addr.
RAx
RBx
RBx
RBy
CBx
~
~
CAx
DAx DAx+1 DAx+2 DAx+3 DAx- 1 DAx DAx+1 DBx DBx+1 DBx+2 DBx+ 3 DBx+ 4 DBx+ 5 DBx+6
~
~
Hi-Z
~ ~
~
~
DQMx
DQ
RBy
~
~
~ ~
A8/AP
Activate
Command
Bank A
Write
Command
Bank A
Activate
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval.
Semiconductor Group
Write
Command
Bank B
Data is
ignored.
Full Page burst operation does not
terminate when the burst length is satisfied;
the burst counter increments and continues
bursting beginning with the starting address.
68
Burst Stop
Command
Activate
Command
Bank B
Precharge
Command
Bank B
SPT03735
1998-10-01
HYB 39S16320TQ-6/-7/-8
21.2. CAS Latency = 3
Burst Length = Full Page, CAS Latency = 3
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
~
~
T0
~
~
CLK
~
~
t CK3
High
~
~
CKE
~
~
CS
~
~ ~
~
RAS
~
~ ~
~
CAS
~
~ ~
~
WE
~
~ ~
~
BA
RAx
Addr.
RAx
RBx
RBx
CBx
RBy
~
~
CAx
DAx DAx+ 1 DAx+ 2 DAx+ 3 DAx- 1 DAx DAx+ 1 DBx DBx+ 1 DBx+ 2 DBx+ 3 DBx+ 4 DBx+ 5
~
~
Hi-Z
~
~ ~
~
DQMx
DQ
RBy
~
~ ~
~
A8/AP
Activate
Command
Bank B
Activate
Command
Bank A
Write
Command
Bank B
Data is
ignored.
Burst Stop
Command
Write
Command
Bank A
Precharge
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval.
Semiconductor Group
Activate
Command
Bank B
Full Page burst operation does not
terminate when the burst length is satisfied;
the burst counter increments and continues
bursting beginning with the starting address.
69
SPT03442
1998-10-01
HYB 39S16320TQ-6/-7/-8
22. Precharge Termination of a Burst
22.1. CAS Latency = 2
Burst Length = 8 or Full Page, CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK2
CKE
High
CS
RAS
CAS
WE
BA
A8/AP
RAx
Addr.
RAx
RAy
CAx
RAy
RAz
CAy
t RP
RAz
CAz
Activate
Command
Bank A
Read
Command
Bank A
t RP
DQMx
DQ
Hi-Z
Activate
Command
Bank A
DAx0 DAx1 DAx2 DAx3
Write
Command
Bank A
Precharge
Command
Bank A
Ay0 Ay1 Ay2
Activate
Command
Bank A
Precharge Termination
of a Write Burst.
Write Data is masked.
Read
Command
Bank A
Precharge
Command
Bank A
Precharge Termination
of a Read Burst.
SPT03736
Semiconductor Group
70
1998-10-01