Agilent HDMP-0450 Quad Port Bypass Circuit for Fibre Channel Arbitrated Loops Data Sheet Description The HDMP-0450 is a Quad Port Bypass Circuit (PBC) which provides a low-cost, low-power physical-layer solution for Fibre Channel Arbitrated Loop (FC-AL) disk array configurations. By using a PBC such as the HDMP-0450, hard disks may be pulled out or swapped while other disks in the array are available to the system. A PBC consists of multiple 2:1 multiplexers daisy chained together. Each port has two modes of operation: “disk in loop” and “disk bypassed.” When the “disk in loop” mode is selected, the loop goes into and out of the disk drive at that port. For example, data goes from the HDMP-0450’s TO_NODE[n]± differential output pins to the Disk Drive Transceiver IC’s (e.g., an HDMP-1636A) Rx differential input pins. Data from the Disk Drive Transceiver IC’s Tx differential outputs goes to the HDMP-0450’s FM_NODE[n]± differential input pins. Figure 2 shows connection diagrams for disk drive array applications. When the “disk bypassed” mode is selected, the disk drive is either absent or nonfunctional and the loop bypasses the hard disk. The “disk bypassed” mode is enabled by pulling the BYPASS[n]pin low. Leave BYPASS[n]floating to enable the “disk in loop” mode. HDMP-0450s may be cascaded with other members of the HDMP-04XX/HDMP-05XX family through the appropriate FM_NODE[n]± and TO_NODE[n]± pins to accommodate any number of hard disks (see Figure 3). The unused cells in the HDMP-0450 may be bypassed by using pulldown resistors on the BYPASS[n]- pins for these cells. An HDMP-0450 may also be configured as five 1:1 buffers, as two 2:1 multiplexers, or as two 1:2 buffers. Features • Supports 1.0625 GBd Fibre Channel operation • Supports 1.25 GBd Gigabit Ethernet (GE) operation • Quad PBC in one package • Signal detect on FM_NODE[0] input • Equalizers on all inputs • High speed LVPECL I/O • Buffered Line Logic (BLL) outputs (no external bias resistors required) • 0.5 W typical power at VCC = 3.3 V • 44 Pin, 10 mm, low-cost plastic QFP package Applications • RAID, JBOD, BTS cabinets • Two 2:1 muxes • Two 1:2 buffers • 1 => N gigabit serial buffer • N => 1 gigabit serial mux HDMP-0450 CAUTION: As with all semiconductor ICs, it is advised that normal static precautions be taken in the handling and assembly of this component to prevent damage and/or degradation which may be induced by electrostatic discharge (ESD). BYPASS[0]– TTL FM_NODE[0] EQU TO_NODE[0] BYPASS[4]– TTL FM_NODE[4] EQU TO_NODE[4] BYPASS[3]– TTL FM_NODE[3] BYPASS[2]– EQU TO_NODE[3] FM_NODE[2] BYPASS[1]– TTL TO_NODE[2] FM_NODE[1] TO_NODE[1] EQU EQU TTL SD BLL BLL BLL BLL TTL SD BLL 1 1 1 1 1 0 0 0 0 0 Figure 1. Block diagram of HDMP-0450. HDMP-0450 Block Diagram BLL OUTPUT All TO_NODE[n]± high-speed differential outputs are driven by a Buffered Line Logic (BLL) circuit that has on-chip source termination, so no external bias resistors are required. The BLL outputs on the HDMP-0450 are of equal strength and can drive in lengthy FR-4 PCB trace. Unused outputs should not be left unconnected. Ideally, unused outputs should have their differential pins shorted together with a short PCB trace. If longer traces or transmission lines are connected to the output pins, the lines should be differentially terminated with an appropriate resistor. The value of the termination resistor should match the PCB trace differential impedance. 2 EQU INPUT All FM_NODE[n]± high-speed differential inputs have an Equalization (EQU) buffer to offset the effects of skin loss and dispersion on PCBs. An external termination resistor is required across all high-speed inputs. The value of the termination resistor should match the PCB trace differential impedance. Alternatively, instead of a single resistor, two resistors in series, with an AC ground between them, can be connected differentially across the FM_NODE[n]± inputs. The latter configuration attenuates high-frequency common mode noise. BYPASS[n]- INPUT The active low BYPASS[n]- inputs control the data flow through the HDMP-0450. All BYPASS pins are LVTTL and contain internal pullup circuitry. To bypass a port, the appropriate BYPASS[n]- pin should be connected to GND through a 1 kΩ resistor. Otherwise, the BYPASS[n]-inputs should be left to float, as the internal pull-up circuitry will force them high. SD OUTPUT The Signal Detect (SD) block detects if the incoming data on FM_NODE[0]± is valid by examining the differential amplitude of that input. The incoming data is considered valid, and SD is driven high, as long as the amplitude is greater than 400 mV (differential peak-topeak). SD is driven low as long as the amplitude of the input signal is less than 100 mV (differential peak-to-peak). When the amplitude of the input signal is between 100-400 mV (differential peak-to-peak), the SD output is undefined. 3 EQU BLL 1 0 TTL EQU 1 BLL 2 0 TTL BLL EQU 1 3 0 TTL 1 HARD DISK A HARD DISK B HARD DISK C HARD DISK D SERDES SERDES SERDES SERDES BLL EQU TTL 4 0 Figure 3. Connection diagram for multiple HDMP-0450s. EQU 1 BLL TTL 0 0 EQU 1 BLL 1 0 1 0 TTL EQU 1 TTL BLL 2 0 EQU 4 1 0 TTL BLL EQU 1 TTL BLL 3 0 EQU 1 TTL 4 0 EQU 1 BYPASS[0] EQU TO_NODE[0] BLL FM_NODE[0] SERDES BYPASS[4]– SERDES FM_NODE[4] SERDES TO_NODE[4] SERDES BYPASS[0]– = HIGH (FLOAT) FM_NODE[0] = FM_LOOP TO_NODE[0] = TO_LOOP HARD DISK D BYPASS[3]– BYPASS[4]– FM_NODE[4] HARD DISK C FM_NODE[3] 0 TO_NODE[4] BYPASS[3]– FM_NODE[3] TO_NODE[3] BYPASS[2]– FM_NODE[2] TO_NODE[2] BYPASS[1]– FM_NODE[1] TO_NODE[1] HARD DISK B TO_NODE[3] 3 BYPASS[2]– TTL FM_NODE[2] 1 TO_NODE[2] BLL BYPASS[1]– = HIGH (FLOAT) 2 FM_NODE[1] EQU TO_NODE[1] = TO_LOOP TTL BYPASS[0]– = HIGH (FLOAT) BLL FM_NODE[0] = FM_LOOP 0 TO_NODE[0] 1 BYPASS[4]– 1 FM_NODE[4] EQU TO_NODE[4] TTL BYPASS[3]– FM_NODE[3] BLL TO_NODE[3] BYPASS[2]– EQU FM_NODE[2] TO_NODE[2] BYPASS[1]– FM_NODE[1] TO_NODE[1] HARD DISK A BLL TTL 0 1 0 Figure 2. Connection diagram for Disk Array applications. HARD DISK E HARD DISK F HARD DISK G HARD DISK H SERDES SERDES SERDES SERDES BLL TTL 0 1 0 I/O Type Definitions I/O Type Definition I-LVTTL LVTTL Input O-LVTTL LVTTL Output HS_OUT High Speed Output. LVPECL Compatible HS_IN High Speed Input C External Circuit Note S Power Supply or Ground Pin Definitions Pin Name Pin Pin Type Pin Description TO_NODE[0]+ TO_NODE[0]– TO_NODE[1]+ TO_NODE[1]– TO_NODE[2]+ TO_NODE[2]– TO_NODE[3]+ TO_NODE[3]– TO_NODE[4]+ TO_NODE[4]– 24 25 07 06 44 43 38 37 31 30 HS_OUT Serial Data Outputs: High-speed outputs to a hard disk drive or to a cable. FM_NODE[0]+ FM_NODE[0]– FM_NODE[1]+ FM_NODE[1]– FM_NODE[2]+ FM_NODE[2]– FM_NODE[3]+ FM_NODE[3]– FM_NODE[4]+ FM_NODE[4]– 10 09 04 03 41 40 35 34 28 27 HS_IN Serial Data Inputs: High-speed inputs from a hard disk drive or from a cable. BYPASS[0]– BYPASS[1]– BYPASS[2]– BYPASS[3]– BYPASS[4]– 14 15 16 17 18 I-LVTTL Bypass Inputs: For “disk bypassed” mode, connect BYPASS[n]– to GND through a 1 kΩ resistor. For “disk in loop” mode, float HIGH. SD 20 O-LVTTL Signal Detect: Indicates acceptable signal amplitude on the FM_NODE[0]± inputs. If (FM_NODE[0]+ – FM_NODE[0]–) >= 400 mV peak-to-peak, SD = 1 If 400 mV > (FM_NODE[0]+ – FM_NODE[0]–) > 100 mV, SD = undefined If 100 mV >= (FM_NODE[0]+ – FM_NODE[0]–), SD = 0 4 Pin Definitions, continued GND 01 08 11 12 13 19 22 23 33 39 S Ground: Normally 0 volts. See Figure 9 for Recommended Power Supply Filtering. VCCHS[0] VCCHS[1] VCCHS[2] VCCHS[3] VCCHS[4] 26 05 42 36 29 S S S S S High Speed Supply: Normally 3.3 volts. Used only for high-speed outputs (TO_NODE[n]). See Figure 9 for Recommended Power Supply Filtering. VCC 02 21 32 S Logic Power Supply: Normally 3.3 volts. Used for internal logic. See Figure 9 for Recommended Power Supply Filtering. Absolute Maximum Ratings TA = 25°C, except as specified. Operation in excess of any of these conditions may result in permanent damage to this device. Continuous operation at these minimum or maximum ratings is not recommended. Symbol Parameter Units Min. Max. VCC Supply Voltage V –0.5 4.0 VIN,LVTTL LVTTL Input Voltage V –0.5 VCC + 0.5 [1] VIN,HS_IN HS_IN Input Voltage (Differential) mV 200 2000 IO,LVTTL LVTTL Output Sink/Source Current mA Tstg Storage Temperature °C –65 +150 Tj Junction Temperature °C 0 +125 ±13 Note: 1. Must remain less than or equal to absolute maximum VCC voltage of 4.0 V. DC Electrical Specifications VCC = 3.15 V to 3.45 V Symbol Parameter Units Min. VIH,LVTTL LVTTL Input High Voltage Range V 2.0 VIL,LVTTL LVTTL Input Low Voltage Range V VOH,LVTTL LVTTL Output High Voltage Range, IOH = –400 µA V 2.2 VCC VOL,LVTTL LVTTL Output Low Voltage Level, IOL = 1 mA V 0 0.6 IIH,LVTTL Input High Current (Magnitude), VIN = 2.4 V, VCC = 3.45 V µA 40 IIL,LVTTL Input Low Current (Magnitude), VIN = 0.4 V, VCC = 3.45 V µA –600 ICC Total Supply Current, TA = 25°C mA 5 Typ. Max. 0.8 150 185 AC Electrical Specifications VCC = 3.15 V to 3.45 V Symbol Parameter Units TLOOP_LAT Total Loop Latency from FM_NODE[0] to TO_NODE[0] ns 2.0 TCELL_LAT Per Cell Latency from FM_NODE[4] to TO_NODE[0] ns 0.8 tr,LVTTLin Input LVTTL Rise Time Requirement, 0.8 V to 2.0 V ns 2.0 tf,LVTTLin Input LVTTL Fall Time Requirement, 2.0 V to 0.8 V ns 2.0 tr,LVTTout Output TTL Rise Time, 0.8 V to 2.0 V, 10 pF Load ns 1.7 3.3 tf,LVTTout Output TTL Fall Time, 2.0 V to 0.8 V, 10 pF Load ns 1.7 2.4 trs,HS_OUT HS_OUT Single-Ended Rise Time, 20%-80% ps 200 300 tfs,HS_OUT HS_OUT Single-Ended Fall Time, 20%-80% ps 200 300 trd,HS_OUT HS_OUT Differential Rise Time, 20%-80% ps 200 300 tfd,HS_OUT HS_OUT Differential Fall Time, 20%-80% ps 200 300 VIP,HS_IN HS_IN Required Peak-to-Peak Differential Input Voltage mV 200 1200 2000 VOP,HS_OUT HS_OUT Peak-to-Peak Differential Output Voltage (Z0 = 75 Ω, Figure 6) mV 1100 1400 2000 Guaranteed Operating Rates VCC = 3.15 V to 3.45 V FC Serial Clock Rate (MBd) Min. Max. GE Serial Clock Rate (MBd) Min. Max. 1,040 1,240 1,080 Figure 4. Eye diagram of TO_NODE[1]± high speed differential output (50 Ω termination). Note: Measurement taken with a 2^7-1 PRBS input to FM_NODE[1]±. 6 1,260 Min. Typ. Max. Simplified I/O Cells O_LVTTL I_LVTTL VCC VCC VCC VBB 1.4 V GND GND ESD PROTECTION ESD PROTECTION GND Figure 5. O-LVTTL and I-LVTTL simplified circuit schematic. HS_OUT HS_IN VCC VCCHS 75 Ω + – VCC TO_NODE[n]+ + – VCC Z0 = 75 Ω 0.01 µF FM_NODE[n]+ 2*Z0 = 150 Ω TO_NODE[n]– Z0 = 75 Ω GND 0.01 µF FM_NODE[n]– GND ESD ESD PROTECTION PROTECTION GND GND NOTE: FM_NODE[n] INPUTS SHOULD NEVER BE CONNECTED TO GROUND AS PERMANENT DAMAGE TO THE DEVICE MAY RESULT. Figure 6. HS_OUT and HS_IN simplified circuit schematic. 7 Package Information Power Dissipation and Thermal Resistance VCC = 3.15 V to 3.45 V Symbol Parameter Units Typ. Max. PD Power Dissipation mW 500 640 θjc[1] Thermal Resistance, Junction to Case °C/W 7 Note: 1. Based on independent package testing by Agilent. θja for this device is 57°C/W. θ ja is measured on a standard 3x3” FR4 PCB in a still air environment. To determine the actual junction temperature in a given application, use the following equation: Tj = Tc + (θjc x PD), where Tc is the case temperature measured on the top center of the package and PD is the power being dissipated. Item Details Package Material Plastic Lead Finish Material 85% Tin, 15% Lead Lead Finish Thickness 200-800 micro-inches Lead Skew 0.33 mm max. Lead Coplanarity (Seating Plane) 0.10 mm max. Mechanical Dimensions PIN #1 ID 1 2 44 43 42 41 40 39 38 37 36 35 34 33 32 3 4 5 31 30 29 6 7 TOP VIEW E E1 28 27 26 8 9 25 10 24 11 23 12 13 14 15 16 17 18 19 20 21 22 D1 D A2 c A SEATING PLANE A1 b 0.25 GUAGE PLANE L e ALL DIMENSIONS ARE IN MILLIMETERS PART NUMBER E1/D1 HDMP-0450 TOLERANCE Figure 7. HDMP-0450 package drawing. 8 10.00 E/D b e L c A2 A1 A 13.20 0.35 0.80 0.88 0.23 2.00 0.25 2.45 ± 0.10 ± 0.20 ± 0.05 BASIC + 0.15/ MAX. + 0.10/ ± 0.25 – 0.10 – 0.05 MAX. FM_NODE[3]– FM_NODE[3]+ VCCHS[3] TO_NODE[3]– GND TO_NODE[3]+ FM_NODE[2]– FM_NODE[2]+ VCCHS[2] TO_NODE[2]– TO_NODE[2]+ Pin Diagram and Recommended Supply Filtering 44 43 42 41 40 39 38 37 36 35 34 GND 1 33 VCC 2 32 VCC FM_NODE [1]– 3 31 TO_NODE[4]+ FM_NODE [1]+ 4 30 TO_NODE[4]– VCCHS[1] 5 29 VCCHS[4] TO_NODE [1]– 6 28 FM_NODE[4]+ TO_NODE [1]+ 7 27 FM_NODE[4]– GND 8 26 VCCHS[0] FM_NODE [0]– 9 25 TO_NODE[0]– FM_NODE [0]+ 10 24 TO_NODE[0]+ GND 11 23 GND Agilent HDMP-0450 nnnn-nnn Rz.zz S YYWW GND nnnn-nnn = WAFER LOT – BUILD NUMBER Rz.zz = DIE REVISION S = SUPPLIER CODE YYWW = DATE CODE (YY = YEAR, WW = WORK WEEK) COUNTRY = COUNTRY OF MANUFACTURE (ON BACK SIDE) GND VCC SD GND BYPASS[4]– BYPASS[3]– BYPASS[2]– BYPASS[1]– BYPASS[0]– GND GND 12 13 14 15 16 17 18 19 20 21 22 VCC GND VCC Figure 8. HDMP-0450 package layout and marking, top view. 44 43 42 41 40 39 38 37 36 35 34 GND VCC VCC 1 33 2 32 3 31 4 30 5 GND VCC 10 µF VCC 29 HDMP-0450 6 GND GND 28 7 27 8 26 9 25 10 24 11 23 VCC GND GND VCC GND GND GND 12 13 14 15 16 17 18 19 20 21 22 Figure 9. Recommended power supply filtering. 9 CAPACITORS = 0.1 µF (EXCEPT WHERE NOTED). www.agilent.com/semiconductors For product information and a complete list of distributors, please go to our web site. For technical assistance call: Americas/Canada: +1 (800) 235-0312 or (408) 654-8675 Europe: +49 (0) 6441 92460 China: 10800 650 0017 Hong Kong: (+65) 6271 2451 India, Australia, New Zealand: (+65) 6271 2394 Japan: (+81 3) 3335-8152(Domestic/International), or 0120-61-1280(Domestic Only) Korea: (+65) 6271 2194 Malaysia, Singapore: (+65) 6271 2054 Taiwan: (+65) 6271 2654 Data subject to change. Copyright © 2002 Agilent Technologies, Inc. August 26, 2002 5988-7490EN