VML VG36128401BT

VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Description
The VG36128401B, VG36128801B and VG3664128161B are high-speed 134,217,728-bit synchronous dynamic random-access memories, organized as 8,388,608 x 4 x 4, 4,194,304 x 8 x 4 and 2,097,152 x
16 x 4 (word x bit x bank), respectively.
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture. All input
and outputs are synchronized with the positive edge of the clock.The synchronous DRAMs are compatible
with Low Voltage TTL (LVTTL).These products are packaged in 54-pin TSOPII.
Features
• Single 3.3V ( ± 0.3V ) power supply
• High speed clock cycle time -7H: 133MHz<2-2-2>, -7L: 133MHz<3-3-3>, -8H: 100MHz<2-2-2>
• Fully synchronous operation referenced to clock rising edge
• Possible to assert random column access in every cycle
• Quad internal banks controlled by BA0 & BA1 (Bank Select)
• Byte control by LDQM and UDQM for VG36128161DT
• Programmable Wrap sequence (Sequential / Interleave)
• Programmable burst length (1, 2, 4, 8 and full page)
• Programmable /CAS latency (2 and 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• X4, X8, X16 organization
• LVTTL compatible inputs and outputs
• 4,096 refresh cycles / 64ms
.
Document :1G5-0183
Rev.1
Page 1
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Pin Configurations
VG36128401 (x4)
VG36128801 (x8)
VG36128161 (x16)
VDD
VDD
VDDQ
DQ0
VDDQ
NC
DQ0
VSSQ
NC
DQ1
VSSQ
DQ0
VDDQ
DQ1
DQ2
VSSQ
VDD
NC
DQ3
NC
NC
DQ4
NC
DQ2
VDDQ
VDDQ
VDDQ
DQ5
NC
NC
DQ6
DQ1
DQ3
VSSQ
VSSQ
VSSQ
DQ7
NC
NC
VDD
VDD
VDD
NC
NC
LDQM
WE
/WE
WE
/CAS
/CAS
/CAS
/RAS
/RAS
/RAS
/CS
/CS
/CS
BA0(A13)
BA0(A13) BA0(A13)
BA1(A12) BA1(A12)
BA1(A12)
A10
A10
A10
A0
A0
A0
A1
A1
A1
A2
A2
A2
A3
A3
A3
VDD
VDD
VDD
Pin Descriptions
Pin Name
CLK
CKE
/CS
/RAS
1
54
VSS
VSS
VSS
2
53
3
52
4
51
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC
UDQM
CLK
CKE
NC
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
NC
VSSQ
NC
DQ3
VDDQ
NC
NC
VSSQ
NC
DQ4
VDDQ
NC
VSS
NC
DQM
CLK
CKE
NC
VSSQ
NC
DQ2
VDDQ
NC
VSS
NC
DQM
CLK
CKE
NC
5
50
6
49
7
8
48
9
46
10
11
45
44
12
43
13
42
47
14
41
15
40
16
39
17
38
18
37
19
36
20
35
A11
A11
A11
21
34
22
33
A9
A8
A7
A6
A5
A4
VSS
A9
A8
A7
A6
A5
A4
VSS
A9
A8
A7
A6
A5
A4
VSS
23
32
24
31
25
30
26
29
27
28
Function
Pin Name
Function
Master Clock
DQM
DQ Mask Enable
Clock Enable
A0-11
Address Input
Chip Select
BA0,1
Bank Address
Row Address Strobe
VDD
Power Supply
/CAS
Column Address Strobe
VDDQ
Power Supply for DQ
/WE
Write Enable
VSS
Ground
DQ0 ~ DQ15
Data I/O
VSSQ
Ground for DQ
Document :1G5-0183
Rev.1
Page 2
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Block Diagram
Address
CAS
WE
Document :1G5-0183
DQM
Column Decoder &
Latch Circuit
Column
Address
Buffer
&
Burst
Counter
Data Control Circuit
Rev.1
Input & Output
Buffer
RAS
Bank A
Sense Amplifier
Control Logic
CS
Command Decoder
Mode
Register
Bank D
Bank C
Bank B
Row
Address
Buffer
&
Refresh
Counter
Latch Circuit
CKE
Clock
Generator
Row Decoder
CLK
Page 3
DQ
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Pin Function
Symbol
Input
Function
CLK
Input
Maste Clock: Other inputs signals are referenecd to the CLK rising edge.
CKE
Input
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals,
device input buffers and output drivers. Deactivating the clock provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWERDOWN (row ACTIVE in any bank).
/CS
Input
Chip Select: /CS enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when /CS is registered HIGH. /CS provides
for external bank selection on systems with multiple banks. /CS is considered part of
the command code.
/RAS, /CAS,
/WE
Input
Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being
entered.
A0 - A13
Input
Address Inputs: Provide the row address for ACTIVE commands, and the column
address and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the respective bank.
The row address is specified by A0-A11.
The column address is specified by A0-A9, A11 (X4) / A0-A9 (X8) / A0-A8 (X16)
BA0,BA1
Input
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or
PRECHARGE command is being applied.
DQM, UDQM ,
LDQM
Input
Din Mask / Output Disable: When DQM is high in burst write, Din for the current cycle is
masked. When DQM is is high in burst read, Dout is disable at the next but one cycle.
DQ0 - DQ15
I/O
Data Input / Output: Data bus.
VDD, VSS
Supply Power Supply for the memory array and peripheral circuitry.
VDDQ, VSSQ
Supply Power Supply are supplied to the output buffers only.
Document :1G5-0183
Rev.1
Page 4
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Absolute Maximum Ratings
Parameter
Supply Voltage
Symbol
VDD
Supply Voltage for Output
VDDQ
Conditions
Value
Unit
with respect to V SS
-0.5 to 4.6
V
with respect to V SSQ
-0.5 to 4.6
V
Input Voltage
VI
with respect to V SS
-0.5 to 4.6
V
Output Voltage
VO
with respect to V SSQ
-0.5 to 4.6
V
Short circuit output current
IO
50
mA
Power dissipation
PD
1
W
Ta = 25 °C
Operating temperature
TOPT
0 to 70
°C
Storage temperature
TSTG
-65 to 150
°C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The
device is not meant to be operated under conditions outside the limits described in the operational section of this
specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions (Ta = 0 ~ 70 °C, unless otherwise noted)
Parameter
Limits
Symbol
Unit
Min.
Typ.
Max.
VDD
3.0
3.3
3.6
V
VDDQ
3.0
3.3
3.6
V
VSS
0
0
0
V
VSSQ
0
0
0
V
High Level Input Voltage (all inputs)
VIH
2.0
VDDQ + 0.3
V
Low Level Input Voltage (all inputs)
VIL
-0.3
0.8
V
Supply Voltage
Supply Voltage for DQ
Ground
Ground for DQ
Pin Capacitance (Ta = 0 ~ 70°C, VDD = VDDQ = 3.3 ± 0.3V , VSS = VSSQ = 0V, unless otherwise noted)
Parameter
Symbol
Limits (Min)
CIN
Input Capacitance, CLK pin
CCLK
Data input / output capacitance
CI/O
Input Capacitance, address & control pin
Document :1G5-0183
Rev.1
Limits (Max)
Unit
-7H
-7L/-8H
2.5
3.8
5.0
pF
2.5
3.5
4.0
pF
4.0
6.5
6.5
pF
Page 5
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
DC Characteristics 1
(Ta = 0 ~ 70°C, VDD = VDDQ = 3.3 ± 0.3V, VSS = VSSQ = 0V, Ouput Open, unless otherwise noted)
Parameter
Operating current
Symbol
ICC1
Precharge standby current ICC2P
in power down mode
ICC2PS
Precharge standby current ICC2N
in non power down mode
ICC2NS
Test Conditions
Organization
≤ VIL(MAX), tCK = 15ns
CKE ≤ VIL(MAX), CLK ≤ VIL(MAX)
CKE
CS ≥ V CC - 0.2V
tCK = 15ns, CKE
CKE ≥ V IH(MIN)
CS ≥ V CC - 0.2V
CKE
CLK ≤ VIL(MAX), CKE
CKE ≥ VVIH(MIN)
Unit Notes
x4
x8
x16
x4/x8/x16
2
2
2
x4/x8/x16
1
1
1
25
25
25
mA
x4/x8/x16
15
15
15
mA
x4/x8/x16
30
30
30
mA
x4/x8/x16
20
20
20
mA
x4
x8
x16
140
150
160
110
120
130
110
120
130
mA
x4/x8/x16
160
160
160
mA
x4/x8/x16
2
0.8
2
0.8
2
0.8
mA
mA
One bank active
tRC = tRC(MIN), tCLK = tCLK(MIN),
BL = 1, CL=3
CKE
Limits (max.)
-7L
-8H
95
95
100
100
120
120
-7H
100
110
130
x4/x8/x16
mA
1
mA
2
All input signals are stable.
Active standby current in
Nonpower down mode
ICC3N
CKE
CS
≥ V CC - 0.2V
CKE
tCK = 15ns, CKE
≥ V IH(MIN)
≥ V CC - 0.2V
CLK ≤ VIL(MAX), CKE
CKE ≥ VVIH(MIN)
2
ICC3NS CKE
CS
All input signals are stable.
All banks active
tCK = tCK(MIN), BL=4, CL=3
All banks active
Operating current
(Burst mode)
ICC4
Refresh current
ICC5
tRC = tRC(MIN), tCLK = tCLK(MIN)
Self refresh current
ICC6
CKE
≤ 0.2V
3
4
NOTES
1. ICC(max) is specified at the output open condition.
2. Input signals are changed one time during 30ns.
3. Normal version: VG36128401BT-7H / VG36128801BT-7L / VG36128161BT-8H
4. Low power version: VG36128401BTL-7H / VG3636128401BTL-7L / VG3636128401BTL-8H
DC Characteristics 2
(Ta = 0 ~ 70°C, VDD = VDDQ = 3.3 ± 0.3V , VSS = VSSQ = 0V, unless otherwise noted)
Parameter
Symbol
Test Condition
Min
Max
Unit
Input leakage current (Inputs)
II (L)
0 ≤ VIN ≤ VDD(MAX)
Pins not under test = 0V
-10
10
uA
Output leakage current (I/O pins)
IO (L)
0 ≤ VOUT ≤ VDD(MAX)
DQ# in H - Z., DOUT is disabled
-10
10
uA
2.4
High level output voltage
VOH (DC)
IOH = -2mA
Low level output voltage
VOL (DC)
IOL = 2mA
Document :1G5-0183
V
0.4
Rev.1
Page 6
V
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
AC Characteristics (Ta = 0 ~ 70°C, VDD = VDDQ = 3.3 ± 0.3V , VSS = VSSQ = 0V, unless otherwise noted)
Test Conditions
AC input Levels (VIH/VIL)
Input rise and fall time
2.0 / 0.8V
Input timing reference level /
Output timing reference level
Output load condition
1ns
1.4V
50pF
Output Load Conditions
VDDQ
VDDQ
VOUT
Z = 50
Ω
Device
Under
Test
Document :1G5-0183
50PF
Rev.1
Page 7
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
A.C. Characteristics (Ta = 0 ~ 70°C, VDD = VDDQ = 3.3 ± 0.3V , VSS = VSSQ = 0V, unless otherwise noted)
Limits
Parameter
Symbol
-7H
Min
CLK cycle time
CLK to valid output delay
-7L
Max
Min
-8H
Max
Min
Unit
Max
CL = 3
tCK3
7.5
7.5
10
ns
CL = 2
tCK2
7.5
10
8
ns
CL = 3
tAC3
5.4
5.4
6
ns
CL = 2
tAC2
5.4
6
6
ns
CLK high pulse width
tCH
2.5
2.5
3
ns
CLK low pulse width
tCL
2.5
2.5
3
ns
Input setup time (all input)
tIS
1.5
1.5
2
ns
Input hold time (all input)
tIH
0.8
0.8
1
ns
CL = 3
tOH3
2.7
2.7
3
ns
CL = 2
tOH2
2.7
3
3
ns
0
0
ns
Output data hold time
CLK to output in low - Z
tLZ
0
CLK to output in H - Z
tHZ
2.7
ROW cycle time
tRC
67.5
ROW active time
tRAS
45
RAS to CAS delay
tRCD
15
20
20
ns
Row precharge time
tRP
15
20
20
ns
Row active to active delay
tRRD
14
15
20
ns
Write recovery time
tWR
14
15
20
ns
Transition time
tT
1
Mode reg. set cycle
tRSC
14
15
20
ns
Power down exit setup time
tPDE
7
7.5
10
ns
Self refresh exit time
tSRX
7
7.5
10
ns
Refresh time
tREF
Document :1G5-0183
5.4
5.4
67.5
100K
10
64
Rev.1
2.7
45
1
3
6
70
100K
10
50
ns
ns
100K
1
10
64
64
Page 8
ns
ns
ms
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Basic Features and Function Description
1. Simplified State Diagram
Self
Refresh
LF
SE
Mode
Register
Set
try
en
LF
SE
MRS
it
ex
AUTO
Refresh
REF
IDLE
E
CK
ACT
CK
E
Power
Down
CKE
ROW
ACTIVE
y
Au Write
to p
red with
har
ge
re
co
ve
r
e
rit
W
CKE
WRITE
Read (write recovery)
CKE
CKE
e re
READ
SUSPEND
Read with
Auto Precharge
)
cov
ery)
CKE
CKE
READA
SUSPEND
n)
(P r
ech
arg
e
READ A
PR
E
tio
ina
Precharge
CKE
CKE
ith e
te w arg
Wri Prech
uto
(writA
m
ter
POWER
ON
READ
ter
min
atio
n
WRITE A
R
Auto ead w
Pre ith
cha
rge
rge
cha
P re
E(
PR
CKE
Read
Write
Write with
Auto Precharge
WRITE A
SUSPEND
PRE
WRITE
SUSPEND
ad
Re
Write (Write recovery)
h
wit rge
ad cha
Re Pre
to
Au
W
rit
e
T
BS
BS
T
CKE
Active
Power
Down
Precharge
Automatic sequence
Manual input
Note: After the AUTO refresh operation, precharge operation is
performed automatically and enter the IDLE state
Document :1G5-0183
Rev.1
Page 9
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
2. Truth Table
2.1 Command Truth Table
FUNCTION
Symbol
CKE
n-1
n
CS
RAS
CAS
WE
BA
A10
A11
A9 - A0
Device deselect
DESL
H
X
H
X
X
X
X
X
X
No operation
NOP
H
X
L
H
H
H
X
X
X
Mode register set
MRS
H
X
L
L
L
L
L
L
V
Bank activate
ACT
H
X
L
L
H
H
V
V
V
READ
H
X
L
H
L
H
V
L
V
READA
H
X
L
H
L
H
V
H
V
WRIT
H
X
L
H
L
L
V
L
V
WRITA
H
X
L
H
L
L
V
H
V
Precharge select bank
PRE
H
X
L
L
H
L
V
L
X
Precharge all banks
PALL
H
X
L
L
H
L
X
H
X
Burst stop
BST
H
X
L
H
H
L
X
X
X
CBR (Auto) refresh
REF
H
H
L
L
L
H
X
X
X
Self refresh
SELF
H
L
L
L
L
H
X
X
X
Read
Read with auto precharge
Write
Write with auto precharge
2.2 DQM Truth Table
CKE
DQM
Symbol
n-1
n-1
Data write/output enable
ENB
H
X
L
Data mask/output disable
MASK
H
X
H
FUNCTION
2.3 CKE Truth Table
CKE
Current State
Function
Symbol
n-1
n
CS
RAS
CAS
WE
Add ress
Activating
Clock suspend mode entry
H
L
X
X
X
X
X
Any
Clock suspend
L
L
X
X
X
X
X
Clock suspend
Clock suspend mode exit
L
H
X
X
X
X
X
Idle
CBR refresh command
REF
H
H
L
L
L
H
X
Idle
Self refresh entry
SELF
H
L
L
L
L
H
X
Self refresh
Self refresh exit
L
H
L
H
H
H
X
L
H
H
X
X
X
X
Idle
Power down entry
H
L
X
X
X
X
X
Power down
Power down exit
L
H
X
X
X
X
X
H : High level, L : Low level
X : High or Low level (Don’t care), V : Valid Data input
Document :1G5-0183
Rev.1
Page 10
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
2.4 Operative Command Table (note 1)
HCurrent state CS
Idle
Row active
Read
Write
RAS CAS WE
(1/3)
Address
Command
Action
Notes
H
X
X
X
X
DESL
Nop or Power down
2
L
H
H
X
X
NOP or BST
Nop or Power down
2
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
3
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BR, RA
ACT
Row active
L
L
H
L
BA, A10
PRE/PALL
Nop
L
L
L
H
X
REF/SELF
Refresh or Self refresh
L
L
L
L
Op-Code
MPS
Mode register access
H
X
X
X
X
DESL
Nop
L
H
H
X
X
NOP or BST
Nop
L
H
L
H
BA, CA, A10
READ/READA
Begin read : Determine AP
5
L
H
L
L
BA, CA, A10
WRIT/WRITA
Begin write : Determine AP
5
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PALL
Precharge
6
L
L
L
H
X
REF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
ILLEGAL
H
X
X
X
X
DESL
Continue burst to end
→ Row active
L
H
H
H
X
NOP
Continue burst to end
→ Row active
L
H
H
L
X
BST
Burst stop
L
H
L
H
BA, CA, A10
READ/READA
Term burst, new read : Determine AP
7
L
H
L
L
BA, CA, A10
WRIT/WRITA
Term burst, start write : Determine AP
7,8
L
L
H
H
BA, RA
ACT
ILLEGAL
L
L
H
L
BA, A10
PRE/PALL
Term burst, precharging
L
L
L
H
X
REF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
ILLEGAL
H
X
X
X
X
DESL
Continue burst to end
→ write recovering
L
H
H
H
X
NOP
Continue burst to end
→ write recovering
L
H
H
L
X
BST
Burst stop
L
H
L
H
BA, CA, A10
READ/READA
Term burst, start read : Determine AP
7,8
L
H
L
L
BA, CA, A10
WRIT/WRITA
Term burst, new write : Determine AP
7
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PALL
Term burst, precharging
9
L
L
L
H
X
REF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
ILLEGAL
Document :1G5-0183
Rev.1
4
→ Row active
3
→ Row active
Page 11
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
(2/3)
Current state
Read with auto
precharge
Write with auto
precharge
Precharging
Row activating
CS RAS CA WE
Address
Command
Action
→
→
Notes
H
X
X
X
X
DESL
Continue burst to end
L
H
H
H
X
NOP
L
H
H
L
X
BST
Continue burst to end
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA ILLEGAL
11
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
11
Precharging
Precharging
L
L
H
H
BA, RA
ACT
ILLEGAL
3,11
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL
3,11
L
L
L
H
X
PEF/SELF
ILLEGAL
L
L
L
L
Op - Code
MRS
ILLEGAL
H
X
X
X
X
DESL
Continue burst to end → write
recovering with auto precharte
L
H
H
H
X
NOP
Continue burst to end → write
recovering with auto precharge
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA ILLEGAL
11
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
11
L
L
H
H
BA, RA
ACT
ILLEGAL
3,11
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL
3,11
L
L
L
H
X
REF/SELF
ILLEGAL
L
L
L
L
Op - code
MRS
ILLEGAL
H
X
X
X
X
DESL
Nop
→
Enter idle after tRP
L
H
H
H
X
NOP
Nop
→
Enter idle after tRP
L
H
H
L
X
BST
Nop
→
Enter idle after tRP
L
H
L
H
BA, CA, A10
READ/READA ILLEGAL
3
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PALL
Nop
L
L
L
H
X
REF/SELF
ILLEGAL
L
L
L
L
Op - Code
MRS
ILLEGAL
H
X
X
X
X
DESL
Nop
L
H
H
H
X
NOP
Nop
L
H
H
L
X
BST
Nop
L
H
L
H
BA, CA, A10
READ/READA ILLEGAL
3
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BA, RA
ACT
ILLEGAL
3, 9
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL
3
L
L
L
H
X
REF/SELF
ILLEGAL
L
L
L
L
Op - Code
MRS
ILLEGAL
Document :1G5-0183
Rev.1
→
→
→
→
Enter idle after tRP
Enter row active after tRCD
Enter row active after tRCD
Enter row active after tRCD
Page 12
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
(3/3)
Current
Write
recovering
Write
recovering
with auto
precharge
Auto
Refreshing
Mode register
setting
CS
RAS
CAS
WE
Address
Command
Action
H
X
X
X
X
DESL
Nop
L
H
H
H
X
NOP
Nop
→
→
L
H
H
L
X
BST
Nop
→
L
H
L
H
BA, CA, A10
READ/READA
Start read, Determine AP
L
H
L
L
BA, CA, A10
WRIT/WRITA
New write, Determine AP
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL
3
L
L
L
H
X
PEF/SELF
ILLEGAL
L
L
L
L
Op - Code
MRS
ILLEGAL
H
X
X
X
X
DESL
Nop
L
H
H
H
X
NOP
Nop
→
→
L
H
H
L
X
BST
Nop
→
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
3,8,11
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
3,11
L
L
H
H
BA, RA
ACT
ILLEGAL
3,11
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL
3
L
L
L
H
X
REF/SELF
ILLEGAL
L
L
L
L
Op - Code
MRS
ILLEGAL
H
X
X
X
X
DESL
Nop Enter idle after tRC
L
H
H
X
X
NOP/BST
Nop Enter idle after tRC
L
H
L
X
X
READ/WRIT
ILLEGAL
L
L
H
X
X
ACT/PRE/PALL
ILLEGAL
L
L
L
X
X
REF/SELF/MRS ILLEGAL
H
X
X
X
X
DESL
Nop
L
H
H
H
X
NOP
Nop
L
H
H
L
X
BST
ILLEGAL
L
H
L
X
X
READ/WRITE
ILLEGAL
L
L
X
X
X
ACT/PRE/PALL/ ILLEGAL
REF/SELF/MRS
→
→
Notes
Enter row active after tDPL
Enter row active after tDPL
Enter row active after tDPL
Enter precharge after tDPL
Enter precharge after tDPL
Enter precharge after tDPL
Enter idle after 2 Clocks
Enter idle after 2 Clocks
Note
1. All entries assume that CKE was active (High level) during the preceding clock cycle.
2. If both banks are idle, and CKE is inactive (Low level), the device will enter Power downmode.
All input buffers except CKE will be disabled.
3. Illegal to bank in specified states; Function may be legal in the bank indicated by BankAddress(BA),
state of that bank.
4. If both banks are idle, and CKE is inactive (Low level), the device will enter Self refresh mode.
All input buffers except CKE will be disabled.
5. Illegal if tRCD is not satisfied.
6. Illegal if tRAS is not satisfied.
7. Must satisfy burst interrupt condition.
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9. Must mask preceding data which don’t satisfy tDPL.
10. Illegal if tRRD is not satisfied.
11. Illegal for single bank, but legal for other banks in multi-bank devices.
Document :1G5-0183
Rev.1
8
depending on the
Page 13
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
2.5 Command Truth Table for CKE (Note 1)
Current state
Self refresh
(S.R.)
Self refresh
recovery
Power down
(P.D.)
Both banks
idle
Any state
other than
listed above
CKE
n-1
CKE
n
CS
RAS
H
L
L
L
L
L
H
X
H
H
H
H
L
H
X
H
L
L
L
X
H
H
H
H
H
H
H
H
H
L
L
H
L
CAS
WE
Address
Action
Notes
X
X
H
H
L
X
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
INVALID, CLK (n - 1)would exit S.R.
S.R. Recovery
S.R. Recovery
ILLEGAL
ILLEGAL
Maintain S.R.
Idle after tRC
L
H
H
X
X
Idle after tRC
H
H
L
L
L
L
H
L
X
H
L
L
H
L
L
L
X
X
X
X
H
L
X
H
H
L
X
X
X
X
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ILLEGAL
ILLEGAL
Begin clock suspend next cycle
Begin clock suspend next cycle
ILLEGAL
ILLEGAL
Exit clock suspend next cycle
Maintain clock suspend
INVALID, CLK (n - 1) would exit P.D.
L
H
L
H
X
H
X
X
X
X
X
X
H
H
L
H
X
X
H
H
L
L
H
X
H
H
H
H
L
L
L
L
L
L
H
L
H
L
H
X
X
X
H
L
L
H
X
X
H
L
L
L
H
X
H
H
L
L
L
L
L
L
L
L
H
L
L
H
X
H
X
X
X
X
X
X
X
X
X
X
H
L
L
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
EXIT P.D. → Idle
X
Maintain power down mode
Refer to operations in Operative
Command Table
Refer to operations in Operative
Command Table
Refer to operation in Operative
Command Table
X
Auto Refresh
Op - Code Refer to operations in Operative
Command Table
Refer to operations in Operative
Command Table
Refer to operations in Operative
Command Table
Refer to operations in Operative
Command Table
X
Self refresh
Op - Code Refer to operations in Operative
Command Table
X
Power down
Refer to operations in Operative
Command Table
Begin clock suspend next cycle
Exit clock suspend next cycle
Maintain clock suspend
Note: 1. H : Hight level, L : low level, X : High or low level (Don't care).
2. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup
time must be satisfied before any command other than EXIT.
3. Power down and Self refresh can be entered only from the both banks idle state.
4. Must be legal command as defined in Operative Command Table.
5. Illegal if tSREX is not satisfied.
Document :1G5-0183
Rev.1
Page 14
2
2
5
5
2
2
3
3
4
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
3. Initiallization
Before starting normal operation, the following power on sequence is necessary to prevent SDRAM from damged or
malfunctioning.
1. Apply power and start clock. Attempt to maintain CKE high , DQN high and NOP condition at the inputs.
2. Maintain stable power, table clock , and NOP input conditions for a minimum of 200us.
3. Issue precharge commands for all bank. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode regiser.
After these sequence, the SDRAM is in idle state and ready for normal operation.
4. Programming the Mode Register
The mode register is programmed by the mode register set command using address bits A13 through A0 as data
inputs. The register retains data until it is reprogrammed or the device loses power.
The mode register has four fields;
Options
: A13 through A7
CAS latency
: A6 through A4
Wrap type
: A3
Burst length
: A2 through A0
Following mode register programming, no command can be asserted befor at least two clock cycles have elapsed.
CAS Latency
CAS latency is the most critical parameter being set. It tells the device how many clocks must elapse before the data
will be available.
The value is determined by the frequency of the clock and the speed grade of the device. The value can be programmed as 2 or 3.
Burst Length
Burst Length is the number of words that will be output or input in read or write cycle. After a read burst is completed,
the output bus will become high impedance.
The burst length is programmable as 1, 2, 4, 8 or full page.
Wrap Type (Burst Sequence)
The wrap type specifies the order in which the burst data will be addressed. The order is programmable as either
“Sequential” or “Interleave”. The method chosen will depend on the type of CPU in the system.
Document :1G5-0183
Rev.1
Page 15
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
5. Mode Register
13 12
0 0
11
0
10
0
9
0
8
0
7
0
5
6
4
LTMODE
3
WT
2
1
BL
0
Bits2 - 0 WT = 0 WT = 1
1
000
1
001
Burst length
Wrap type
010
4
4
011
8
8
100
R
R
101
R
R
110
R
R
111
Fullpage
R
0
1
Sequential
Interleave
Bits 6-4
Latency
mode
2
2
000
CAS Iatency
R
001
R
010
2
011
3
100
R
101
R
110
R
111
R
Remark R : Reserved
Document :1G5-0183
Rev.1
Page 16
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
6. Burst Length and Sequence
(Burst of Two)
Starting Address
(column address A0, binary)
Sequential Addressing
Sequence (decimal)
Interleave Addressing Sequence
(decimal)
0
0, 1
0, 1
1
1, 0
1, 0
Starting Address
(column address A1 - A0, binary)
Sequential Addressing
Sequence (decimal)
Interleave Addressing Sequence (decimal)
00
0, 1, 2, 3
0, 1, 2, 3
01
1, 2, 3, 0
1, 0, 3, 2
10
2, 3, 0, 1
2, 3, 0, 1
11
3, 0, 1, 2
3, 2, 1, 0
Starting Address
(column address A2 - A0, binary)
Sequential Addressing
Sequence (decimal)
Interleave Addressing Sequence
(decimal)
000
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
001
1, 2, 3, 4, 5, 6, 7, 0
1, 0, 3, 2, 5, 4, 7, 6
010
2, 3, 4, 5, 6, 7, 0, 1
2, 3, 0, 1, 6, 7, 4, 5
011
3, 4, 5, 6, 7, 0, 1 ,2
3, 2, 1, 0, 7, 6, 5, 4
100
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
101
5, 6 ,7, 0, 1, 2, 3, 4
5, 4, 7, 6, 1, 0, 3, 2
110
6, 7 ,0 ,1 ,2 ,3 ,4 ,5
6, 7, 4, 5, 2, 3, 0, 1
111
7, 0, 1, 2, 3, 4, 5, 6
7, 6, 5, 4, 3, 2, 1, 0
(Burst of Four)
(Burst of Eight)
Full page burst is an extension of the above tables of sequential addressing, with the length being 2,048
(for 32Mx4), 1,024 (for 16M x 8) and 512 (for 8Mx16).
Document :1G5-0183
Rev.1
Page 17
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
7. Precharge
The precharge command can be asserted anytime after tRAS(min.) is satisfied.
Soon after the precharge command is asserted, the precharge operation is performed and the synchronous DRAM enters the
idle state after tRP(min.) is satisfied. The parameter tRP is the time required to perform the precharge.
The earliest timing in a read cycle that a precharge command can be asserted without losing any data in the burst is as follows.
PrechargeE
T0
T1
T3
T2
T4
Burst lengh=4
T7
T6
T5
CLK
Command
Read
PRE
CAS latency = 2
DQ
Q0
Command
Q1
Read
Q2
Hi - Z
Q3
PRE
CAS latency = 3
DQ
Q1
Q0
Q2
Q3
Hi - Z
(tRAS is satisfied)
In order to write all data to the memory cell correctly, the asynchronous parameter ”tDPL ” must be satisfied. The
tDPL(min.) specification defines the earliest time that a precharge command can be asserted. The minimum number of
clocks can be calculated by dividing t DPL(min.) with the clock cycle time.
In summary, the precharge command can be asserted relative to the reference clock that indicates the last data word is
valid. In the following table, minus means clocks before the reference; plus means time after the reference.
Document :1G5-0183
CAS latency
Read
Write
2
-1
+ tDPL(min.)
3
-2
+ tDPL(min.)
Rev.1
Page 18
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
8. Auto Precharge
During a read or write command cycle, A10 controls whether auto precharge is selected. If A10 is high in the read or write
command (Read with Auto precharge command or Write with Auto precharge command), auto precharge is selected and
begins automatically.
In the write cycle, tDAL(min.) must be satisfied before asserting the next activate command to the bank being precharged.
When using auto precharge in the read cycle, knowing when the precharge starts is important because the next activate
command to the bank being precharged cannot be executed until the precharge cycle ends. Once auto precharge has
started, an activate command to the bank can be asserted after tRP has been satisfied.
A Read or Write command without auto - precharge can be terminated in the midst of a burst operation. However, a Read
or Write command with auto - precharge can not be interrupted by the same bank commands before the entire burst operation is completed. Therefore use of the same bank Read, Write, Precharge or Burst Stop command is prohibited during a
read or write cycle with auto - precharge. It should be noted that the device will not respond to the Auto - Precharge command if the device is programmed for full page burst read or write cycles.
The timing when the auto precharge cycle begins depends both on both the CAS Iatency programmed into the mode register and whether the cycle is read or write.
8.1 Read with Auto Precharge
During a READA cycle, the auto precharge begins one clock earlier (CL = 2) or two clocks earlier (CL = 3) than the last
word output.
READ with AUTO PRECHARGE
Burst lengh = 4
T0
T1
T4
T3
T2
T6
T5
T7
CLK
No New Command to Bank B
Command
Auto precharge starts
READA B
CAS latency = 2
DQ
QB0
QB1
QB2
Hi - Z
QB3
No New Command to Bank B
Auto precharge starts
Command
READA B
CAS latency = 3
DQ
QB0
QB1
QB2
QB3
Hi - Z
Remark READA means READ with AUTO PRECHARGE
Document :1G5-0183
Rev.1
Page 19
T8
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
8.2 Write with Auto Precharge
During a write cycle, the auto precharge starts at the timing that is equal to the value of tDPL(min.) after the last data
word input to the device.
WRITE with AUTO PRECHRGE
Burst lengh = 4
T0
T1
T3
T2
T4
T5
T6
T7
T8
CLK
Command
AUTO PRECHARGE starts
WRITA B
tDPL
CAS latency = 2
DQ
DB0
DB1
DB2
Hi - Z_
DB3
AUTO PRECHARGE starts
Command
WRITA B
tDPL
CAS latency = 3
DQ
DB0
DB2
DB1
Hi - Z
DB3
Remark WRITA means WRITE with AUTO Precharge
In summary, the auto precharge cycle begins relative to a reference clock that indicates the last data word is valid.
In the table below, minus means clocks before the reference; plus means clocks after the reference.
Document :1G5-0183
CAS latency
Read
Write
2
-1
+ tDPL(min.)
3
-2
+ tDPL(min.)
Rev.1
Page 20
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
9. Read / Writw Command Interval
9.1 Read to Read Command Interval
During a read cycle when a new read command is asserted, it will be effective after the CAS latency, even if the previous read operation has not completed. READ will be interrupted by another READ.
Each read command can be asserted in every clock without any restriction.
READ to READ Command Interval
Burst lengh=4, CAS latency=2
T0
T1
T3
T2
T4
T6
T5
T7
T8
CLK
Read B
Read A
Command
DQ
QA0
QB0
QB1
QB2
Hi-Z_
QB3
1 cycle
9.2 Write to Write Command Interval
During a write cycle, when a new Write command is asserted, the previous burst will terminated and the new burst will
begin with a new write command. WRITE will be interrupted by another WRITE.
Each write command can be asserted in every clock without any restriction.
WRITE to WRITE Command Interval
Burst lengh=4, CAS latency=2
T0
T1
T3
T2
T4
T5
T6
T7
CLK
Command
Write A
Write B
DQ
QA0
QB0
QB1
QB2
QB3
Hi-Z_
1 cycle
Document :1G5-0183
Rev.1
Page 21
T8
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
9.3 Write to Read Command Interval
The write command to read command interval is also a minimum of 1 cycle. Only the write data before the read command
will be written. The data bus must be Hi-Z at least one cycle prior to the first DOUT.
WRITE to READ Command Interval
Burst lengh=4
T0
T1
T3
T2
T4
T6
T5
T8
T7
CLK
1 cycle
Command
WRITE A
Read B
CAS latency=2
DQ
Command
Hi-Z
DA0
Write A
QB0
QB1
QB2
QB3
QB1
QB2
Read B
CAS latency=3
DQ
DA0
Hi-Z
QB0
QB3
9.4 Read to Write Command Interval
During a read cycle, READ can be interrupted by WRITE.
DQM must be in High at least 3 clocks prior to the write command. There is a restriction to avoid a data conflict. The data
bus must be Hi-Z using DQM before Write.
Document :1G5-0183
Rev.1
Page 22
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
READ to WRITE Command Interval
T0
T1
T3
T2
T4
T6
T5
T7
CAS latency=2
T8
CLK
Read
Command
Write
DQM
DQ
Hi-Z
D0
D1
D2
D3
1 cycle
T0
T1
T3
T2
T4
T6
T5
T7
Burst length=8, CAS latency=2
T9
T8
CLK
Command
Write
Read
DQM
Q0
DQ
Q2
Q1
D0
D2
D1
Hi-Z is
necessary
example: Burst length=4, CAS latency=3
T0
T1
T2
T3
T4
T6
T5
T8
T7
CLK
Command
Read
Write
DQM
DQ
Q2
Hi-Z is
D0
D1
D2
necessary
Document :1G5-0183
Rev.1
Page 23
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
10. BURST Termination
There are two methods to terminate a burst operation other than using a read or a write command. One is the burst
stop command and the other is the precharge command.
10.1 BURST Stop Command
During a read burst, when the burst stop command is issued, the burst read data are terminated and the data bus
goes to high-impedance after the CAS latency from the burst stop command.
During a write burst, when the burst stop command is issued, the burst write data are termained and data bus goes to
Hi-Z at the same clock with the burst stop command.
Burst Termination
T0
T1
T3
T2
T4
Burst lengh=X, CAS Intency=2,3
T7
T6
T5
CLK
BST
Read
Command
CAS latency=2
DQ
Q0
CAS latency=3
Q1
Q2
Q0
Q1
Hi-Z
Hi-Z
Q2
DQ
Remark BST: Burst stop command
T0
T1
T3
T2
T4
T5
Burst lengh=X, CAS latency=2,3
T7
T6
CLK
Command
BST
Write
CAS latency=2,3
Q0
Q0
Q1
Q2
Hi-Z_
DQ
Remark BST: Burst command
Document :1G5-0183
Rev.1
Page 24
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
10.2 PRECHARGE TERMINATION
10.2.1 PRECHARGE TERMINATION in READ Cycle
During READ cycle, the burst read operation is terminated by a precharge command.
When the precharge command is issued, the burst read operation is terminated and precharge starts.
The same bank can be activated again after tRP from the precharge command.
When CAS latency is 2, the read data will remain valid until one clock after the precharge command.
When CAS latency is 3, the read data will remain valid until two clocks after the precharge command.
Precharge Termination in READ Cycle
T0
T1
T3
T2
T4
T6
T5
T7
Burst lengh= X
T8
CLK
Command
PRE
Read
ACT
tRP
CAS latency=2
DQ
command
Q0
Q1
Read
Q2
ACT
PRE
tRP
CAS latency=3
DQ
Document :1G5-0183
Hi-Z
Q3
Q0
Rev.1
Q1
Q2
Q3
Hi-Z
Page 25
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
10.2.2 Precharge Termination in WRITE Cycle
During WRITE cycle, the burst write operation is terminated by a precharge command.
When the precharge command is issued, the burst write operation is terminated and precharge starts.
The same bank can be activated again after tRP from the precharge command. The DQM must be high to mask
invalid data in.
During WRITE cycle, the write data written prior to the precharge command will be correctly stored. However,
invalid data may be written at the same clock as the precharge command. To prevent this from happening, DQM
must be high at the same clock as the precharge command. This will mask the invalid data.
PRECHARGE TERMINATION in WRITE Cycle
T0
T1
T3
T2
T4
T6
T5
T7
Burst lengh = X
T8
CLK
Command
Write
PRE
ACT
CAS latency = 2
DQM
DQ
D0
D1
D2
D3
Hi - Z
D4
tRP
command
Write
PRE
ACT
CAS latency = 3
DQM
DQ
D0
D1
D2
D3
D4
Hi - Z
tRP
Document :1G5-0183
Rev.1
Page 26
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Timing Diagram
Document :1G5-0183
Rev.1
Page 27
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Mode Register Set
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
CKE
t
RSC
CS
RAS
CAS
WE
BS0,1
A10
Address Key
ADD
DQM
t
RP
DQ
Hi-Z
Precharge
Command
All Banks
Document :1G5-0183
Mode Register
Set Command
Rev.1
Command
Page 28
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
AC Parameters for Write Timing (1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5
T6 T7 T8
T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CH
CKE
t
CL
t
CK2
t
CMS
t
CKS
Begin Auto Precharge Begin Auto Precharge
Bank A
Bank B
t
CKH
t
CMH
CS
RAS
CAS
WE
*BS0
A10
tAS
tAH
ADD
DQM
tRCD
DQ
tDAL
t
RRD
tDS
tRC
t
DH
t
DPL
t
RP
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3
Activate
Write with Activate
Write with
Activate
Command Auto Precharge Command Auto Precharge Command
Bank A
Command
Bank A
Command
Bank B
Bank B
Bank A
Write without
Auto Precharge
Command
Bank A
Precharge
Command
Bank A
Activate
Command
Bank A
Activate
Command
Bank B
* BS1=”L”, Bank C,D = Idle
Document :1G5-0183
Rev.1
Page 29
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
AC Parameters for Write Timing (2 of 2)
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CLK
t
CL
t
CH
CKE
t
CK3
t
CMS
t
CKS
Begin Auto Precharge Begin Auto Precharge
Bank A
Bank B
t
CKH
t
CMH
CS
RAS
CAS
WE
*BS0
A10
tAS
tAH
ADD
DQM
tRCD
DQ
t
DAL
t
RRD
tDS
RC
t
DH
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3
Activate
Command
Bank A
Write with Activate
Write with
Auto Precharge Command Auto Precharge
Command
Bank B
Command
Bank A
Bank B
Activate
Command
Bank A
t
DPL
t
RP
QAb0 QAb1 QAb2 QAb3
Write without
Auto Precharge
Command
Bank A
Precharge
Command
Bank A
Activate
Command
Bank A
* BS1=”L”, Bank C,D = Idle
Document :1G5-0183
Rev.1
Page 30
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
AC Parameters for Read Timing (1 of 2)
Burst Length=2, CAS Latency=2
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CLK
tCH tCL
tCK2
Begin Auto
Precharge
Bank B
tCMS
t
CMH
CKE
tCKS
t
CKH
CS
RAS
CAS
WE
*BS0
A10
tAS
tAH
ADD
tRRD
tRAS
tRC
DQM
t
AC2
tLZ
t
RCD
DQ
Hi-Z
tAC2
tOH
QAa0
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank B
tHZ
tOH
QAa1
Read with
Auto Precharge
Command
Bank B
tRP
tHZ
QBa0
Precharge
Command
Bank A
QBa1
Activate
Command
Bank A
* BS1=”L”, Bank C,D = Idle
Document :1G5-0183
Rev.1
Page 31
T13
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
AC Parameters for Read Timing (2 of 2)
Burst Length=2, CAS Latency=3
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11
T12
T13 T14
T15
CLK
t
CH tCL
CKE
t
CK3
Begin Auto
Precharge
Bank B
t
CMS
tCKS
t
CMH
t
CKH
CS
RAS
CAS
WE
*BS0
A10
t
AH
t
AS
ADD
t
RRD
t
RAS
t
RP
t
RC
DQM
tAC3
tLZ
t
RCD
DQ
tAC3
tOH
tHZ
tOH
Hi-Z
QAa0
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank B
QAa1
Read with
Auto Precharge
Command
Bank B
t
QBa0
Precharge
Command
Bank A
HZ
QBa1
Activate
Command
Bank A
* BS1=”L”, Bank C,D = Idle
Document :1G5-0183
Rev.1
Page 32
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Power on Sequence and Auto Refresh (CBR)
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
High level
is required
CKE
t
RSC
Minimum of 8 Refresh Cycles are required
CS
RAS
CAS
WE
BS0, 1
A10
Address Key
ADD
DQM
High Level is Necessary
t
DQ
t
RC
RP
Hi-Z
Precharge
Inputs Command
All Banks
must
be stable
for 200us
Document :1G5-0183
1st Auto
Refresh
Command
2nd Auto
Refresh
Command
Rev.1
Mode Register
Set Command
Command
Page 33
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Clock Suspension During Burst Read (Using CKE) (1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
CKE
CS
RAS
CAS
WE
*BS0
A10
RAa
ADD
RAa
CAa
DQM
t
DQ
HZ
Hi-Z
QAa0
Activate
Command
Bank A
Read
Command
Bank A
QAa1
Clock
Suspended
1 Cycle
QAa2
Clock
Suspended
2 Cycles
QAa3
Clock
Suspended
3 Cycles
* BS1=”L”, Bank C,D = Idle
Document :1G5-0183
Rev.1
Page 34
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Clock Suspension During Burst Read (Using CKE) (2 of 2)
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK3
CKE
CS
RAS
CAS
WE
*BS0
A10
RAa
ADD
RAa
CAa
DQM
t
HZ
DQ
Hi-Z
QAa0
Activate
Command
Bank A
Read
Command
Bank A
QAa1
QAa2
Clock
Suspended
1 Cycles
Clock
Suspended
2 Cycles
QAa3
Clock
Suspended
3 Cycles
* BS1=”L”, Bank C,D = Idle
Document :1G5-0183
Rev.1
Page 35
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Clock Suspension During Burst Write (Using CKE) (1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
CKE
CS
RAS
CAS
WE
*BS0
A10
RAa
ADD
RAa
CAa
DQM
DQ
Hi-Z
DAa0
Activate
Command
Bank A
DAa1
Clock
Suspended
1 Cycle
Write
Command
Bank A
DAa2
Clock
Suspended
2 Cycles
DAa3
Clock
Suspended
3 Cycles
* BS1=”L”, Bank C,D = Idle
Document :1G5-0183
Rev.1
Page 36
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Clock Suspension During Burst Write (Using CKE) (2 of 2)
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6
T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK3
CKE
CS
RAS
CAS
WE
*BS0
A10
RAa
ADD
RAa
CAa
DQM
DQ
Hi-Z
DAa0
Activate
Command
Bank A
DAa1
Clock
Suspended
1 Cycle
Write
Command
Bank A
DAa2
Clock
Suspended
2 Cycles
DAa3
Clock
Suspended
3 Cycles
* BS1=”L”, Bank C,D = Idle
Document :1G5-0183
Rev.1
Page 37
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Power Down Mode and Clock Mask
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
t
t
CKH
CKS
t
CKS
CKE
VALID
CS
RAS
CAS
WE
*BS0
A10
RAa
ADD
RAa
CAa
DQM
DQ
Hi-Z
QAa0 QAa1
Activate
Command
Bank A
ACTIVE
STANDBY
Power Down
Mode Entry
QAa2
Precharge
Command
Read
Command
Bank A
Power Down
Mode Exit
QAa3
Clock Mask
Start
Clock Mask
End
Power Down
Mode Entry
Precharge
Standby
Power
Down
Mode
Exit
Command
* BS1=”L”, Bank C,D = Idle
Document :1G5-0183
Rev.1
Page 38
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Auto Refresh (CBR)
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
CKE
CS
RAS
CAS
WE
*BS0, 1
A10
RAa
ADD
RAa
CAa
DQM
t
DQ
RP
t
RC
t
RC
Hi-Z
Q0
Precharge CBR Refresh
Command
Command
All Banks
CBR Refresh
Command
Q1
Q2
Activate
Read
Command Command
* BS1=”L”, Bank C,D = Idle
Document :1G5-0183
Rev.1
Page 39
Q3
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Self Refresh (Entry and Exit)
CLK can be Stopped**
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
SRX
t
SRX
t
CKS
t
CKS
CKE
CS
RAS
CAS
WE
*BS0
A10
ADD
t
RC
DQM
DQ
t
RC
Hi-Z
All Banks
must be idle
Self refresh
Entry
Self Refresh
Exit
Self Refresh
Entry
Self Refresh
Exit
Activate
Command
* BS1=”L”, Bank C,D = Idle
* Clock can be stopped at CKE=Low. If clock is stopped, it must be restarted/stable for 4 clock cycles before CKE=High
Document :1G5-0183
Rev.1
Page 40
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Random Column Read (Page With Same Bank) (1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
CKE
CS
RAS
CAS
WE
*BS0
A10
RAa
ADD
RAa
RAa
RAd
CAa
CAb
CAc
RAd
CAd
DQM
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QAb0 QAb1 QAc0 QAc1 QAc2 QAc3
Precharge
Command
Bank A
Read
Command
Bank A
Read
Read
Command Command
Bank A
Bank A
QAd0 QAd1 QAd2 QAd3
Precharge Activate
Read
Command Command Command
Bank
A
Bank A
Bank A
* BS1=”L”, Bank C,D = Idle
Document :1G5-0183
Rev.1
Page 41
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Random Column Read (Page With Same Bank) (2 of 2)
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK3
CKE
CS
RAS
CAS
WE
*BS0
A10
RAa
ADD
RAa
RAd
CAa
CAb
CAc
RAd
CAd
DQM
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QAb0 QAb1 QAc0 QAc1 QAc2 QAc3
Activate
Command
Bank A
Read
Command
Bank A
Read
Read
Command Command
Bank A
Bank A
Precharge
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
* BS1=”L”, Bank C,D = Idle
Document :1G5-0183
Rev.1
Page 42
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Random Column Write (Page With Same Bank) (1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
CKE
CS
RAS
CAS
WE
*BS0
A10
Ra
ADD
Ra
Rd
Cb
Ca
Cc
Rd
Cd
DQM
DQ
Hi-Z
Da0
Activate
Command
Bank B
Da1
Write
Command
Bank B
Da2
Da3
Db0
Db1
Dc0
Dc1
Dc2
Write
Write
Command Command
Bank B
Bank B
Dc3
Dd0
Dd1
Dd2
Dd3
Precharge Activate
Write
Command Command Command
Bank B
Bank B
Bank B
* BS1=”L”, Bank C,D = Idle
Document :1G5-0183
Rev.1
Page 43
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Random Column Write (Page With Same Bank) (1 of 2)
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK
CKE
CS
RAS
CAS
WE
*BS0
A10
Ra
ADD
Ra
Rd
Cb
Ca
Cc
Rd
Cd
DQM
DQ
Hi-Z
Da0
Activate
Command
Bank B
Da1
Write
Command
Bank B
Da2
Da3
Db0
Db1
Write
Command
Bank B
Dc0
Dc1
Write
Command
Bank B
Dc2
Dc3
Dd0
Precharge
Command
Bank B
Activate
Command
Bank B
Dd1
Write
Command
Bank B
* BS1=”L”, Bank C,D = Idle
Document :1G5-0183
Rev.1
Page 44
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Random Row Read (Interleaving Banks) (1 of 2)
Burst Length=8, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
CKE
High
CS
RAS
CAS
WE
*BS0
A10
ADD
t
DQM
DQ
RCD
Hi-Z
Activate
Command
Bank B
t
AC2
t
RP
QBb0 QBb1
QBa0 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7
Read
Command
Bank B
Activate
Command
Bank A
Precharge Active
Command Command
Bank B
Bank B
Read
Command
Bank B
Read
Command
Bank A
* BS1=”L”, Bank C,D = Idle
Document :1G5-0183
Rev.1
Page 45
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Random Row Read (Interleaving Banks) (2 of 2)
Burs tLength=8, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK3
CKE
High
CS
RAS
CAS
WE
*BS0
A10
ADD
t
DQM
DQ
t
RCD
t
AC3
RP
Hi-Z
QBa0 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QBb0
Activate
Command
Bank B
Read
Command
Bank B
Activate
Command
Bank A
Read
Command
Bank A
Precharge
Command
Bank B
Activate
Command
Bank B
Read
Precharge
Command Command
Bank B
Bank A
* BS1=”L”, Bank C,D = Idle
Document :1G5-0183
Rev.1
Page 46
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Random Row Write (Interleaving Banks) (1 of 2)
Burst Length=8, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
CKE
High
CS
RAS
CAS
WE
*BS0
A10
ADD
t
RCD
DQM
DQ
Hi-Z
Activate
Command
Bank A
t
DPL
t
RP
QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QBa0 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QAb0 QAb1 QAb2 QAb3 QAb4
Write
Command
Bank A
Activate
Command
Bank B
Precharge Active
Command Command
Bank A
Bank A
Write
Command
Bank B
Write
Command
Bank A
Precharge
Command
Bank B
* BS1=”L”, Bank C,D = Idle
Document :1G5-0183
Rev.1
Page 47
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Random Row Write (Interleaving Banks) (2 of 2)
Burst Length=8, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK
CKE
High
CS
RAS
CAS
WE
*BS0
A10
ADD
RBa
t
DPL
DQM
DQ
Hi-Z
Activate
Command
Bank A
t
DPL
t
RP
QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QBa0 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBb7 QAb0 QAb1 QAb2 QAb3
Write
Command
Bank A
Activate
Command
Bank B
Write
Command
Bank B
Precharge
Command
Bank A
Activate
Command
Bank A
Precharge
Write
Command Command
Bank B
Bank A
* BS1=”L”, Bank C,D = Idle
Document :1G5-0183
Rev.1
Page 48
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Read and Write Cycle (1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
CKE
CS
RAS
CAS
WE
*BS0
A10
RAa
ADD
RAa
CAb
CAa
CAc
DQM
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3
Activate
Command
Bank A
Write
Command
Bank A
DAb0 DAb1
DAb3
The Write Data
Write
Command is Masked with a
Bank A
Zero Clock
latency
QAc0 QAc1
Read
Command
Bank A
QAc3
The Read Data
is Masked with
Two Clocks
Latency
* BS1=”L”, Bank C,D = Idle
Document :1G5-0183
Rev.1
Page 49
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Read and Write Cycle (2 of 2)
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK3
CKE
CS
RAS
CAS
WE
*BS0
A10
RAa
ADD
RAa
CAa
CAb
CAc
DQM
DQ
Hi-Z
DAb0 DAb1
QAa0 QAa1 QAa2 QAa3
Activate
Command
Bank A
Read
Command
Bank A
DAb3
Write
The Write Data Read
Command is Masked with a Command
Bank A
Bank A
Zero Clock
Latency
QAc0 QAc1
QAc3
The Read Data
is Masked with
Two Clock
Latency
* BS1=”L”, Bank C,D = Idle
Document :1G5-0183
Rev.1
Page 50
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Interleaved Column Read Cycle (1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
CKE
CS
RAS
CAS
WE
*BS0
A10
Ra
ADD
Ra
Ca
t
DQM
DQ
Ra
RCD
Ra
Ca
Cb
Cc
Cb
Cd
t
AC2
Hi-Z
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBb0 QBb1 QBc0 QBc1 QAb0 QAb1 QBd0 QBd1 QBd2 QBd3
Activate
Command
Bank A
Read
Read
Read
Activate
Read
Read
Read
Command Command Command Command Command Command Command
Bank A
Bank A
Bank B
Bank B
Bank B
Bank B
Bank B
Precharge
Command
Bank B
Precharge
Command
Bank A
* BS1=”L”, Bank C,D = Idle
Document :1G5-0183
Rev.1
Page 51
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Interleaved Column Read Cycle (2 of 2)
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK3
CKE
CS
RAS
CAS
WE
*BS0
A10
Ra
ADD
Ra
Ra
Ca
Ca
Ra
Cb
Cc
Cb
DQM
t
RCD
t
RRD
DQ
t
AC3
Hi-Z
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBb0 QBb1 QBc0 QBc1 QAb0 QAb1 QAb2 QAb3
Activate
Command
Bank A
Read
Command
Bank A
Read
Read
Read
Read
Precharge Precharge
Command Command Command Command Command Command
Bank A
Bank B
Bank B Bank B
Bank B
Bank A
Activate
Command
Bank B
* BS1=”L”, Bank C,D = Idle
Document :1G5-0183
Rev.1
Page 52
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Interleaved Column Write Cycle (1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
CKE
CS
RAS
CAS
WE
*BS0
A10
Ra
ADD
Ra
Ra
Ca
Ca
Cb
Cc
Cb
t
RCD
DQM
t
DQ
Ra
Cb
t
RP
t
DPL
RRD
Hi-Z
DAa0 DAa1 DAa2 DAa3 DBa0 DBa1 DBb0 DBb1 DBc0 DBc1 DAb0 DAb1 DBd0 DBd1 DBd2 DBd3
Activate
Write
Write
Write
Write
Write
Activate
Command Command Command Command Command Command Command
Bank B
Bank B
Bank A
Bank A
Bank B
Bank B
Bank A
Precharge
Command
Bank A
Write
Command
Bank B
Precharge
Command
Bank B
* BS1=”L”, Bank C,D = Idle
Document :1G5-0183
Rev.1
Page 53
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Interleaved Column Write Cycle (2 of 2)
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK3
CKE
CS
RAS
CAS
WE
*BS0
A10
Ra
ADD
Ra
Ra
Ca
Ca
Cb
t
RCD
DQM
t
DQ
Ra
Cc
Cb
Cd
t
DPL
t
DPL
t
RP
RRD
Hi-Z
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBb0 QBb1 QBc0 QBc1 QAb0 QAb1 QBd0 QBd1 QBd2 QBd3
Activate
Command
Bank A
Write
Command
Bank A
Write
Write
Write
Write
Write
Command Command Command Command Command
Bank A
Bank B
Bank B Bank B
Bank B
Activate
Command
Bank B
Precharge
Command
Bank B
Precharge
Command
Bank A
* BS1=”L”, Bank C,D = Idle
Document :1G5-0183
Rev.1
Page 54
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Auto Precharge after Read Burst (1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CKE
CK2
High
Start Auto Precharge
Bank B
Start Auto Precharge
Bank A
Start Auto Precharge
Bank B
CS
RAS
CAS
WE
*BS0
A10
Ra
ADD
Ra
Ra
Ca
Ra
Rb
Ca
Cb
Rb
Rc
Cb
Rc
Cc
DQM
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QAc2
Activate
Read
Activate
Read with
Command Command Command Auto Precharge
Bank A
Bank A
Bank B Command
Bank B
Read with
Auto Precharge
Command
Bank A
Activate
Command
Read with
Bank A
Auto Precharge
Command
Read with
Activate
Bank B
Auto Precharge
Command
Command
Bank B
Bank A
* BS1=”L”, Bank C,D = Idle
Document :1G5-0183
Rev.1
Page 55
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Auto Precharge after Read Burst (2 of 2)
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CKE
CK3
High
Start Auto Precharge
Bank B
Start Auto
Precharge
Bank A
Start Auto Precharge
Bank B
CS
RAS
CAS
WE
*BS0
A10
Ra
ADD
Ra
Ra
Ca
Ra
Rb
Ca
Cb
Rb
RBb
Cb
DQM
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3
Activate
Command
Bank A
Activate
Command
Bank B
Read with
Auto Precharge
Command
Bank B
Read with
Auto Precharge
Command
Bank A
Activate
Command
Bank B
QBb0 QBb1 QBb2
Write with
Auto precharge
Command
Bank B
Read
Command
Bank A
* BS1=”L”, Bank C,D = Idle
Document :1G5-0183
Rev.1
Page 56
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Auto Precharge after Write Burst (1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CKE
CK2
High
Start Auto Precharge
Bank B
Start Auto Precharge
Bank B
Start Auto Precharge
Bank A
CS
RAS
CAS
WE
*BS0
A10
Ra
ADD
Ra
Ra
Ca
Ra
Rb
Ca
Cb
Rb
Rc
Cb
Rc
Cc
DQM
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QAc2 QAc3
Activate
Write
Write with
Activate
Command Command Command Auto Precharge
Command
Bank A
Bank B
Bank A
Bank B
Activate
Write with
Activate
Command
Auto Precharge Command
Bank A
Command
Bank B
Write with
Bank A
Auto Precharge
Write with
Bank A
Auto Precharge
Command
Bank B
Start Auto
Precharge
Bank A
* BS1=”L”, Bank C,D = Idle
Document :1G5-0183
Rev.1
Page 57
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Auto Precharge after Write Burst (2 of 2)
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK3
CKE
High
Start Auto
Precharge
Bank A
Start Auto Precharge
Bank B
Start Auto Precharge
Bank B
CS
RAS
CAS
WE
*BS0
A10
Ra
ADD
Ra
Ra
Ca
Ra
Rb
Ca
Cb
Rb
RBb
Cb
DQM
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3
Activate
Command
Bank A
Activate
Command
Bank B
Read with
Auto Precharge
Command
Bank B
Read with
Auto Precharge
Command
Bank A
Activate
Command
Bank B
QBb0 QBb1 QBb2 QBb3
Write with
Auto precharge
Command
Bank B
Read
Command
Bank A
* BS1=”L”, Bank C,D = Idle
Document :1G5-0183
Rev.1
Page 58
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Full Page Read Cycle (1 of 2)
Burst Length=Full Page, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
CKE
High
CS
RAS
CAS
WE
*BS0
A10
Ra
ADD
Ra
Rb
Ra
Ca
Ca
Ra
Rb
t
RP
DQM
DQ
Hi-Z
QAa
Activate
Command
Bank A
Read
Command
Bank A
QAa+1 QAa+2 QAa-2 QAa-1
Activate
Command
Bank B
QAa
QAa+1 QBa
Read
Command
Bank B
QBa+1 QBa+2 QBa+3 QBa+4 QBa+51QBa+6
Full page burst operation does not
terminate when the burst length is
satisfied; the burst counter
increments and continues bursting
beginning with the starting address
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Precharge
Command
Bank B
Activate
Command
Bank B
Burst Stop
Command
* BS1=”L”, Bank C,D = Idle
Document :1G5-0183
Rev.1
Page 59
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Full Page Read Cycle (2 of 2)
Burst Length=Full Page, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK3
CKE
High
CS
RAS
CAS
WE
*BS0
A10
Ra
ADD
Ra
Rb
Ra
Ca
Ca
Ra
Rb
DQM
DQ
Hi-Z
QAa
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank B
QAa+1 QAa+2 QAa-2 QAa-1
QAa
Read
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval
QAa+1 QBa0
QBa+1 QBa+2 QBa+3 QBa+4 QBa+5
Full page burst operation
does not teminate when
the burst length is satisfied;
the burst counter increments
and continues bursting
beginning with the starting
address
Precharge
Command
Bank B
Activate
Command
Bank B
Burst Stop
Command
* BS1=”L”, Bank C,D = Idle
Document :1G5-0183
Rev.1
Page 60
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Full Page Write Cycle (1 of 2)
Burst Length=Full Page, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
CKE
High
CS
RAS
CAS
WE
*BS0
A10
Ra
ADD
Ra
Rb
Ra
Ca
Rb
Ca
Ra
DQM
t
DQ
BDL
Hi-Z
QAa
Activate
Command
Bank A
QAa+1 QAa+2 QAa+3 QAa-1
Write
Command
Bank A
QAa
QAa+1
Activate
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval
QBa
QBa+1 QBa+2 QBa+3 QBa+4 QBa+5 QBa+6
Write
Command
Bank B
Data is ignored
Precharge
Command
Bank B
Full page burst operation
does not terminate when
the burst length is satisfied;
the burst counter increments
and continues bursting
beginning with the starting
address
Activate
Command
Bank B
Burst Stop
Command
* BS1=”L”, Bank C,D = Idle
Document :1G5-0183
Rev.1
Page 61
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Full Page Write Cycle (2 of 2)
Burst Length=Full Page, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK3
CKE
High
CS
RAS
CAS
WE
*BS0
A10
Ra
ADD
Ra
Rb
Ra
Ca
Rb
Ca
Ra
DQM
tBDL
DQ
Data is ignored.
Hi-Z
DAa
Activate
Command
Bank A
DAa+1 DAa+2 DAa+3 DAa-1
Write
Command
Bank A
DAa
DAa+1
Activate
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval
DBa
DBa+1 DBa+2 DBa+3 DBa+4 DBa+5
Write
Command
Bank B
Full page burst operation
does not terminate when
the burst length is satisfied;
the burst counter increments
and continues bursting
beginning with the starting
address
Precharge
Command
Bank B
Activate
Command
Bank B
Burst Stop
Command
* BS1=”L”, Bank C,D = Idle
Document :1G5-0183
Rev.1
Page 62
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Burst Read and Single Write Operation
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
CLK
CKE
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
High
CS
RAS
CAS
WE
*BS0
A10
RAa
ADD
RAa
CAa
CAb
CAc
CAd
CAe
DQM
Hi-Z
DQ
Activate
Command
Bank A
Read
Command
Bank A
Read
Single Write Single Write
Command
Command
Command
Bank A
Bank A
Bank A
DQs are
masked
Single Write
Command
Bank A
* BS1=”L”, Bank C,D = Idle
Document :1G5-0183
Rev.1
Page 63
DQs are
masked
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Full Page Random Column Read
Burst Length=Full Page, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
CKE
CS
RAS
CAS
WE
BS
A10
Ra
Ra
ADD
Ra
Ra
Rb
Ca
Ca
Cb
Cc
Cb
Cc
Rb
t
RP
DQM
DQ
Hi-Z
QAa0 QBa0
Activate
Command
Bank A
Activate
Command
Bank B
Read
Command
Bank B
Read
Command
Bank A
QAb0
QAb1
Read
Command
Bank B
QBb0
QBb1
Read
Command
Bank A
QAc0
QAc1
QAc2
Read
Command
Bank B
QBc0
QBc1
QBc2
Precharge
Command Bank B (Bank D)
(Precharge Termination)
Activate
Command
Bank B
Read
Command
Bank A
* BS1=”L”, Bank C,D = Idle
Document :1G5-0183
Rev.1
Page 64
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Full Page Random Column Write
Burst Length=Full Page, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
CKE
CS
RAS
CAS
WE
*BS0
A10
Ra
Ra
ADD
Ra
Ra
Rb
Ca
Ca
Cb
Cc
Cb
Cc
Rb
t
RP
DQM
DQ
Hi-Z
QAa0
Activate
Command
Bank A
Activate
Command
Bank B
QBa0
QAb0
QAb1
Write
Command
Bank B
Write
Command
Bank A
QBb0
QBb1
Write
Command
Bank B
QAc0
QAc1
Write
Command
Bank A
QAc2
QBc0
QBc1
Write
Command
Bank B
QBc2
Precharge
Command Bank B (Bank D)
(Precharge Termination)
Write Data
is masked
Write
Command
Bank A
Activate
Command
Bank B
* BS1=”L”, Bank C,D = Idle
Document :1G5-0183
Rev.1
Page 65
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Precharge Termination of a Burst (1 of 2)
Burst Length=8, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
CKE
High
CS
RAS
CAS
WE
*BS0
A10
RAa
ADD
RAa
RAb
CAa
RAb
t
DPL
t
RAc
CAb
RAc
t
RP
CAc
t
RP
RP
DQM
DQ
Hi-Z
QAa0
Activate
Command
Bank A
QAa1
Write
Command
Bank A
QAa2
QAb0
Da3
Precharge
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
Precharge Termination
of a Write Burst. Write
data is masked.
QAb1
QAb2
Precharge
Command
Bank A
Activate
Command
Bank A
QAc0
Read
Command
Bank A
QAc1
QAc2
Precharge
Command
Bank A
Precharge Termination
of a Read Burst.
* BS1=”L”, Bank C,D = Idle
Document :1G5-0183
Rev.1
Page 66
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Precharge Termination of a Burst (2 of 2)
Burst Length=8, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK3
CKE
High
CS
RAS
CAS
WE
*BS0
A10
RAa
ADD
RAa
RAb
CAa
RAb
t DPL
t
DQM
DQ
t
RAc
CAb
t
RP
RAc
t
RAS
RP
RCD
Hi-Z
DAa0
Activate
Command
Bank A
QAb0
DAa1
Write
Command
Bank A
Precharge
Command
Bank A
Write Data
is masked
Activate
Command
Bank A
Read
Command
Bank A
QAb1
QAb2
Activate
Command
Bank A
QAb3
Activate
Command
Bank A
Precharge Termination
of a Read Burst.
Precharge Termination
of a Write Burst.
* BS1=”L”, Bank C,D = Idle
Document :1G5-0183
Rev.1
Page 67
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Ordering information
Part Number
Cycle time
VG3612840(80/16)1BT(L)-7H
7.5 ns (133MHz 2/2/2)
VG3612840(80/16)1BT(L)-7L
7.5 ns (133MHz 3/3/3)
VG3612840(80/16)1BT(L)-8H
10 ns (100MHz 2/2/2)
Package
400mil, 54-Pin
Plastic TSOP
VG36128401BT(L)-7L
• VG : VIS Memory Product
• 36
: Technology/Design Rule
• 128 : 128Mb
• 80
: Device Configuration, 40:x4, 80: x8, 16: x16
•1
: Interface Type, 1: LVTTL
•B
: Mask/Design Version
•T
: Package Type, T: TSOP
•L
: None: normal version; L:low power version
• 7L
: Cycle time, 7H: 133MHz 2/2/2, 7L: 133MHz 3/3/3, 8H: 100MHz 2/2/2
Packaging Information
• 400mil, 54-Pin Plastic TSOP
DIM
A
MILLIMETERS
RAD R1
INCHES
MIN.
NOM.
MAX.
MIN.
NOM.
MAX.
---
---
1.20
---
---
0.047
A1
0.05
---
0.15
0.002
---
0.006
A2
0.95
1.00
1.05
0.037
0.039
0.041
b
0.30
---
0.45
0.012
---
0.018
b1
0.30
---
0.40
0.012
---
0.016
c
0.12
---
0.21
0.005
---
0.008
c1
0.12
---
0.16
0.005
---
0.006
D
22.09
22.35
0.870
0.875
0.880
ZD
e
22.22
0.71 REF.
0.028 REF.
0.80 BASIC
0.0315 BASIC
54
RAD R
28
A2
B
L
A1
E1
c
B
0¢X~8¢X
DETAIL A
b
SECTION B-B
b1
E
11.56
11.76
11.96
0.455
0.463
0.471
E1
10.03
10.16
10.29
0.395
0.400
0.405
L
0.40
0.50
0.60
0.016
0.020
0.024
R
0.12
---
0.25
0.005
---
0.010
R1
0.12
---
---
0.005
---
---
1
27
D
c1
c
BASE METAL
WITH PLATING
NOTE:
1. CONTROLLING DIMENSION : MILLIMETERS
2. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION.
MOLD PROTRUSION SHALL NOT EXCEED 0.15mm(0.006") PER SIDE.
DIMENSION E1 DOES NOT INCLUDE INTERLEAD PROTRUSION.
INTERLEAD PROTRUSION SHALL NOT EXCEED 0.25mm(0.01") PER SIDE.
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSIONS/INTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD TO
BE WIDER THAN THE MAX b DIMENSION BY MORE THAN 0.13mm.
DAMBAR INTRUSION SHALL NOT CAUSE THE LEAD TO BE NARROWER
THAN THE MIN b DIMENSION BY MORE THAN 0.07mm.
Document :1G5-0183
DETAIL A
ZD
A
e
b
E
SEATING PLANE
0.100(0.004")
Rev.1
Page 68