PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD45128441-I, 45128841-I, 45128163-I 128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range) Description The µPD45128441, 45128841, 45128163 are high-speed 134,217,728-bit synchronous dynamic random-access memories, organized as 8,388,608 × 4 × 4, 4,194,304 × 8 × 4, 2,097,152 × 16 × 4 (word × bit × bank), respectively. The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture. All inputs and outputs are synchronized with the positive edge of the clock. The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL). These products are packaged in 54-pin TSOP (II). Features • Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge • Pulsed interface • Possible to assert random column address in every cycle • Quad internal banks controlled by BA0(A13) and BA1(A12) • Byte control (×16) by LDQM and UDQM • Programmable Wrap sequence (Sequential / Interleave) • Programmable burst length (1, 2, 4, 8 and full page) • Programmable /CAS latency (2 and 3) • Ambient temperature (TA): −40 to + 85°C • Automatic precharge and controlled precharge • CBR (Auto) refresh and self refresh • ×4, ×8, ×16 organization • Single 3.3 V ± 0.3 V power supply • LVTTL compatible inputs and outputs • 4,096 refresh cycles / 64 ms • Burst termination by Burst stop command and Precharge command The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for availability and additional information. Document No. E0233N10 (Ver. 1.0) Date Published November 2001 (K) Japa C Elpida Memory, Inc. 2001 Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd. µPD45128441-I, 45128841-I, 45128163-I Ordering Information Part number µPD45128441G5-A75I-9JF Organization (word × bit × bank) Clock frequency MHz (MAX.) 8M × 4 × 4 133 54-pin Plastic TSOP (II) Ambient temperature 125 (10.16mm (400)) µPD45128441G5-A80I-9JF µPD45128441G5-A10I-9JF µPD45128841G5-A75I-9JF 100 4M × 8 × 4 133 µPD45128841G5-A80I-9JF 125 µPD45128841G5-A10I-9JF 100 µPD45128163G5-A75I-9JF 2M × 16 × 4 µPD45128163G5-A80I-9JF 125 µPD45128163G5-A10I-9JF µPD45128441G5-A75LI-9JF 133 100 8M × 4 × 4 133 µPD45128441G5-A80LI-9JF 125 µPD45128441G5-A10LI-9JF 100 µPD45128841G5-A75LI-9JF 4M × 8 × 4 µPD45128841G5-A80LI-9JF 125 µPD45128841G5-A10LI-9JF µPD45128163G5-A75LI-9JF 133 100 2M × 16 × 4 133 µPD45128163G5-A80LI-9JF 125 µPD45128163G5-A10LI-9JF 100 2 Preliminary Data Sheet E0233N10 Package Note TA = −40 to + 85°C µPD45128441-I, 45128841-I, 45128163-I Part Number [ x4, x8 ] µPD45128841G5 - A75L I NEC Memory Synchronous DRAM Memory density Wide temperature range 128 : 128M bits I : -40 to + 85°C Low Power Organization 4 : x4 8 : x8 Minimum cycle time 75 80 10 Number of banks : 7.5 ns (133 MHz) : 8 ns (125 MHz) : 10 ns (100 MHz) 4 : 4 banks Low voltage Interface A : 3.3 V ± 0.3 V 1 : LVTTL Package [ x16 ] 163 G5 : TSOP (II) Organization 16 : x16 Number of banks and Interface 3 : 4 banks, LVTTL Preliminary Data Sheet E0233N10 3 µPD45128441-I, 45128841-I, 45128163-I Pin Configurations /xxx indicates active low signal. [µPD45128441] 54-pin Plastic TSOP (II) (10.16mm (400)) 8M words × 4 bits × 4 banks VCC NC VCCQ NC DQ0 VSSQ NC NC VCCQ NC DQ1 VSSQ NC VCC NC /WE /CAS /RAS /CS BA0(A13) BA1(A12) A10 A0 A1 A2 A3 VCC A0 to A11 Note 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Vss NC VssQ NC DQ3 VccQ NC NC VssQ NC DQ2 VccQ NC Vss NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 Vss : Address inputs BA0(A13), BA1(A12): Bank select DQ0 to DQ3 4 : Data inputs / outputs CLK : Clock input CKE : Clock enable /CS : Chip select /RAS : Row address strobe /CAS : Column address strobe /WE : Write enable DQM : DQ mask enable VCC : Supply voltage VSS : Ground VCCQ : Supply voltage for DQ VSSQ : Ground for DQ NC : No connection Note A0 to A11 Preliminary Data Sheet E0233N10 : Row address inputs A0 to A9, A11 : Column address inputs µPD45128441-I, 45128841-I, 45128163-I [µPD45128841] 54-pin Plastic TSOP (II) (10.16mm (400)) 4M words × 8 bits × 4 banks VCC DQ0 VCCQ NC DQ1 VSSQ NC DQ2 VCCQ NC DQ3 VSSQ NC VCC NC /WE /CAS /RAS /CS BA0(A13) BA1(A12) A10 A0 A1 A2 A3 VCC A0 to A11 Note 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Vss DQ7 VssQ NC DQ6 VccQ NC DQ5 VssQ NC DQ4 VccQ NC Vss NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 Vss : Address inputs BA0(A13), BA1(A12): Bank select DQ0 to DQ7 : Data inputs / outputs CLK : Clock input CKE : Clock enable /CS : Chip select /RAS : Row address strobe /CAS : Column address strobe /WE : Write enable DQM : DQ mask enable VCC : Supply voltage VSS : Ground VCCQ : Supply voltage for DQ VSSQ : Ground for DQ NC : No connection Note A0 to A11 : Row address inputs Preliminary Data Sheet E0233N10 A0 to A9 : Column address inputs 5 µPD45128441-I, 45128841-I, 45128163-I [µPD45128163] 54-pin Plastic TSOP (II) (10.16mm (400)) 2M words × 16 bits × 4 banks VCC DQ0 VCCQ DQ1 DQ2 VSSQ DQ3 DQ4 VCCQ DQ5 DQ6 VSSQ DQ7 VCC LDQM /WE /CAS /RAS /CS BA0(A13) BA1(A12) A10 A0 A1 A2 A3 VCC A0 to A11 Note 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Vss DQ15 VssQ DQ14 DQ13 VccQ DQ12 DQ11 VssQ DQ10 DQ9 VccQ DQ8 Vss NC UDQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 Vss : Address inputs BA0(A13), BA1(A12): Bank select DQ0 to DQ15 : Data inputs / outputs CLK : Clock input CKE : Clock enable /CS : Chip select /RAS : Row address strobe /CAS : Column address strobe /WE : Write enable LDQM : Lower DQ mask enable UDQM : Upper DQ mask enable VCC : Supply voltage : Ground : Supply voltage for DQ VSSQ : Ground for DQ NC 6 Note A0 to A11 : Row address inputs VSS VCCQ : No connection Preliminary Data Sheet E0233N10 A0 to A8 : Column address inputs µPD45128441-I, 45128841-I, 45128163-I Block Diagram CLK CKE Clock Generator Bank D Bank C Address Mode Register Row Address Buffer & Refresh Counter Row Decoder Bank B Bank A DQM Column Decoder & Latch Circuit Data Control Circuit Preliminary Data Sheet E0233N10 Input & Output Buffer /WE Column Address Buffer & Burst Counter Latch Circuit /CAS Control Logic /RAS Command Decoder Sense Amplifier /CS DQ 7 µPD45128441-I, 45128841-I, 45128163-I CONTENTS 1. Input / Output Pin Function ........................................................................................................... 10 2. Commands ...................................................................................................................................... 11 3. Simplified State Diagram ............................................................................................................... 14 4. Truth Table ...................................................................................................................................... 15 4.1 Command Truth Table ............................................................................................................................ 15 4.2 DQM Truth Table ..................................................................................................................................... 15 4.3 CKE Truth Table ...................................................................................................................................... 15 4.4 Operative Command Table .................................................................................................................... 16 4.5 Command Truth Table for CKE ............................................................................................................. 19 5. Initialization ..................................................................................................................................... 20 6. Programming the Mode Register .................................................................................................. 21 7. Mode Register ................................................................................................................................. 22 7.1 Burst Length and Sequence ................................................................................................................. 23 8. Address Bits of Bank-Select and Precharge ................................................................................ 24 9. Precharge ........................................................................................................................................ 25 10. Auto Precharge ............................................................................................................................... 26 10.1 Read with Auto Precharge .................................................................................................................. 26 10.2 Write with Auto Precharge ................................................................................................................. 27 11. Read / Write Command Interval .................................................................................................... 28 11.1 Read to Read Command Interval ....................................................................................................... 28 11.2 Write to Write Command Interval ....................................................................................................... 28 11.3 Write to Read Command Interval ....................................................................................................... 29 11.4 Read to Write Command Interval ....................................................................................................... 30 12. Burst Termination ........................................................................................................................... 31 8 12.1 Burst Stop Command ......................................................................................................................... 31 12.2 Precharge Termination ....................................................................................................................... 32 12.2.1 Precharge Termination in READ Cycle ................................................................................... 32 12.2.2 Precharge Termination in WRITE Cycle ................................................................................. 33 Preliminary Data Sheet E0233N10 µPD45128441-I, 45128841-I, 45128163-I 13. Electrical Specifications ................................................................................................................ 34 13.1 AC Parameters for Read Timing ........................................................................................................ 39 13.2 AC Parameters for Write Timing ........................................................................................................ 41 13.3 Relationship between Frequency and Latency ................................................................................. 42 13.4 Mode Register Set ............................................................................................................................... 43 13.5 Power on Sequence and CBR (Auto) Refresh .................................................................................. 44 13.6 /CS Function ........................................................................................................................................ 45 13.7 Clock Suspension during Burst Read (using CKE Function) ......................................................... 46 13.8 Clock Suspension during Burst Write (using CKE Function) ......................................................... 48 13.9 Power Down Mode and Clock Mask .................................................................................................. 50 13.10 CBR (Auto) Refresh ............................................................................................................................. 51 13.11 Self Refresh (Entry and Exit) .............................................................................................................. 52 13.12 Random Column Read (Page with Same Bank) ............................................................................... 53 13.13 Random Column Write (Page with Same Bank) ............................................................................... 55 13.14 Random Row Read (Ping-Pong Banks) ............................................................................................ 57 13.15 Random Row Write (Ping-Pong Banks) ............................................................................................ 59 13.16 Read and Write .................................................................................................................................... 61 13.17 Interleaved Column Read Cycle ......................................................................................................... 63 13.18 Interleaved Column Write Cycle ......................................................................................................... 65 13.19 Auto Precharge after Read Burst ....................................................................................................... 67 13.20 Auto Precharge after Write Burst ....................................................................................................... 69 13.21 Full Page Read Cycle .......................................................................................................................... 71 13.22 Full Page Write Cycle .......................................................................................................................... 73 13.23 Byte Write Operation ........................................................................................................................... 75 13.24 Burst Read and Single Write (Option) ............................................................................................... 77 13.25 Full Page Random Column Read ....................................................................................................... 79 13.26 Full Page Random Column Write ....................................................................................................... 81 13.27 PRE (Precharge) Termination of Burst .............................................................................................. 83 14. Package Drawing ............................................................................................................................ 85 15. Recommended Soldering Conditions .......................................................................................... 86 16. Revision History ............................................................................................................................. 87 Preliminary Data Sheet E0233N10 9 µPD45128441-I, 45128841-I, 45128163-I 1. Input / Output Pin Function Pin name Input / Output CLK Input CKE Input Function CLK is the master clock input. Other inputs signals are referenced to the CLK rising edge. CKE determine validity of the next CLK (clock). If CKE is high, the next CLK rising edge is valid; otherwise it is invalid. If the CLK rising edge is invalid, the internal clock is not issued and the µPD45128xxx suspends operation. When the µPD45128xxx is not in burst mode and CKE is negated, the device enters power down mode. During power down mode, CKE must remain low. /CS Input /CS low starts the command input cycle. When /CS is high, commands are ignored but operations continue. /RAS, /CAS, /WE Input /RAS, /CAS and /WE have the same symbols on conventional DRAM but different functions. For details, refer to the command table. A0 - A11 Input Row Address is determined by A0 - A11 at the CLK (clock) rising edge in the active command cycle. It does not depend on the bit organization. Column Address is determined by A0 - A9, A11 at the CLK rising edge in the read or write command cycle. It depends on the bit organization: A0 - A9, A11 for ×4 device, A0 - A9 for ×8 device, A0 - A8 for ×16 device. A10 defines the precharge mode. When A10 is high in the precharge command cycle, all banks are precharged; when A10 is low, only the bank selected by BA0(A13) and BA1(A12) is precharged. When A10 is high in read or write command cycle, the precharge starts automatically after the burst access. BA0, BA1 Input BA0(A13) and BA1(A12) are the bank select signal. In command cycle, BA0(A13) and BA1(A12) low select bank A, BA0(A13) high and BA1(A12) low select bank B, BA0(A13) low and BA1(A12) high select bank C and then BA0(A13) and BA1(A12) high select bank D. DQM, UDQM, LDQM Input DQM controls I/O buffers. In ×16 products, UDQM and LDQM control upper byte and lower byte I/O buffers, respectively. In read mode, DQM controls the output buffers like a conventional /OE pin. DQM high and DQM low turn the output buffers off and on, respectively. The DQM latency for the read is two clocks. In write mode, DQM controls the word mask. Input data is written to the memory cell if DQM is low but not if DQM is high. The DQM latency for the write is zero. DQ0 - DQ15 Input / Output VCC, VSS, VCCQ, VSSQ (Power supply) DQ pins have the same function as I/O pins on a conventional DRAM. VCC and VSS are power supply pins for internal circuits. VCCQ and VSSQ are power supply pins for the output buffers. 10 Preliminary Data Sheet E0233N10 µPD45128441-I, 45128841-I, 45128163-I 2. Commands Mode register set command Fig.1 Mode register set command CLK (/CS, /RAS, /CAS, /WE = Low) CKE The µPD45128xxx has a mode register that defines how the device /CS operates. In this command, A0 through A11, BA0(A13) and BA1(A12) /RAS are the data input pins. /CAS After power on, the mode register set command must be executed to initialize the device. The mode register can be set only when all banks are in idle state. During 2 CLK (tRSC) following this command, the µPD45128xxx cannot accept any other commands. H /WE BA0(A13), BA1(A12) A10 Add Activate command Fig.2 Row address strobe and bank activate command (/CS, /RAS = Low, /CAS, /WE = High) CLK The µPD45128xxx has four banks, each with 4,096 rows. This command activates the bank selected by BA0(A13) and BA1(A12) and a row address selected by A0 through A11. This command corresponds to a conventional DRAM’s /RAS falling. CKE H /CS /RAS /CAS /WE BA0(A13), BA1(A12) Precharge command A10 Row Add Row Fig.3 Precharge command (/CS, /RAS, /WE = Low, /CAS = High) CLK CKE This command begins precharge operation of the bank selected by /CS BA0(A13) and BA1(A12). When A10 is High, all banks are /RAS precharged, regardless of BA0(A13) and BA1(A12). When A10 is /CAS Low, only the bank selected by BA0(A13) and BA1(A12) is precharged. H /WE BA0(A13), BA1(A12) After this command, the µPD45128xxx can’t accept the activate command to the precharging bank during tRP (precharge to activate A10 (Precharge select) Add command period). This command corresponds to a conventional DRAM’s /RAS rising. Preliminary Data Sheet E0233N10 11 µPD45128441-I, 45128841-I, 45128163-I Write command Fig.4 Column address and write command (/CS, /CAS, /WE = Low, /RAS = High) CLK CKE If the mode register is in the burst write mode, this command sets the burst start address given by the column address to begin the burst /RAS write operation. The first write data in burst mode can input with this /CAS command with subsequent data on following clocks. H /CS /WE BA0(A13), BA1(A12) A10 Add Read command Col. Fig.5 Column address and read command (/CS, /CAS = Low, /RAS, /WE = High) CLK CKE Read data is available after /CAS latency requirements have been H /CS met. This command sets the burst start address given by the column /RAS address. /CAS /WE BA0(A13), BA1(A12) A10 Add CBR (auto) refresh command Fig.6 CBR (auto) refresh command (/CS, /RAS, /CAS = Low, /WE, CKE = High) CLK CKE This command is a request to begin the CBR (auto) refresh operation. The refresh address is generated internally. Before executing CBR (auto) refresh, all banks must be precharged. After this cycle, all banks will be in the idle (precharged) state and ready for a row activate command. /CS /RAS /CAS /WE BA0(A13), BA1(A12) During tRC period (from refresh command to refresh or activate command), the µPD45128xxx cannot accept any other command. 12 Col. Preliminary Data Sheet E0233N10 A10 Add H µPD45128441-I, 45128841-I, 45128163-I Self refresh entry command Fig.7 Self refresh entry command (/CS, /RAS, /CAS, CKE = Low, /WE = High) CLK CKE After the command execution, self refresh operation continues while /CS CKE remains low. When CKE goes high, the µPD45128xxx exits the /RAS self refresh mode. /CAS During self refresh mode, refresh interval and refresh operation are performed internally, so there is no need for external control. Before executing self refresh, all banks must be precharged. /WE BA0(A13), BA1(A12) A10 Add Burst stop command Fig.8 Burst stop command in Full Page Mode (/CS, /WE = Low, /RAS, /CAS = High) CLK This command can stop the current burst operation. CKE H /CS /RAS /CAS /WE BA0(A13), BA1(A12) A10 Add No operation Fig.9 No operation (/CS = Low, /RAS, /CAS, /WE = High) CLK CKE This command is not an execution command. No operations begin or terminate by this command. H /CS /RAS /CAS /WE BA0(A13), BA1(A12) A10 Add Preliminary Data Sheet E0233N10 13 µPD45128441-I, 45128841-I, 45128163-I 3. Simplified State Diagram Self Refresh LF SE xit Fe L SE MRS Mode Register Set REF IDLE CBR (Auto) Refresh CK E ACT CK E Power Down CKE ROW ACTIVE BS T BS e ite wit pre h ch arg Wr CKE Read ad WRITE CKE CKE WRITEA CKE Precharge PR E( Pre cha rge ter min atio n) Write CKE POWER ON Read READ n) atio min ter rge cha Pre E( PR WRITEA SUSPEND Au WRITE SUSPEND to W T Re h wit e ad rg Re cha pre to PRE Write Au e rit Active Power Down CKE CKE CKE READA CKE READ SUSPEND READA SUSPEND Precharge Automatic sequence Manual input 14 Preliminary Data Sheet E0233N10 µPD45128441-I, 45128841-I, 45128163-I 4. Truth Table 4.1 Command Truth Table Function Symbol CKE /CS n–1 n /RAS /CAS /WE BA1, A10 BA0 A11, A9 - A0 Device deselect DESL H × H × × × × × × No operation NOP H × L H H H × × × Burst stop BST H × L H H L × × × Read READ H × L H L H V L V Read with auto precharge READA H × L H L H V H V Write WRIT H × L H L L V L V Write with auto precharge WRITA H × L H L L V H V Bank activate ACT H × L L H H V V V Precharge select bank PRE H × L L H L V L × Precharge all banks PALL H × L L H L × H × Mode register set MRS H × L L L L L L V Remark H = High level, L = Low level, × = High or Low level (Don't care), V = Valid data input 4.2 DQM Truth Table Function Symbol CKE DQM n–1 n Data write / output enable ENB H × U L L Data mask / output disable MASK H × H Upper byte write enable / output enable ENBU H × × L Lower byte write enable / output enable ENBL H × × L Upper byte write inhibit / output disable MASKU H × H × Lower byte write inhibit / output disable MASKL H × × H Remark H = High level, L = Low level, × = High or Low level (Don't care) 4.3 CKE Truth Table Current state Function Symbol CKE n–1 n /CS /RAS /CAS /WE Address Activating Clock suspend mode entry H L × × × × × Any Clock suspend mode L L × × × × × Clock suspend Clock suspend mode exit L H × × × × × Idle CBR (auto) refresh command REF H H L L L H × Idle Self refresh entry SELF H L L L L H × Self refresh Self refresh exit L H L H H H × L H H × × × × Idle Power down entry H L × × × × × Power down Power down exit L H H × × × × L H L H H H × Remark H = High level, L = Low level, × = High or Low level (Don't care) Preliminary Data Sheet E0233N10 15 µPD45128441-I, 45128841-I, 45128163-I 4.4 Operative Command Table Note1 Current state Idle Row active Read Write 16 (1/3) /CS /RAS /CAS /WE H × × L H L H Address Command Action Notes × × DESL Nop or power down 2 H × × NOP or BST Nop or power down 2 L H BA, CA, A10 READ/READA ILLEGAL 3 3 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL L L H H BA, RA ACT Row activating L L H L BA, A10 PRE/PALL Nop L L L H × REF/SELF CBR (auto) refresh or self refresh 4 L L L L Op-Code MRS Mode register accessing H × × × × DESL Nop L H H × × NOP or BST Nop L H L H BA, CA, A10 READ/READA Begin read : Determine AP L H L L BA, CA, A10 WRIT/WRITA Begin write : Determine AP 5 L L H H BA, RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PALL Precharge 6 L L L H × REF/SELF ILLEGAL 5 L L L L Op-Code MRS ILLEGAL H × × × × DESL Continue burst to end → Row active L H H H × NOP Continue burst to end → Row active L H H L × BST Burst stop → Row active L H L H BA, CA, A10 READ/READA Terminate burst, new read : Determine AP 7 7, 8 L H L L BA, CA, A10 WRIT/WRITA Terminate burst, start write : Determine AP L L H H BA, RA ACT ILLEGAL L L H L BA, A10 PRE/PALL Terminate burst, precharging L L L H × REF/SELF ILLEGAL 3 L L L L Op-Code MRS ILLEGAL H × × × × DESL Continue burst to end → Write recovering L H H H × NOP Continue burst to end → Write recovering L H H L × BST Burst stop → Row active L H L H BA, CA, A10 READ/READA Terminate burst, start read : Determine AP 7, 8 L H L L BA, CA, A10 WRIT/WRITA Terminate burst, new write : Determine AP 7 L L H H BA, RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PALL Terminate burst, precharging 9 L L L H × REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL Preliminary Data Sheet E0233N10 µPD45128441-I, 45128841-I, 45128163-I (2/3) Current state /CS /RAS /CAS /WE Address Command Action Read with auto H × × × × DESL Continue burst to end → Precharging precharge L H H H × NOP Continue burst to end → Precharging Write with auto precharge Precharging Row activating Notes L H H L × BST ILLEGAL L H L H BA, CA, A10 READ/READA ILLEGAL 3 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 3 L L H H BA, RA ACT ILLEGAL 3 3 L L H L BA, A10 PRE/PALL ILLEGAL L L L H × REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL H × × × × DESL Continue burst to end → Write recovering with auto precharge L H H H × NOP Continue burst to end → Write recovering with auto precharge L H H L × BST ILLEGAL L H L H BA, CA, A10 READ/READA ILLEGAL 3 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 3 L L H H BA, RA ACT ILLEGAL 3 3 L L H L BA, A10 PRE/PALL ILLEGAL L L L H × REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL H × × × × DESL Nop → Enter idle after tRP L H H H × NOP Nop → Enter idle after tRP L H H L × BST ILLEGAL L H L H BA, CA, A10 READ/READA ILLEGAL 3 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 3 3 L L H H BA, RA ACT ILLEGAL L L H L BA, A10 PRE/PALL Nop → Enter idle after tRP L L L H × REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL H × × × × DESL Nop → Enter bank active after tRCD L H H H × NOP Nop → Enter bank active after tRCD L H H L × BST ILLEGAL L H L H BA, CA, A10 READ/READA ILLEGAL 3 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 3 L L H H BA, RA ACT ILLEGAL 3, 10 L L H L BA, A10 PRE/PALL ILLEGAL 3 L L L H × REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL Preliminary Data Sheet E0233N10 17 µPD45128441-I, 45128841-I, 45128163-I (3/3) Current state Write recovering Write recovering with auto precharge Refreshing /CS /RAS /CAS /WE Address Command Action Notes H × × × × DESL Nop → Enter row active after tDPL L H H H × NOP Nop → Enter row active after tDPL L H H L × BST Nop → Enter row active after tDPL L H L H BA, CA, A10 READ/READA Start read, Determine AP L H L L BA, CA, A10 WRIT/WRITA New write, Determine AP L L H H BA, RA ACT ILLEGAL 3 3 L L H L BA, A10 PRE/PALL ILLEGAL L L L H × REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL H × × × × DESL Nop → Enter precharge after tDPL 8 L H H H × NOP Nop → Enter precharge after tDPL L H H L × BST Nop → Enter precharge after tDPL L H L H BA, CA, A10 READ/READA ILLEGAL 3, 8 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 3 L L H H BA, RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PALL ILLEGAL L L L H × REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL H × × × × DESL Nop → Enter idle after tRC L H H × × NOP/BST Nop → Enter idle after tRC L H L × × READ/WRIT ILLEGAL L L H × × ACT/PRE/PALL ILLEGAL L L L × × REF/SELF/MRS ILLEGAL Mode register H × × × × DESL Nop → Enter idle after tRSC accessing L H H H × NOP Nop → Enter idle after tRSC L H H L × BST ILLEGAL L H L × × READ/WRIT ILLEGAL L L × × × ACT/PRE/PALL/ ILLEGAL REF/SELF/MRS Notes 1. 2. All entries assume that CKE was active (High level) during the preceding clock cycle. If all banks are idle, and CKE is inactive (Low level), µPD45128xxx will enter Power down mode. All input buffers except CKE will be disabled. 3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank. 4. If all banks are idle, and CKE is inactive (Low level), µPD45128xxx will enter Self refresh mode. All input buffers except CKE will be disabled. 5. Illegal if tRCD is not satisfied. 6. Illegal if tRAS is not satisfied. 7. Must satisfy burst interrupt condition. 8. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 9. Must mask preceding data which don't satisfy tDPL. 10. Illegal if tRRD is not satisfied. Remark H = High level, L = Low level, × = High or Low level (Don’t care), V = Valid data 18 Preliminary Data Sheet E0233N10 µPD45128441-I, 45128841-I, 45128163-I 4.5 Command Truth Table for CKE Current State CKE n–1 Self refresh Self refresh recovery Power down /CS /RAS /CAS /WE Address Action H × × × × × × INVALID, CLK (n – 1) would exit self refresh L H H × × × × Self refresh recovery L H L H H × × Self refresh recovery L H L H L × × ILLEGAL L H L L × × × ILLEGAL L L × × × × × Maintain self refresh H H H × × × × Idle after tRC H H L H H × × Idle after tRC H H L H L × × ILLEGAL H H L L × × × ILLEGAL H L H × × × × ILLEGAL H L L H H × × ILLEGAL H L L H L × × ILLEGAL H L L L × × × ILLEGAL H × × × × × L H H × × × L H L H H L L × × H H H × H H L H H L H H H H H L H L H H INVALID, CLK (n – 1) would exit power down × EXIT power down → Idle H × EXIT power down → Idle × × × × × Refer to operations in Operative Command Table H × × Refer to operations in Operative Command Table L H × Refer to operations in Operative Command Table L L L H × CBR (auto) Refresh L L L L Op-Code Refer to operations in Operative Command Table H × × × Refer to operations in Operative Command Table L H × × Refer to operations in Operative Command Table L L L H × L L L L H × H L L L L L Op-Code Refer to operations in Operative Command Table L × × × × × × Power down H × × × × × × Refer to operations in Operative Command Table L × × × × × × Power down Any state other than H H × × × × listed above H L × × × × × Begin clock suspend next cycle L H × × × × × Exit clock suspend next cycle L L × × × × × Maintain clock suspend All banks idle Row active Notes n Maintain power down mode Refer to operations in Operative Command Table Self refresh 1 1 1 Refer to operations in Operative Command Table 2 Notes 1. Self refresh can be entered only from the all banks idle state. Power down can be entered only from all banks idle or row active state. 2. Must be legal command as defined in Operative Command Table. Remark H = High level, L = Low level, × = High or Low level (Don't care) Preliminary Data Sheet E0233N10 19 µPD45128441-I, 45128841-I, 45128163-I 5. Initialization The synchronous DRAM is initialized in the power-on sequence according to the following. (1) To stabilize internal circuits, when power is applied, a 100 µs or longer pause must precede any signal toggling. (2) After the pause, all banks must be precharged using the Precharge command (The Precharge all banks command is convenient). (3) Once the precharge is completed and the minimum tRP is satisfied, the mode register can be programmed. After the mode register set cycle, tRSC (2 CLK minimum) pause must be satisfied as well. (4) Two or more CBR (Auto) refresh must be performed. Remarks 1. The sequence of Mode register programming and Refresh above may be transposed. 2. CKE and DQM must be held high until the Precharge command is issued to ensure data-bus Hi-Z. 20 Preliminary Data Sheet E0233N10 µPD45128441-I, 45128841-I, 45128163-I 6. Programming the Mode Register The mode register is programmed by the Mode register set command using address bits A11 through A0, BA0(A13) and BA1(A12) as data inputs. The register retains data until it is reprogrammed or the device loses power. The mode register has four fields; Options : A11 through A7, BA0(A13), BA1(A12) /CAS latency : A6 through A4 Wrap type : A3 Burst length : A2 through A0 Following mode register programming, no command can be issued before at least 2 CLK have elapsed. /CAS Latency /CAS latency is the most critical of the parameters being set. It tells the device how many clocks must elapse before the data will be available. The value is determined by the frequency of the clock and the speed grade of the device. 13.3 Relationship between Frequency and Latency shows the relationship of /CAS latency to the clock period and the speed grade of the device. Burst Length Burst Length is the number of words that will be output or input in a read or write cycle. After a read burst is completed, the output bus will become Hi-Z. The burst length is programmable as 1, 2, 4, 8 or full page. Wrap Type (Burst Sequence) The wrap type specifies the order in which the burst data will be addressed. This order is programmable as either “Sequential” or “Interleave”. The method chosen will depend on the type of CPU in the system. Some microprocessor cache systems are optimized for sequential addressing and others for interleaved addressing. 7.1 Burst Length and Sequence shows the addressing sequence for each burst length using them. Both sequences support bursts of 1, 2, 4 and 8. Additionally, sequence supports the full page length. Preliminary Data Sheet E0233N10 21 µPD45128441-I, 45128841-I, 45128163-I 7. Mode Register BA0 BA1 (A13) (A12) A11 0 0 0 BA0 BA1 (A13) (A12) A11 x x x BA0 BA1 (A13) (A12) A11 BA0 BA1 (A13) (A12) A11 x x x BA0 BA1 (A13) (A12) A11 0 0 0 A10 A9 A8 A7 0 0 0 1 A10 A9 A8 A7 x 1 0 0 A10 A9 A8 A7 1 0 A6 A5 A4 A3 A2 A1 A0 JEDEC Standard Test Set (refresh counter test) A6 A5 A4 LTMODE A6 A5 A3 A2 WT A4 A3 A1 A0 BL A2 A1 Burst Read and Single Write (for Write Through Cache) A0 Use in future A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 x x 1 1 V V V V V V V A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 LTMODE WT Vender Specific V = Valid x = Don’t care BL Mode Register Set Burst length Bits2-0 000 001 010 011 100 101 110 111 Wrap type 0 1 Latency mode WT = 0 1 2 4 8 R R R Full page Sequential Interleave Bits6-4 000 001 010 011 100 101 110 111 Remark R : Reserved Mode Register Set Timing CLK CKE /CS /RAS /CAS /WE A0 - A11, BA0(13), BA1(A12) Mode Register Set 22 Preliminary Data Sheet E0233N10 /CAS latency R R 2 3 R R R R WT = 1 1 2 4 8 R R R R µPD45128441-I, 45128841-I, 45128163-I 7.1 Burst Length and Sequence [Burst of Two] Starting address (column address A0, binary) Sequential addressing sequence (decimal) Interleave addressing sequence (decimal) 0 0, 1 0, 1 1 1, 0 1, 0 Starting address (column address A1 - A0, binary) Sequential addressing sequence (decimal) Interleave addressing sequence (decimal) 00 0, 1, 2, 3 0, 1, 2, 3 01 1, 2, 3, 0 1, 0, 3, 2 10 2, 3, 0, 1 2, 3, 0, 1 11 3, 0, 1, 2 3, 2, 1, 0 Starting address (column address A2 - A0, binary) Sequential addressing sequence (decimal) Interleave addressing sequence (decimal) 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 [Burst of Four] [Burst of Eight] Full page burst is an extension of the above tables of sequential addressing, with the length being 2,048 (for 32M ×4 device), 1,024 (for 16M ×8 device), and 512 (for 8M ×16 device). Preliminary Data Sheet E0233N10 23 µPD45128441-I, 45128841-I, 45128163-I 8. Address Bits of Bank-Select and Precharge Row A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA1 BA0 (A12) (A13) (Activate command) A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA1(A12) BA0(A13) Result Select Bank A “Activate” command Select Bank B “Activate” command 0 0 0 1 1 0 Select Bank C “Activate” command 1 1 Select Bank D “Activate” command BA1 BA0 (A12) (A13) A10 BA1(A12) BA0(A13) 0 0 0 0 1 0 0 0 1 0 1 1 1 x x (Precharge command) Result Precharge Bank A Precharge Bank B Precharge Bank C Precharge Bank D Precharge All Banks x : Don’t care 0 Col. A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 x BA1 BA0 (A12) (A13) 1 disables Auto-Precharge (End of Burst) enables Auto-Precharge (End of Burst) (/CAS strobes) BA1(A12) BA0(A13) 24 Preliminary Data Sheet E0233N10 Result enables Read/Write commands for Bank A enables Read/Write commands for Bank B 0 0 0 1 1 0 enables Read/Write commands for Bank C 1 1 enables Read/Write commands for Bank D µPD45128441-I, 45128841-I, 45128163-I 9. Precharge The precharge command can be issued anytime after tRAS (MIN.) is satisfied. Soon after the precharge command is issued, precharge operation performed and the synchronous DRAM enters the idle state after tRP is satisfied. The parameter tRP is the time required to perform the precharge. The earliest timing in a read cycle that a precharge command can be issued without losing any data in the burst is as follows. It is depending on the /CAS latency and clock cycle time. Burst length=4 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK /CAS latency = 2 Command PRE READ Q1 DQ Q2 Q3 Hi-Z Q4 /CAS latency = 3 Command READ PRE DQ Q1 Q2 Q3 Hi-Z Q4 (tRAS must be satisfied) In order to write all data to the memory cell correctly, the asynchronous parameter “tDPL” must be satisfied. The tDPL (MIN.) specification defines the earliest time that a precharge command can be issued. Minimum number of clocks is calculated by dividing tDPL (MIN.) with clock cycle time. In summary, the precharge command can be issued relative to reference clock that indicates the last data word is valid. In the following table, minus means clocks before the reference; plus means time after the reference. /CAS latency Read Write 2 –1 +tDPL (MIN.) 3 –2 +tDPL (MIN.) Preliminary Data Sheet E0233N10 25 µPD45128441-I, 45128841-I, 45128163-I 10. Auto Precharge During a read or write command cycle, A10 controls whether auto precharge is selected. A10 high in the Read or Write command (Read with Auto precharge command or Write with Auto precharge command), auto precharge is selected and begins automatically. The tRAS must be satisfied with a read with auto precharge or a write with auto precharge operation. In addition, the next activate command to the bank being precharged cannot be executed until the precharge cycle ends. In read cycle, once auto precharge has started, an activate command to the bank can be issued after tRP has been satisfied. In write cycle, the tDAL must be satisfied to issue the next activate command to the bank being precharged. The timing that begins the auto precharge cycle depends on both the /CAS latency programmed into the mode register and whether read or write cycle. 10.1 Read with Auto Precharge During a read cycle, the auto precharge begins one clock earlier (/CAS latency of 2) or two clocks earlier (/CAS latency of 3) the last data word output. Burst length = 4 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 CLK /CAS latency = 2 Command Auto precharge starts READA B Hi-Z DQ QB1 QB2 QB3 QB4 /CAS latency = 3 Command Auto precharge starts READA B Hi-Z DQ QB1 QB2 QB3 QB4 (tRAS must be satisfied) Remark READA means Read with Auto precharge 26 Preliminary Data Sheet E0233N10 µPD45128441-I, 45128841-I, 45128163-I 10.2 Write with Auto Precharge During a write cycle, the auto precharge starts at the timing that is equal to the value of the tDPL (MIN.) after the last data word input to the device. Burst length = 4 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK /CAS latency = 2 Auto precharge starts Command WRITA B Hi-Z DQ DB1 DB2 DB3 DB4 tDPL(MIN.) /CAS latency = 3 Command Auto precharge starts WRITA B Hi-Z DB1 DQ DB2 DB3 DB4 tDPL(MIN.) (tRAS must be satisfied) Remark WRITA means Write with Auto Precharge In summary, the auto precharge begins relative to a reference clock that indicates the last data word is valid. In the table below, minus means clocks before the reference; plus means after the reference. /CAS latency Read Write 2 –1 +tDPL (MIN.) 3 –2 +tDPL (MIN.) Preliminary Data Sheet E0233N10 27 µPD45128441-I, 45128841-I, 45128163-I 11. Read / Write Command Interval 11.1 Read to Read Command Interval During a read cycle, when new Read command is issued, it will be effective after /CAS latency, even if the previous read operation does not completed. READ will be interrupted by another READ. The interval between the commands is 1 cycle minimum. Each Read command can be issued in every clock without any restriction. Burst length = 4, /CAS latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 QA1 QB1 QB2 QB3 QB4 T8 T9 CLK Command READ A READ B Hi-Z DQ 1cycle 11.2 Write to Write Command Interval During a write cycle, when a new Write command is issued, the previous burst will terminate and the new burst will begin with a new Write command. WRITE will be interrupted by another WRITE. The interval between the commands is minimum 1 cycle. Each Write command can be issued in every clock without any restriction. Burst length = 4, /CAS latency = 2 T0 T1 T2 T3 T4 T5 DB2 DB3 DB4 T6 CLK Command WRITE A WRITE B DA1 DB1 Hi-Z DQ 1cycle 28 Preliminary Data Sheet E0233N10 T7 T8 µPD45128441-I, 45128841-I, 45128163-I 11.3 Write to Read Command Interval Write command and Read command interval is also 1 cycle. Only the write data before Read command will be written. The data bus must be Hi-Z at least one cycle prior to the first DOUT. Burst length = 4 T0 T1 T2 T3 T4 T5 T6 T7 QB1 QB2 QB3 QB4 QB1 QB2 QB3 T8 CLK /CAS latency = 2 Command WRITE A READ B Hi-Z DQ DA1 /CAS latency = 3 Command WRITE A READ B Hi-Z DQ DA1 Preliminary Data Sheet E0233N10 QB4 29 µPD45128441-I, 45128841-I, 45128163-I 11.4 Read to Write Command Interval During a read cycle, READ can be interrupted by WRITE. The Read and Write command interval is 1 cycle minimum. There is a restriction to avoid data conflict. The Data bus must be Hi-Z using DQM before WRITE. Burst length = 4 T0 T1 T2 T3 T4 T5 D2 D3 D4 T6 T7 T8 CLK Command READ WRITE DQM Hi-Z DQ D1 1cycle READ can be interrupted by WRITE. DQM must be High at least 3 clocks prior to the Write command. Burst length = 8 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 D2 D3 D2 D3 CLK /CAS latency = 2 Command READ WRITE DQM DQ Q1 Q2 Q3 D1 Hi-Z is necessary /CAS latency = 3 Command READ WRITE DQM DQ Q1 Q2 D1 Hi-Z is necessary 30 Preliminary Data Sheet E0233N10 µPD45128441-I, 45128841-I, 45128163-I 12. Burst Termination There are two methods to terminate a burst operation other than using a Read or a Write command. One is the burst stop command and the other is the precharge command. 12.1 Burst Stop Command During a read cycle, when the burst stop command is issued, the burst read data are terminated and the data bus goes to Hi-Z after the /CAS latency from the burst stop command. Burst length = X T0 T1 T2 T3 T4 T5 T6 T7 CLK Command READ BST /CAS latency = 2 Hi-Z DQ Q1 Q2 Q3 Q1 Q2 /CAS latency = 3 Hi-Z DQ Q3 Remark BST: Burst stop command During a write cycle, when the burst stop command is issued, the burst write data are terminated and data bus goes to Hi-Z at the same clock with the burst stop command. Burst length = X T0 T1 T2 T3 T4 T5 T6 T7 CLK Command WRITE BST /CAS latency = 2, 3 DQ Hi-Z D1 D2 D3 D4 Remark BST: Burst stop command Preliminary Data Sheet E0233N10 31 µPD45128441-I, 45128841-I, 45128163-I 12.2 Precharge Termination 12.2.1 Precharge Termination in READ Cycle During a read cycle, the burst read operation is terminated by a precharge command. When the precharge command is issued, the burst read operation is terminated and precharge starts. The same bank can be activated again after tRP from the precharge command. To issue a precharge command, tRAS must be satisfied. When /CAS latency is 2, the read data will remain valid until one clock after the precharge command. Burst length = X, /CAS latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 CLK READ Command PRE ACT Hi-Z DQ Q1 Q2 Q3 Q4 tRP (tRAS must be satisfied) When /CAS latency is 3, the read data will remain valid until two clocks after the precharge command. Burst length = X, /CAS latency = 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK Command READ ACT PRE Hi-Z DQ Q1 Q2 Q3 Q4 tRP (tRAS must be satisfied) 32 Preliminary Data Sheet E0233N10 µPD45128441-I, 45128841-I, 45128163-I 12.2.2 Precharge Termination in WRITE Cycle During a write cycle, the burst write operation is terminated by a precharge command. When the precharge command is issued, the burst write operation is terminated and precharge starts. The same bank can be activated again after tRP from the precharge command. To issue a precharge command, tRAS must be satisfied. When /CAS latency is 2, the write data written prior to the precharge command will be correctly stored. However, invalid data may be written at the same clock as the precharge command. To prevent this from happening, DQM must be high at the same clock as the precharge command. This will mask the invalid data. Burst length = X, /CAS latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 CLK Command WRITE ACT PRE DQM Hi-Z DQ D1 D2 D3 D4 D5 tRP (tRAS must be satisfied) When /CAS latency is 3, the write data written prior to the precharge command will be correctly stored. However, invalid data may be written at the same clock as the precharge command. To prevent this from happening, DQM must be high at the same clock as the precharge command. This will mask the invalid data. Burst length = X, /CAS latency = 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK Command WRITE ACT PRE DQM Hi-Z DQ D1 D2 D3 D4 D5 tRP (tRAS must be satisfied) Preliminary Data Sheet E0233N10 33 µPD45128441-I, 45128841-I, 45128163-I 13. Electrical Specifications • All voltages are referenced to VSS (GND). • After power up, wait more than 100 µs and then, execute Power on sequence and CBR (auto) Refresh before proper device operation is achieved. Absolute Maximum Ratings Parameter Symbol Voltage on power supply pin relative to GND Condition Rating Unit VCC, VCCQ −0.5 to +4.6 V Voltage on any pin relative to GND VT −0.5 to +4.6 V Short circuit output current IO 50 mA Power dissipation PD 1 W Operating ambient temperature TA −40 to + 85 °C Storage temperature Tstg −55 to + 125 °C Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Supply voltage Symbol Condition VCC, VCCQ High level input voltage VIH Low level input voltage VIL Operating ambient temperature TA MIN. TYP. MAX. Unit 3.0 3.3 3.6 V Note1 2.0 VCC+0.3 V +0.8 V 85 °C Note2 −0.3 −40 Notes 1. VIH (MAX.) = VCC + 1.5 V (Pulse width ≤ 5 ns) 2. VIL (MIN.) = –1.5 V (Pulse width ≤ 5 ns) Pin Capacitance (TA = 25 °C, f = 1 MHz) Parameter Input capacitance Data input / output capacitance 34 Symbol Condition MIN. TYP. MAX. Unit pF CI1 CLK 2.5 3.5 CI2 A0 - A11, BA0(A13), BA1(A12), CKE, /CS, /RAS, /CAS, /WE, DQM, UDQM, LDQM 2.5 3.8 CI/O DQ0 - DQ15 4 6.5 Preliminary Data Sheet E0233N10 pF µPD45128441-I, 45128841-I, 45128163-I DC Characteristics 1 (Recommended Operating Conditions unless otherwise noted) Parameter Symbol Test condition /CAS Grade Operating current ICC1 Burst length = 1, CL = 2 tRC ≥ tRC (MIN.), Io = 0 mA, One bank active CL = 3 Precharge standby current in power down mode Precharge standby current ICC2P ICC2PS ICC2N in non power down mode Maximum ×4 latency ×8 -A75 100 100 110 -A80 100 100 110 -A10 100 100 110 -A75 105 105 115 -A80 100 100 110 -A10 100 100 110 1 1 1 CKE ≤ VIL (MAX.), tCK = 15 ns Unit Notes mA 1 ×16 CKE ≤ VIL (MAX.), tCK = ∞ 1 1 1 CKE ≥ VIH (MIN.), tCK = 15 ns, /CS ≥ VIH (MIN.), 20 20 20 8 8 8 5 5 5 mA mA Input signals are changed one time during 30 ns. ICC2NS CKE ≥ VIH (MIN.), tCK = ∞, Input signals are stable. Active standby current in power down mode Active standby current ICC3P ICC3PS ICC3N in non power down mode CKE ≤ VIL (MAX.), tCK = 15 ns CKE ≤ VIL (MAX.), tCK = ∞ 4 4 4 CKE ≥ VIH (MIN.), tCK = 15 ns, /CS ≥ VIH (MIN.), 30 30 30 20 20 20 -A75 105 120 145 -A80 105 120 145 -A10 85 95 110 -A75 140 155 185 -A80 130 145 175 -A10 110 125 140 mA mA Input signals are changed one time during 30 ns. ICC3NS CKE ≥ VIH (MIN.), tCK = ∞ , Input signals are stable. Operating current ICC4 (Burst mode) tCK ≥ tCK (MIN.), Io = 0 mA, CL = 2 All banks active CL = 3 CBR (auto) refresh current ICC5 tRC ≥ tRC (MIN.) CL = 2 CL = 3 Self refresh current ICC6 mA 2 mA 3 -A75 230 230 230 -A80 230 230 230 -A10 230 230 230 -A75 240 240 240 -A80 230 230 230 -A10 230 230 230 -** 2 2 2 mA -**L 0.8 0.8 0.8 mA CKE ≤ 0.2 V Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC1 is measured condition that addresses are changed only one time during tCK (MIN.). 2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC4 is measured condition that addresses are changed only one time during tCK (MIN.). 3. ICC5 is measured on condition that addresses are changed only one time during tCK (MIN.). Preliminary Data Sheet E0233N10 35 µPD45128441-I, 45128841-I, 45128163-I DC Characteristics 2 (Recommended Operating Conditions unless otherwise noted) Parameter Symbol Test condition MIN. TYP. MAX. Unit 0 ≤ V ≤ V Q, V Q = V All other pins not under test = 0 V −1.0 +1.0 µA IO (L) 0 ≤ VO ≤ VCCQ, DOUT is disabled −1.5 +1.5 µA High level output voltage VOH IO = −4 mA 2.4 Low level output voltage VOL IO = +4 mA Input leakage current I Output leakage current I (L) I CC CC CC V 0.4 V AC Characteristics (Recommended Operating Conditions unless otherwise noted) Test Conditions Parameter AC high level input voltage / low level input voltage Input timing measurement reference level Value Unit 2.4 / 0.4 V 1.4 V 1 ns 1.4 V Transition time (Input rise and fall time) Output timing measurement reference level tCK tCH CLK 2.4 V 1.4 V 0.4 V tSETUP tHOLD Input 2.4 V 1.4 V 0.4 V tAC tOH Output 36 Preliminary Data Sheet E0233N10 tCL Note µPD45128441-I, 45128841-I, 45128163-I Synchronous Characteristics Parameter Clock cycle time Access time from CLK Symbol -A75 -A80 MIN. MAX. -A10 Unit MIN. MAX. MIN. MAX. Note /CAS latency = 3 tCK3 7.5 (133 MHz) 8 (125 MHz) 10 (100 MHz) ns /CAS latency = 2 tCK2 10 (100 MHz) 10 (100 MHz) 13 (77 MHz) ns /CAS latency = 3 tAC3 5.4 6 6 ns 1 /CAS latency = 2 tAC2 6 6 7 ns 1 CLK high level width t CH 2.5 3 3 ns CLK low level width tCL 2.5 3 3 ns Data-out hold time tOH 2.7 2.7 2.7 ns Data-out low-impedance time tLZ 0 Data-out high-impedance time /CAS latency = 3 tHZ3 2.7 5.4 2.7 0 6 2.7 0 6 ns /CAS latency = 2 tHZ2 2.7 6 2.7 6 2.7 7 ns Data-in setup time tDS 1.5 2 2 ns Data-in hold time t DH 0.8 1 1 ns Address setup time tAS 1.5 2 2 ns Address hold time tAH 0.8 1 1 ns 1 ns CKE setup time tCKS 1.5 2 2 ns CKE hold time tCKH 0.8 1 1 ns CKE setup time (Power down exit) tCKSP 1.5 2 2 ns Command (/CS, /RAS, /CAS, /WE, DQM) setup time Command (/CS, /RAS, /CAS, /WE, DQM) hold time tCMS 1.5 2 2 ns tCMH 0.8 1 1 ns Note 1. Output load Z = 50 Ω Output 50 pF Preliminary Data Sheet E0233N10 37 µPD45128441-I, 45128841-I, 45128163-I Asynchronous Characteristics Parameter Symbol -A75 MIN. ACT to REF/ACT command period (operation) -A80 MAX. MIN. -A10 MAX. 70 MIN. Unit MAX. tRC 67.5 REF to REF/ACT command period (refresh) tRC1 67.5 ACT to PRE command period tRAS 45 70 PRE to ACT command period tRP 20 20 20 ns Delay time ACT to READ/WRITE command tRCD 20 20 20 ns 70 120,000 48 ns 70 120,000 50 ns 120,000 ns ACT (one) to ACT (another) command period t RRD 15 16 20 ns Data-in to PRE command period tDPL 15 15 15 ns Data-in to ACT (REF) command period /CAS latency = 3 tDAL3 1CLK +22.5 1CLK +20 1CLK +20 ns (Auto precharge) /CAS latency = 2 tDAL2 1CLK +20 1CLK +20 1CLK +20 ns Mode register set cycle time Transition time Refresh time (4,096 refresh cycles) tRSC 2 tT 0.5 tREF 2 30 0.5 64 2 30 64 1 Note 1 CLK 30 ns 64 ms Note 1. The –A75 grade device can satisfy the tDAL3 spec of 1CLK+20 ns for up to and including 125MHz operation. 38 Preliminary Data Sheet E0233N10 13.1 AC Parameters for Read Timing (Manual Precharge, Burst Length = 4, /CAS Latency = 3) ;;;;;; ;;;; ;; ;; ;; ; ;; ; ; ;; ; ;; ;; ; ;; ; ; ;; ; ;; ;; ; ;; ; ; ;; ; ; ;; ;; ;; ; ;; ; ; ; ; ;; ; ;; ; ; ; ; ;; ; ;; ; ; ; ; ;; ; ;; ; ; ;; ; ; ;; ; ;; ; ; ;; ; ; ;; ; ;; ; ; ;; ; ;; ; ;; ; ; ;; ; ;; ; ;; ; ; ;; ; ;; ; ;; ; ; ;; ; ;; ; ;; ; ; ;; ; ;; ; ;; ; ; ;; ; ;; ;; ; ; ; ;; ; ;;; ;; ;; ; ; ;; ; T0 tCK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 CLK tCH tCL CKE tCKH tCKS tCMS tCMH /CS /RAS /CAS ;;;; ;;;; BA0 BA1 A10 ADD tAS tAH DQM L tAC DQ tAC tAC tAC tHZ Hi-Z tLZ tRCD tOH tOH tRAS tOH tOH tRP tRC Activate Command for Bank A Read Command for Bank A Precharge Command for Bank A Activate Command for Bank A 39 µPD45128441-I, 45128841-I, 45128163-I Preliminary Data Sheet E0233N10 /WE 40 AC Parameters for Read Timing (Auto Precharge, Burst Length = 4, /CAS Latency = 3) T0 tCK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 CLK ;;;;;;;;;; ;;;;;;;;;; ; ; ; ; ; ; ;;;;;;;;;;;; ;;;;;; ;;;;; ;;;;;; ;;; ;;;;;;;;; ;;;;;;;; ;;;;;;;;;; tCH tCL CKE tCKS Auto Precharge Start for Bank C tCMS tCMH tCKH /CS /RAS /CAS BA0 A10 ADD tAS tAH DQM ;; ;; ; BA1 L tAC DQ tAC tAC tAC tHZ Hi-Z tRCD tLZ tOH tOH tOH tOH tRAS tRRD tRC Activate Command for Bank C Read with Auto Precharge Command for Bank C Activate Command for Bank D Activate Command for Bank C µPD45128441-I, 45128841-I, 45128163-I Preliminary Data Sheet E0233N10 /WE 13.2 AC Parameters for Write Timing (Burst Length = 4, /CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK ;;;;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;;;;;; ; ; ; ; ; ; ; ;;;;;; ;; ;;;;;; ;;;; ;;;; ;;;;;;;;;; CKE Auto Precharge Start for Bank C tCKS tCMS tCMH tCKH /RAS /CAS Preliminary Data Sheet E0233N10 /WE BA0 BA1 A10 ADD tAS tAH DQM L tDS tDH DQ Hi-Z tRCD tDAL tRC tRRD tRCD tDPL tRP tRAS tRC 41 Activate Command for Bank C Write with Activate Auto Precharge Command Command for Bank B for Bank C Write Command for Bank B Activate Precharge Command Command for Bank C for Bank B Activate Command for Bank B µPD45128441-I, 45128841-I, 45128163-I ;; ;; ;; /CS µPD45128441-I, 45128841-I, 45128163-I 13.3 Relationship between Frequency and Latency Speed version -75 -80 -10 Clock cycle time [ns] 7.5 10 8 10 10 13 Frequency [MHz] 133 100 125 100 100 77 /CAS latency 3 2 3 2 3 2 [tRCD] 3 2 3 2 2 2 /RAS latency (/CAS latency + [tRCD]) 6 4 6 4 5 4 [tRC] 9 7 9 7 7 6 [tRC1] 9 7 9 7 8 6 [tRAS] 6 5 6 5 5 4 [tRRD] 2 2 2 2 2 2 [tRP] 3 2 3 2 2 2 [tDPL] 2 2 2 2 2 2 [tDAL] 4 3 4 3 3 3 [tRSC] 2 2 2 2 2 2 42 Preliminary Data Sheet E0233N10 13.4 Mode Register Set (Burst Length = 4, /CAS Latency = 2) tRSC H CKE BA1 A10 ADD ADDRESS KEY DQM DQ Hi-Z Mode Register Set Command 43 tRP Activate Command is valid µPD45128441-I, 45128841-I, 45128163-I ;;; ;;; ;; ;; ; ;;; ; ;; ;; ; ;; ; ;;; ; ;; ;; ; ;; ; ;;; ; ;; ;; ; ;; ; ;;; ; ;; ;; ; ;; ; ;;; ; ;; ;; ; ;; ; ;;; ; ;; ;; ; ;; ; ;;; ; ;; ;; ; ;; ; ;;; ; ;; ;; ; ;; ; ;;; ; ;; ;; ; ;; ; ;;; ; ;; ;; ; ;; ; ;;; ; ;; ;; ; ;; ; ;;; ; ;; ;; ; ;; ; ;;; ; ;; ;; ; ;; ;; ;; ;; ; ;;; ; ; ;;; ; ;; ;; ; ;; ; ;;; ;; ; ;; ;; ; ;; ; ;;; ; ;; ;; ; ;; ; /WE Preliminary Data Sheet E0233N10 BA0 Precharge All Banks Command T21 T20 T19 T18 T17 T16 T15 T14 T13 T12 T11 T10 T9 T8 T7 T6 T5 T4 T3 T2 T1 T0 CLK 2 CLK (MIN.) /CS /RAS /CAS 44 13.5 Power On Sequence and CBR (Auto) Refresh CLK Clock cycle is necessary CKE tRSC 2 refresh cycles are necessary ;;;; ;;;; ;; ; ;; ;; ; ; ;; ; ; ; ;; ; ;; ;; ; ; ; ;; ; ;; ; ;; ; ; ;; ; ;; ; ;; ; ; ;; ; ;; ; ;; ; ; ;; ; ; ;; ;; ; ; ;; ; ;; ;; ; ; ; ;; ; ;; ; ;; ; ; ;; ; ;; ; ;; ; ; ;; ; ;; ; ;; ; ; ;; ; ;; ; ;; ;; ;; ; ; ; ;; ; ; ; ;; ;; ; ; ;; ; ; ; ;; ; ;; ;; ;; ; ;; ; ; ;; ; ;; ; ;; ; ; ;; ; High level is necessary /CS /RAS /CAS BA0 BA1 A10 ADDRESS KEY ADD DQM High level is necessary Hi-Z DQ Precharge All Banks Command is necessary Mode Register Set Command is necessary tRP CBR (Auto) Refresh Command is necessary CBR (Auto) Refresh Command is necessary tRC1 Activate Command tRC1 µPD45128441-I, 45128841-I, 45128163-I Preliminary Data Sheet E0233N10 /WE 13.6 /CS Function (Burst Length = 4, /CAS Latency = 3) Only /CS signal needs to be issued at minimum rate T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H /CS /RAS /WE BA0 L BA1 L A10 RAa ADD RAa DQM CAa CAb L Hi-Z QAa1 DQ Activate Command for Bank A Read Command for Bank A QAa2 QAa3 QAa4 DAb1 Write Command for Bank A DAb2 DAb3 DAb4 Precharge Command for Bank A 45 µPD45128441-I, 45128841-I, 45128163-I Preliminary Data Sheet E0233N10 /CAS 46 13.7 Clock Suspension during Burst Read (using CKE Function) (1/2) (Burst Length = 4, /CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE ;;; ;; ;;; ;; ; ;; ; ;; ; ;; ;; ; ;; ; ;; ; ;; ;; ; ;; ; ;; ; ;; ;; ; ;; ; ;; ; ;; ;; ; ;; ; ;; ; ;; ;; ; ;; ; ;; ; ;; ;; ; ;; ; ;; ; ;; ;; ; ;; ; ;; ; ;; ;; ; ;; ; ;; ; ;; ;; ; ;; ; ;; ; ;; ;; ; ;; ; ;; ; ;; ;; ; ;; ; ;; ; ;; ;; ; ;; ; ;; ; ;; ;; ; ;; ; ; ;; ; ;; ;; ; ;; ;; ; ; ;; ; ;; ; ;; ;; ; ; ;; ; ; ;; ;; ;; ; ; ;; ; ;; /CS /RAS /CAS BA0 BA1 A10 RAa ADD RAa DQM CAa L Hi-Z QAa1 DQ Activate Command for Bank A Read Command for Bank A QAa2 QAa3 1-CLOCK SUSPENDED QAa4 2-CLOCK SUSPENDED 3-CLOCK Hi-Z (turn off) SUSPENDED at the end of burst µPD45128441-I, 45128841-I, 45128163-I Preliminary Data Sheet E0233N10 /WE Clock Suspension during Burst Read (using CKE Function) (2/2) (Burst Length = 4, /CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE ;;; ;; ;;; ;; ; ; ;; ; ;; ;; ;; ; ; ;; ; ;; ;; ;; ; ; ;; ; ;; ;; ;; ; ; ;; ; ;; ;; ;; ; ; ;; ; ;; ;; ;; ; ; ;; ; ;; ;; ;; ; ; ;; ; ;; ;; ;; ; ; ;; ; ;; ;; ;; ; ; ;; ; ;; ;; ;; ; ; ;; ; ;; ;; ;; ; ; ;; ; ;; ;; ;; ; ; ;; ; ;; ;; ;; ; ; ; ; ;; ;; ;; ;; ; ;; ; ;; ;; ;; ; ; ; ; ; ;; ; ;; ;; ;; ; ;; ; ;; ;; ; ;; ; ; ;; ; ; ;; ;; ; ;; /CS /RAS /CAS BA0 BA1 A10 RAa ADD RAa DQM CAa L Hi-Z QAa1 DQ Activate Command for Bank A Read Command for Bank A QAa2 1-CLOCK SUSPENDED QAa3 QAa4 2-CLOCK SUSPENDED 3-CLOCK SUSPENDED Hi-Z (turn off) at the end of burst 47 µPD45128441-I, 45128841-I, 45128163-I Preliminary Data Sheet E0233N10 /WE 48 13.8 Clock Suspension during Burst Write (using CKE Function) (1/2) (Burst Length = 4, /CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE ;;;;; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; /CS /RAS /CAS BA0 BA1 A10 RAa ADD RAa DQM DQ CAa L Hi-Z Activate Command for Bank A DAa1 DAa2 Write 1-CLOCK Command SUSPENDED for Bank A DAa3 2-CLOCK SUSPENDED DAa4 3-CLOCK SUSPENDED µPD45128441-I, 45128841-I, 45128163-I Preliminary Data Sheet E0233N10 /WE Clock Suspension during Burst Write (using CKE Function) (2/2) (Burst Length = 4, /CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE ;; ;; ;; ;; ;; ; ; ;; ;; ; ;; ;; ; ; ;; ;; ; ;; ;; ; ; ;; ;; ; ;; ;; ; ; ;; ;; ; ;; ;; ; ; ;; ;; ; ;; ;; ; ; ;; ;; ; ;; ;; ; ; ;; ;; ; ;; ;; ; ;; ; ;; ;; ; ;; ;; ; ;; ; ;; ;; ; ;; ;; ; ;; ; ;; ;; ; ;; ;; ; ;; ; ;; ;; ; ;; ;; ; ;; ;; ; ;; ;; ; ;; ;; ; ; ; ; ;; ;; ;; ;; ;; ; ;; ;; ;; ;; ; ; ; ; ;; ; ; ; ;; ;; ;; ;; ; ;; ;; ;; ; ;; ; ; ; ;; ; ;; ; ;; ; ;; /CS /RAS /CAS BA0 BA1 A10 RAa ADD RAa DQM CAa L Hi-Z DQ DAa1 Activate Command for Bank A DAa2 Write 1-CLOCK Command SUSPENDED for Bank A DAa3 2-CLOCK SUSPENDED DAa4 3-CLOCK SUSPENDED 49 µPD45128441-I, 45128841-I, 45128163-I Preliminary Data Sheet E0233N10 /WE 50 13.9 Power Down Mode and Clock Mask (Burst Length = 4, /CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK tCKSP tCKSP CKE ;;; ;;;;;;;;; ;; ; ;;;;;;;;; ;; ; ;;;;;;;;; ;; ; ;;;;;;;;; ;; ; ;;;;;;;;; ; ; ;;;;;;;;; ;; ; ;;;;;;;;; ; ;;;;;;;; ;;; VALID /CS /RAS /CAS BA0 BA1 A10 RAa ADD RAa DQM CAa L Hi-Z QAa1 QAa2 QAa3 DQ Activate Command for Bank A QAa4 Read Command for Bank A Power Down Mode Entry Power Down Mode Exit ACTIVE STANDBY Precharge Command for Bank A Clock Mask Start Clock Mask End Power Down Mode Entry Power Down Mode Exit PRECHARGE STANDBY µPD45128441-I, 45128841-I, 45128163-I Preliminary Data Sheet E0233N10 /WE 13.10 CBR (Auto) Refresh T0 T1 T2 T3 T4 T5 T6 Tn Tn + 1 Tn + 2 Tn + 3 Tn + 4 Tn + 5 Tn + 6 Tm Tm + 1 Tm + 2 Tm + 3 Tm + 4 Tm + 5 Tm + 6 Tm + 7 CLK CKE H ;;;; ;;;;; ;;; ;; ; ;; ;; ; ;; ; ;; ;; ; ;;; ;;; ; ;; ;; ; ;; ;;; ;; ; ;; ;; ; ;;; ; ;; ;; ; ;; ;;; ; ;; ;; ; ;; ;;; ; ;; ;; ; ;; ;;; ; ;; ;; ; ;; ; ;;; ;; ;; ; ;; ;;; ; ;; ;; ; ;; ;;; ; ;; ;; ; ;; ;;; ; ;; ;; ; ;; ;;; ; ;; ;; ; ;; ;;; ;; ; ;; ; ;; ;; ; ;; ; ;;; ;; ;;; ;; ;; ; ;; ;; ; ;;; ;; ; ;; ;; ; /CS /RAS /CAS BA0 BA1 A10 ADD DQM DQ L Hi-Z Q1 Precharge CBR (Auto) Refresh Command (if necessary) 51 tRP CBR (Auto) Refresh tRC1 Activate Command tRC1 Read Command µPD45128441-I, 45128841-I, 45128163-I Preliminary Data Sheet E0233N10 /WE 52 13.11 Self Refresh (Entry and Exit) T1 T2 T3 T4 Tn Tn + 1 Tn + 2 Tm Tm + 1 Tk Tk + 1 Tk + 2 Tk + 3 Tk + 4 ;;;; ;;;; ;; ;; ;; ; ; ;; ; ; ;; ;; ; ; ;; ; ; ; ;; ;; ; ; ;; ; ;;; ; ;; ; ; ;; ; ;;; ; ;; ; ; ;; ; ;;; ; ;; ; ; ;; ; ;;; ;; ; ; ; ;; ; ; ;; ;; ; ; ;; ; ;; ; ;; ; ; ;; ; ;;; ; ;; ; ; ;; ; ;;; ; ;; ; ; ;; ; ;;;;; ; ;; ; ; ;; ; ;; ; ; ;; ; ; ;; ; ;; ; ;; ; ; ;; ; ;; ; ;; ; ; ;; ; ;; ; ;; ; ; ;; ; T0 CLK CKE /CS /RAS /CAS BA0 BA1 A10 ADD DQM L Hi-Z DQ Precharge Command (if necessary) Self Refresh Entry Self Refresh Self Refresh Entry Exit (or Activate Command) Self Refresh Exit Activate Command Next Clock Enable Next Clock Enable tRP tRC1 tRC1 µPD45128441-I, 45128841-I, 45128163-I Preliminary Data Sheet E0233N10 /WE 13.12 Random Column Read (Page with Same Bank) (1/2) (Burst Length = 4, /CAS Latency = 2) T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 ;;; ;;;; ;; ;; ; ; ; ;; ; ; ; ; ;; ; ; ; ;; ;; ; ; ; ; ;; ; ; ;; ; ; ; ; ;; ; ; ; ; ; ;; ; ; ;; ; ; ;; ; ; ; ;; ; ; ;; ; ; ; ;; ; ; ;; ; ; ; ;; ; ; ; ; ;; ;; ; ; ; ; ; ; ;; ; ; ;; ; ;; ; ; ; ; ;; ; ; ;; ; ; ;; ; ; ; ;; ; ; ;; ; ; ; ;; ; ; ;; ; ; ; ;; ; ; ;; ; ; ; ;; ; ; ; ;; ; T0 CLK CKE H /CS /RAS /CAS BA0 BA1 A10 RAa ADD RAa DQM RAd CAa CAb CAc RAd CAd L Hi-Z QAa1 DQ Activate Command for Bank A Read Command for Bank A QAa2 QAa3 Read Command for Bank A QAa4 QAb1 Read Command for Bank A QAb2 QAc1 QAc2 QAc3 Precharge Command for Bank A QAc4 Activate Command for Bank A QAd1 Read Command for Bank A QAd2 QAd3 53 µPD45128441-I, 45128841-I, 45128163-I Preliminary Data Sheet E0233N10 /WE 54 Random Column Read (Page with Same Bank) (2/2) (Burst Length = 4, /CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 ;;;;;; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; CLK H CKE /CS /RAS /CAS BA0 BA1 A10 RAa ADD RAa DQM RAa CAa CAb CAc RAa CAa Activate Command for Bank A Read Command for Bank A L Hi-Z QAa1 QAa2 DQ Activate Command for Bank A Read Command for Bank A Read Command for Bank A QAa3 QAa4 Read Command for Bank A QAb1 QAb2 QAc1 QAc2 Precharge Command for Bank A QAc3 QAc4 µPD45128441-I, 45128841-I, 45128163-I Preliminary Data Sheet E0233N10 /WE 13.13 Random Column Write (Page with Same Bank) (1/2) (Burst Length = 4, /CAS Latency = 2) T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 ;;; ;;;; ;; ;; ; ; ;; ; ;; ; ; ;; ; ; ;; ; ;; ; ; ;; ; ; ; ; ; ;; ;; ; ;; ; ; ;; ;; ; ;; ; ; ; ; ; ;; ; ; ;; ; ;; ; ; ; ; ;; ;; ; ;; ; ; ;; ;; ; ;; ; ; ; ; ;; ; ;; ; ; ;; ; ; ; ; ; ; ;; ;; ;; ; ; ; ; ;; ; ; ; ; ;; ;; ; ; ;; ; ; ; ; ;; ;; ; ; ;; ; ; ; ; ;; ;; ; ;; ; ; ; ;; ; ;; ;; ; ; ; ;; ; ;; ; ;; ; ; ; ;; ; ;; ; ; ;; ; T0 CLK CKE H /CS /RAS /CAS BA0 BA1 A10 RDa ADD RDa DQM DQ RDd CDa CDb CDc RDd CDd L Hi-Z Activate Command for Bank D DDa1 DDa2 Write Command for Bank D DDa3 DDa4 DDb1 DDb2 Write Command for Bank D DDc1 Write Command for Bank D DDc2 DDc3 DDc4 Precharge Command for Bank D DDd1 DDd2 Activate Command for Bank D Write Command for Bank D DDd3 DDd4 55 µPD45128441-I, 45128841-I, 45128163-I Preliminary Data Sheet E0233N10 /WE 56 Random Column Write (Page with Same Bank) (2/2) (Burst Length = 4, /CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 ;;;;;; ;;;;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;;;;; CLK CKE H /CS /RAS /CAS BA0 BA1 A10 RDa ADD RDa DQM DQ RDd CDa CDb CDc RDd CDd L Hi-Z Activate Command for Bank D DDa1 Write Command for Bank D DDa2 DDa3 DDa4 DDb1 DDb2 Write Command for Bank D DDc1 Write Command for Bank D DDc2 DDc3 DDc4 Precharge Command for Bank D DDd1 DDd2 Activate Command for Bank D Write Command for Bank D µPD45128441-I, 45128841-I, 45128163-I Preliminary Data Sheet E0233N10 /WE 13.14 Random Row Read (Ping-Pong Banks) (1/2) (Burst Length = 8, /CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 ;;;;;; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; CLK CKE H /CS /RAS /CAS BA0 BA1 A10 RDa ADD RDa DQM DQ RDb RBa CDa RBa CBa RDb CDb L Hi-Z Activate Command for Bank D QDa1 QDa2 QDa3 QDa4 QDa5 QDa6 QDa7 QDa8 QBa1 QBa2 QBa3 QBa4 Read Command for Bank D Activate Command for Bank B Read Command for Bank B 57 Precharge Command for Bank D Activate Command for Bank D QBa5 QBa6 QBa7 QBa8 Read Command for Bank D µPD45128441-I, 45128841-I, 45128163-I Preliminary Data Sheet E0233N10 /WE 58 Random Row Read (Ping-Pong Banks) (2/2) (Burst Length = 8, /CAS Latency = 3) T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 ;; ;;;; ;; ;;; ; ;; ;; ;; ; ; ;; ; ; ; ; ; ; ;; ;; ; ;; ; ; ; ;; ;; ; ;; ; ; ; ; ; ;; ;; ; ;; ; ; ; ;; ;; ; ; ;; ; ; ; ;; ; ; ;; ;; ; ;; ; ; ;; ;; ;; ; ; ;; ; ; ;; ;; ; ; ;; ; ; ; ;; ;; ; ; ;; ; ; ; ;; ;; ; ; ;; ; ; ; ;; ;; ; ; ;; ; ; ; ;; ;; ; ; ;; ; ; ; ; ;; ;; ;; ; ; ; ; ;; ; ;; ; ;; ; ; ; ;; ; ;; ; ; ; ;; ; ; ;; ; ;; ; ;; ; ; T0 CLK CKE H /CS /RAS /CAS BA0 BA1 A10 RBa ADD RBa DQM DQ RBb RAa CBa RAa CAa RBb CBb L Hi-Z Activate Command for Bank B QBa1 QBa2 Read Command for Bank B QBa3 QBa4 QBa5 QBa6 QBa7 QBa8 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 Activate Command for Bank A Read Command for Bank A Precharge Command for Bank B Activate Command for Bank B Read Command for Bank B Precharge Command for Bank A µPD45128441-I, 45128841-I, 45128163-I Preliminary Data Sheet E0233N10 /WE 13.15 Random Row Write (Ping-Pong Banks) (1/2) (Burst Length = 8, /CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 ;; ;; ;; ;;; ;; ; ; ;; ; ;; ; ;; ;; ; ; ;; ; ; ;; ;; ; ; ;; ;; ; ; ;; ;; ; ; ;; ;; ; ; ;; ;; ; ; ;; ;; ; ; ;; ; ;; ;; ; ; ;; ; ;; ; ; ;; ;; ;; ; ; ;; ; ;; ;; ;; ; ; ; ;; ; ; ; ;; ;; ;; ; ; ;; ;; ;; ;; ; ; ; ; ; ;; ; ;; ; ;; ;; ; ; ;; ; ;; ; ;; ;; ; ; ; ;; ; ;; ; ;; ;; ; ; ; ;; ; ; ;; ;; ;; ; ; ; ;; ;; ; ; ;; ;; ; ; ; ;; ; ;; ;; ; ;; ; CLK CKE H /CS /RAS /CAS BA0 BA1 A10 RAa ADD RAa DQM DQ RDa CAa RAb RDa RAb CDa CAb L Hi-Z Activate Command for Bank A DAa1 DAa2 Write Command for Bank A DAa3 DAa4 DAa5 DAa6 DAa7 DAa8 Activate Command for Bank D DDa1 DDa2 DDa3 DDa4 Write Command for Bank D 59 Precharge Command for Bank A DDa5 DDa6 DDa7 DDa8 Activate Command for Bank A DAb1 DAb2 DAb3 Write Command for Bank A Precharge Command for Bank D µPD45128441-I, 45128841-I, 45128163-I Preliminary Data Sheet E0233N10 /WE 60 Random Row Write (Ping-Pong Banks) (2/2) (Burst Length = 8, /CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK ;;; ;;;;; ;;;;; ; ; ; ;; ;; ; ; ;; ; ; ;; ; ; ;; ;; ; ;; ; ;; ;; ;; ; ;; ; ; ; ; ; ; ; ; ;; ;; ;; ; ;; ; ; ;; ; ;; ;; ;; ; ; ; ;; ;; ; ; ; ; ;; ; ; ;; ;; ; ; ; ; ;; ;; ;; ; ; ; ;; ; ;; ;; ; ;; ; ;; ;; ;; ; ;; ; ; ; ; ; ; ; ;; ;; ;; ; ;; ; ; ;; ; ;; ;; ; ;; ; ; ;; ;; ; ;; ; ; ;; ; ;; ; ; ; ;; ; ;; ;; ; ;; ; ; ;; ;; ; ; ;; ; ;; ; ; ;; ;; ; ; ; ;; ; ; ;; ; ;; ;; ; ;; CKE H /CS /RAS /CAS BA0 BA1 A10 RAa ADD RAa DQM DQ RAb RDa RDa CAa CDa RAb CAb L Hi-Z Activate Command for Bank A DAa1 DAa2 Write Command for Bank A DAa3 DAa4 DAa5 DAa6 DAa7 DAa8 Activate Command for Bank D DDa1 DDa2 DDa3 DDa4 DDa5 DDa6 DDa7 DDa8 DAb1 Write Command for Bank D Precharge Command for Bank A Activate Command for Bank A Write Command for Bank A DAb2 Precharge Command for Bank D µPD45128441-I, 45128841-I, 45128163-I Preliminary Data Sheet E0233N10 /WE 13.16 Read and Write (1/2) (Burst Length = 4, /CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H ;;;;;; ;; ;; ; ; ; ;; ; ;; ; ; ; ;; ; ;; ; ; ; ;; ; ;; ; ; ; ;; ; ;; ; ; ; ;; ; ;; ; ; ; ;; ; ; ;; ; ; ;;;;;;;;;; ;;; ;; ; ; ;; ; ; ;; ; ; ;; ; ; ;; ; ; ;; ; ; ;; ; ; ;; ; ; ;; ; ; ;; ; ; ;; ; ; ; ;; ; ;; ; ; ; ;; ; ;; ; ; ; ;; ; /CS /RAS /CAS BA0 BA1 A10 RAa ADD RAa CAa CAb CAc Write Latency = 0 DQM L Word Masking DQ Hi-Z Activate Command for Bank A QAa1 Read Command for Bank A QAa2 QAa3 QAa4 DAb1 DAb2 DAb4 Write Command for Bank A 61 Hi-Z at the end of wrap function QAc1 QAc2 QAc4 Read Command for Bank A 0-Clock Latency 2-Clock Latency µPD45128441-I, 45128841-I, 45128163-I Preliminary Data Sheet E0233N10 /WE 62 Read and Write (2/2) (Burst Length = 4, /CAS Latency = 3) T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 ;;;;;;; ;; ;; ; ; ; ;; ; ;;;; ; ; ; ;; ; ;; ; ; ; ;; ; ;;;; ; ; ; ;; ; ;; ; ; ; ;; ; ;;;; ; ; ; ;; ; ; ; ; ; ;; ; ;;;; ; ;; ; ;;; ; ; ;; ; ; ; ;; ; ;;;; ; ; ; ;; ; ;; ; ; ; ;; ; ;;;; ; ; ; ;; ; ;; ; ;; ; ; ; ;;;; ; ; ; ;; ; ; ; ;; ; ;; ; ;;;; ; ; ;; ; ; T0 CLK CKE H /CS /RAS /CAS BA0 BA1 A10 RAa ADD RAa CAb CAa CAc Write Latency = 0 DQM L Word Masking DQ Hi-Z Activate Command for Bank A QAa1 Read Command for Bank A QAa2 QAa3 QAa4 DAb1 DAb2 DAb4 Write Command for Bank A Hi-Z at the end of wrap function QAc1 QAc2 Read Command for Bank A 0-Clock Latency 2-Clock Latency µPD45128441-I, 45128841-I, 45128163-I Preliminary Data Sheet E0233N10 /WE 13.17 Interleaved Column Read Cycle (1/2) (Burst Length = 4, /CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H /CS ;; ; ;;; ;; ; ;; ; ;; ;; ; ; ; ; ; ;; ; ;; ;; ; ;; ; ; ;; ;; ; ;; ; ; ;; ;; ; ; ;; ; ;; ;; ; ; ;; ;; ; ; ;; ; ;; ;; ;; ; ; ; ; ; ; ; ;; ;; ;; ; ;; ; ;; ; ;; ; ; ;; ; ;; ;; ; ; ; ; ;; ;; ;; ; ; ; ; ; ;; ; ;; ;; ; ; ;; ; ; ;; ;; ;; ; ; ;; ;; ; ; ;; ; ;; ;; ; ;; ; ; ;; ;; ; /RAS /CAS BA0 BA1 A10 RAa ADD RAa DQM RDa CAa RDa CDa CDb CDc CAb CDd L Hi-Z Aa1 DQ Activate Command for Bank A Read Command for Bank A 63 Activate Command for bank D Aa2 Aa3 Read Command for Bank D Aa4 Da1 Read Command for Bank D Da2 Db1 Read Command for Bank D Db2 Dc1 Read Command for Bank A Dc2 Ab1 Ab2 Read Command for Bank D Precharge Command for Bank A Dd1 Dd2 Dd3 Precharge Command for Bank D Dd4 µPD45128441-I, 45128841-I, 45128163-I Preliminary Data Sheet E0233N10 /WE 64 Interleaved Column Read Cycle (2/2) (Burst Length = 4, /CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 ;; ;;; ;; ; ;; ;; ;; ; ; ;; ;; ; ; ;; ;; ; ; ;; ;; ; ; ; ;; ; ;; ; ; ;; ;; ; ; ;; ;; ; ; ;; ;; ; ; ;; ;; ;; ;; ; ; ; ; ; ;; ; ; ; ;; ;; ;; ; ; ;; ; ;; ; ; ;; ;; ; ; ;; ;; ; ;; ;; ; ; ; ; ;; ;; ; ;; ; ;; ; ; ; ;; ;; ;; ; ;; ; ; ; ;; ;; ;; ; ;; ; ; ; ;; ;; ; ; ; ;; ;; ; ; ;; ;; ; ; ;; ;; ; ; ;; ;; ; ; ;; ; ; ;; ; ;; ;; ; ;; ; ; ;; ; ;; ;; ; ;; CLK CKE H /CS /RAS /CAS BA0 BA1 A10 RAa ADD RAa DQM DQ RDa CAa RDa CDa CDb CAb CDc L Hi-Z Activate Command for Bank A Aa1 Read Command for Bank A Activate Command for Bank D Aa2 Read Command for Bank D Aa3 Aa4 Read Command for Bank D Da1 Da2 Read Command for Bank D Db1 Db2 Dc1 Dc2 Ab1 Ab2 Read Command for Bank A Precharge Command for Bank D Precharge Command for Bank A Ab3 Ab4 µPD45128441-I, 45128841-I, 45128163-I Preliminary Data Sheet E0233N10 /WE 13.18 Interleaved Column Write Cycle (1/2) (Burst Length = 4, /CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 ;;;;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;;; ;;;;;;;;;;;; ; ; ; ; ;;;;;;; ; ; ; ;;;; ;;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;;;;; CLK CKE H /CS /RAS /CAS BA0 BA1 A10 RAa ADD RAa DQM RBa RBa CAa CBa CBb CBc CAb CBd L Hi-Z DQ Activate Command for Bank A Aa1 Write Command for Bank A Aa2 Aa3 Activate Command for Bank B Aa4 Ba1 Write Command for Bank B Ba2 Bb1 Write Command for Bank B Bb2 Bc1 Write Command for Bank B Bc2 Ab1 Write Command for Bank A Ab2 Bd1 Write Command for Bank B Bd2 Bd3 Bd4 Precharge Command for Bank A 65 Precharge Command for Bank B µPD45128441-I, 45128841-I, 45128163-I Preliminary Data Sheet E0233N10 /WE 66 Interleaved Column Write Cycle (2/2) (Burst Length = 4, /CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 ;;;;;;;;;;; ;; ; ; ; ;; ;;;;; ;; ;;; ; ; ; ;; ; ;; ; ; ; ; ; ;;;; ;; ; ; ; ; ; ;; ; ; ;; ;;; ;; ; ; ;;;; ;; ; ; ;; ; ; ;; ; ;; ; ; ;;;;; ;; ;; ; ;; ; ; ; ;; ; ;; ; ; ;;;;; ;; ; ;; ; ;; ; ; ;; ; ;; ; ; ;;;;; ;; ;; ; ;; ; ;; ; ;; ;; ; ;; ; ;;;;; ;; ;; ; ;; ; ;; ;;;; ;;;;;;; ;; ; ;; CLK CKE H /CS /RAS /CAS ;; BA0 BA1 A10 RAa ADD RAa DQM DQ RBa CAa RBa Aa1 Aa2 CBa CBb CAb CBc CBd L Hi-Z Activate Command for Bank A Write Command for Bank A Activate Command for Bank B Aa3 Aa4 Ba1 Write Command for Bank B Ba2 Bb1 Write Command for Bank B Bb2 Bc1 Write Command for Bank B Bc2 Ab1 Write Command for Bank A Ab2 Bd1 Bd2 Bd3 Bd4 Write Command for Bank B Precharge Command for Bank A Precharge Command for Bank B µPD45128441-I, 45128841-I, 45128163-I Preliminary Data Sheet E0233N10 /WE 13.19 Auto Precharge after Read Burst (1/2) (Burst Length = 4, /CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 ;;; ;;;;; ; ;;; ; ; ;; ;; ; ;; ;;; ; ;; ;; ; ;;;; ;; ; ;; ; ;; ; ;; ;; ; ;; ;;; ; ;;;; ;; ; ;; ;; ; ; ; ;; ;;; ;; ; ;; ; ; ;;;; ;; ; ; ; ;; ;; ; ;; ;;; ;; ; ;; ; ; ;;;; ;; ; ; ;; ;; ; ;; ;;; ; ;; ;; ; ;;;; ;; ; ; ;; ;; ; ; ;; ;;; ; ;; ;; ; ; ;;;; ;; ; ;; ; ;; ; ; ; ;; ;;; ; ;; ;; ; ; ;;;; ;; ; ; ;; ;; ; ; ;; ;;;; ;;; ;; ; ;; ; ;; CLK CKE H /CS /RAS /CAS BA0 BA1 A10 RAa ADD RAa DQM DQ RDa CAa RDa RDb CDa CAb RDb RAc CDb RAc CAc L Hi-Z Activate Command for Bank A Read Command for Bank A Activate Command for Bank D Read with Auto Precharge Command for Bank D 67 Read with Auto Precharge Command for Bank A Auto Precharge Start for Bank D Activate Command for Bank D Activate Command Read with Read with for Bank A Auto Precharge Auto Precharge Command Command for Bank A for Bank D Auto Precharge Auto Precharge Start for Bank A Start for Bank D µPD45128441-I, 45128841-I, 45128163-I Preliminary Data Sheet E0233N10 /WE 68 Auto Precharge after Read Burst (2/2) (Burst Length = 4, /CAS Latency = 3) T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 ;;;;;;; ;; ; ; ; ; ; ; ; ;;;; ; ;; ; ; ; ; ; ; ; ;;;; ; ; ; ;; ; ; ; ; ; ;;;; ; ;; ; ; ; ; ; ; ; ;;;; ; ;; ; ; ; ; ; ; ; ;;;; ; ;; ; ; ; ; ; ; ; ;;;; ; ;; ; ; ; ; ; ; ; ;;;; ; ;; ; ; ; ; ;;;; ; ; ; ; T0 CLK CKE H /CS /RAS /CAS BA0 BA1 A10 RAa ADD RAa DQM DQ RDa CAa RDa RDb CDa CAb RDb CDb L Hi-Z Activate Command for Bank A Activate Command for Bank D Read Command for Bank A Read with Auto Precharge Command for Bank D Read with Auto Precharge Command for Bank A Auto Precharge Start for Bank D Activate Command for Bank D Read with Auto Precharge Command for Bank D Auto Precharge Start for Bank A µPD45128441-I, 45128841-I, 45128163-I Preliminary Data Sheet E0233N10 /WE 13.20 Auto Precharge after Write Burst (1/2) (Burst Length = 4, /CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 ;;;; ;;;; ; ;;; ; ;; ; ;; ; ;; ;;; ;; ; ;; ; ;;;; ;; ; ;; ; ;; ; ;; ;; ;; ;;; ; ; ;;;; ;; ; ;; ; ;; ; ; ;; ;;; ;; ; ;; ; ; ;;;; ;; ; ; ;; ; ;; ; ;; ;;; ;; ; ;; ; ; ;;;; ;; ; ;; ; ;; ; ;; ;;; ;; ; ;; ; ;;;; ;; ; ;; ; ;; ; ; ;; ;;; ;; ; ;; ; ; ;;;; ;; ; ;; ; ;; ; ; ; ;; ;;; ;; ; ;; ;;;; ; ; ;; ; ;; ; ;; ; ; ;; ;;;; ;;; ;; ; ;; ; ; ;; CLK CKE H /CS /RAS /CAS BA0 BA1 A10 RAa ADD RAa DQM DQ RDa CAa RDa RDb CDa CAb RDb RAc CDb RAc CAc L Hi-Z Activate Command for Bank A Activate Command for Bank D Write Command for Bank A Activate Command for Bank D Write with Auto Precharge Command for Bank D Write with Auto Precharge Command for Bank A Activate Command for Bank A 69 Write with Write with Auto Precharge Auto Precharge Command Command for Bank D for Bank A Auto Precharge Auto Precharge Auto Precharge Start for Bank D Start for Bank A Start for Bank D µPD45128441-I, 45128841-I, 45128163-I Preliminary Data Sheet E0233N10 /WE 70 Auto Precharge after Write Burst (2/2) (Burst Length = 4, /CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK ;;;; ;;; ;;; ; ;; ; ;; ; ;; ;; ;;; ; ;;;; ; ; ;; ; ;; ; ;;; ;; ; ;; ; ;;;; ; ; ; ;; ; ;; ; ;;; ;; ; ;; ;;;; ; ; ; ; ; ;; ;; ;;; ;; ; ;; ;;;; ; ; ;; ; ;; ; ;;; ;; ; ;; ;;;; ; ; ;; ; ;; ; ;;; ;; ; ;; ;;;; ; ; ;; ; ;; ; ;;; ;; ; ;; ;;;; ; ; ;; ; ;; ; ;;;; ;;; ;; ; ;; ; CKE H /CS /RAS /CAS BA0 BA1 A10 RAa ADD RAa DQM DQ RDa CAa RDa RDb CDa CAb RDb CDb L Hi-Z Activate Command for Bank A Activate Command for Bank D Write Command for Bank A Write with Auto Precharge Command for Bank D Write with Auto Precharge Command for Bank A Auto Precharge Start for Bank D Activate Command for bank D Auto Precharge Start for Bank A Write with Auto Precharge Command for Bank D µPD45128441-I, 45128841-I, 45128163-I Preliminary Data Sheet E0233N10 /WE 13.21 Full Page Read Cycle (1/2) (/CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 Tn Tn + 1 Tn + 2 Tn + 3 Tn + 4 Tn + 5 Tn + 6 Tn + 7 Tn + 8 Tn + 9 Tn + 10 Tn + 11 Tn + 12 Tn + 13 ;;;;;; ;;;;;;;;;;;; ; ; ; ; ; ;;;;;;; ; ; ;;;;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;;;;; CLK H CKE /CS /RAS /CAS BA0 BA1 A10 RAa ADD RAa DQM DQ RDa CAa RDb RDa CDa RDb L Hi-Z Activate Command for Bank A Aa Read Command for Bank A Activate Command for Bank D Aa+1 Aa+2 Aa-2 Aa-1 Aa Read Command for Bank D Aa+1 Da Da+1 Da+2 Da+3 Da+4 Burst Stop Command Da+5 Da+6 Precharge Command for Bank D Activate Command for Bank D 71 µPD45128441-I, 45128841-I, 45128163-I Preliminary Data Sheet E0233N10 /WE 72 Full Page Read Cycle (2/2) (/CAS latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 Tn Tn + 1 Tn + 2 Tn + 3 Tn + 4 Tn + 5 Tn + 6 Tn + 7 Tn + 8 Tn + 9 Tn + 10 Tn + 11 Tn + 12 CLK ;;;;; ;;;;;;;;;; ;;;;;;;;; ;;;;;;;;;; ;;;;;;;;;; ;;;;;;;;;; ;;;;;;;; ;;;; ;;;;;;;;;; ;;;;;;;;;; CKE H /CS /RAS /CAS BA0 BA1 A10 RAa ADD RAa DQM DQ RDa CAa RDb RDa CDa RDb L Hi-Z Activate Command for Bank A Aa Read Command for Bank A Activate Command for Bank D Aa+1 Aa-3 Aa-2 Aa-1 Read Command for Bank D Aa Aa+1 Da Da+1 Da+2 Da+3 Burst Stop Command Da+4 Da+5 Precharge Command for Bank D Activate Command for Bank D µPD45128441-I, 45128841-I, 45128163-I Preliminary Data Sheet E0233N10 /WE 13.22 Full Page Write Cycle (1/2) (/CAS latency = 2) T0 T1 T2 T3 T4 T5 Tn Tn + 1 Tn + 2 Tn + 3 Tn + 4 Tn + 5 Tn + 6 Tn + 7 Tn + 8 Tn + 9 Tn + 10 Tn + 11 Tn + 12 Tn + 13 Tn + 14 Tn + 15 ;; ; ;;;;;;; ;; ;; ; ;; ; ;; ; ;; ; ;; ;; ; ;;;;; ;; ; ;; ; ;; ;;;;;; ;;; ;; ;;;; ; ;; ; ; ;; ;; ; ;; ;;; ; ;; ;; ;;;; ; ;; ; ; ;; ;; ; ;; ;;; ; ;; ;; ;;;; ; ;; ;; ; ;; ; ;; ; ;; ;; ; ;; ;;;;; ; ;; ;; ; ;; ; ;; ; ; ;; ;; ; ;; ; ;;;;; ; ;; ;; ; ;; ; ; ;; ;;;;;;; ;; ; ;;;; ; ;; ; ; ;; ; ;; ; ;; ;;;; ;;; ;; ; ;; ; ;; CLK CKE H /CS /RAS /CAS BA0 BA1 A10 RAa ADD RAa DQM DQ RDa CAa RDb RDa CDa RDb L Hi-Z Activate Command for Bank A Aa Write Command for Bank A Aa+1 Aa+2 Activate Command for Bank D Aa-2 Aa-1 Aa Aa+1 Da Da+1 Da+2 Da+3 Da+4 Da+5 Precharge Command for Bank D Write Command for Bank D Burst Stop Command 73 Activate Command for Bank D µPD45128441-I, 45128841-I, 45128163-I Preliminary Data Sheet E0233N10 /WE 74 Full Page Write Cycle (2/2) (/CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 Tn Tn + 1 Tn + 2 Tn + 3 Tn + 4 Tn + 5 Tn + 6 Tn + 7 Tn + 8 Tn + 9 Tn + 10 Tn + 11 Tn + 12 Tn + 13 CLK ;;;;; ;;;;;;;;;; ;;;;;;;;;; ;;;;;;;;;; ;;;;;;;;;; ;;;;;;;;;; ;;;;;;;;;; ;;;;;;;;;; ;;;;;;;;;; CKE H /CS /RAS /CAS BA0 BA1 A10 RAa ADD RAa DQM DQ RDa CAa RDb RDa CDa RDb L Hi-Z Activate Command for Bank A Aa Aa+1 Write Command for Bank A Aa+2 Activate Command for Bank D Aa+3 Aa-1 Aa Aa+1 Da Da+1 Da+2 Da+3 Da+4 Da+5 Write Command for Bank D Precharge Command for Bank D Burst Stop Command Burst is not completed in the Full Page Mode Activate Command for Bank D µPD45128441-I, 45128841-I, 45128163-I Preliminary Data Sheet E0233N10 /WE 13.23 Byte Write Operation (Burst Length = 4, /CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE ; ;;; ;;; ; ;;; ;;;;;; ;;;; ; ;;; ;;;;;; ;;;; ;;;;;; ; ; ;;;;;; ; ; ; ;;;;;; ;;;; ; ;;; ;;;;;; ;;;; ;;;;;; ;;;; ; ; ;;;;;; ;;; ;;; ; /CS /RAS /CAS BA0 BA1 A10 ADD LDQM UDQM DQ (lower) DQ (upper) 75 Activate Command for Bank D Read Command for Bank D Upper Byte not Read Lower Byte Upper Byte Lower Byte not Write not Write not Write µPD45128441-I, 45128841-I, 45128163-I Preliminary Data Sheet E0233N10 /WE 76 Byte Write Operation (Burst Length = 4, /CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE ;;; ;;; ; ; ;;;;;; ;;;; ;;; ; ;;;;;; ;;; ; ;;;;;; ;;;; ;;;;;; ; ; ; ;;;;;; ;;; ;;; ; ; ;;;;;; ;;;; ; ;;;;;; ;;; ; ; ;;;;;; ;;;; ;;; /CS /RAS /CAS BA0 BA1 A10 ADD LDQM UDQM DQ (lower) DQ (upper) Activate Command for Bank D Read Command for Bank D Upper Byte not Read Lower Byte not Read Lower Byte not Write Upper Byte not Write Lower Byte not Write Read Command for Bank D Lower Byte not Read Lower Byte not Read µPD45128441-I, 45128841-I, 45128163-I Preliminary Data Sheet E0233N10 /WE 13.24 Burst Read and Single Write (Option) (Burst Length = 4, /CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H ;;;;; ;;;;;;;;;; ;;;;;;;;;; ;;;;;;;;;; ;;;;;;;;;; ;;;;;;;;;; ;;;;;;;;;; ;;;;;;;;;; ;;;;;;;;;; /CS /RAS /CAS BA0 BA1 A10 ADD DQM DQ Hi-Z Activate Command for Bank D Qa1 Read Command for Bank D Qa2 Qa3 Qa4 D1 Single Write Command for Bank D Qb1 Single Write Command for Bank D Read Command for Bank D Qb2 Qb4 D2 Single Write Command for Bank D 77 µPD45128441-I, 45128841-I, 45128163-I Preliminary Data Sheet E0233N10 /WE 78 Burst Read and Single Write (Option) (Burst Length = 4, /CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H ;;;;; ;;;;;;;;;; ;;;;;;;;;; ;;;;;;;;;; ;;;;;;;;;; ;;;;;;;;;; ;;;;;;;;;; ;;;;;;;;;; ;;;;;;;;;; /CS /RAS /CAS BA0 BA1 A10 ADD DQM DQ Hi-Z Activate Command for Bank D Qa1 Read Command for Bank D Qa2 Qa3 Qa4 D1 Single Write Command for Bank D Qb1 Single Write Command for Bank D Read Command for Bank D Qb2 Qb4 µPD45128441-I, 45128841-I, 45128163-I Preliminary Data Sheet E0233N10 /WE 13.25 Full Page Random Column Read (Burst Length = Full Page, /CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK ;;;;;;;;;; ;;;;;;;;;; ;;;;;;;;;; ;;;;;;;;;; ;;;;;;;;;; ;;;;;;;;;; ;;;;;;; ;;;;;;;;;; ;;;;;;;;;; CKE H /CS /RAS /CAS BA0 BA1 A10 RAa RDa ADD RAa RDa DQM DQ CAa CDa CAb CDb CAc QAa1 QDa1 QAb1 QAb2 QDb1 QDb2 CDc L Hi-Z Activate Command for Bank A Activate Command for Bank D Read Command for Bank A Read Command for Bank A 79 Read Command for Bank D Read Command for Bank D Read Command for Bank A QAc1 QAc2 Read Command for Bank D QAc3 QDc1 QDc2 QDc3 Precharge Command for Bank D (PRE Termination of Burst) µPD45128441-I, 45128841-I, 45128163-I Preliminary Data Sheet E0233N10 /WE 80 Full Page Random Column Read (Burst Length = Full Page, /CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK ;;;;;;;;;; ;;;;;;;;;; ;;;;;;;;;; ;;;;;;;;;; ;;;;;;;;;; ;;;;;;;;;; ;;;;;;; ;;;;;;;;;; ;;;;;;;;;; CKE H /CS /RAS /CAS BA0 BA1 A10 RAa RDa ADD RAa RDa DQM DQ CAa CDa CAb CDb CDc CAc L Hi-Z Activate Command for Bank A QAa1 QDa1 Activate Command for Bank D Read Command for Bank A Read Command for Bank A Read Command for Bank D Read Command for Bank D QAb1 QAb2 Read Command for Bank A QDb1 QDb2 QAc1 Read Command for Bank D QAc2 QAc3 QDc1 QDc2 QDc3 Precharge Command for Bank D (PRE Termination of Burst) Hi-Z µPD45128441-I, 45128841-I, 45128163-I Preliminary Data Sheet E0233N10 /WE 13.26 Full Page Random Column Write (Burst Length = Full Page, /CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 ;;;;;; ;;;;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;; ;;;;;;;; ;;;;;;;;;;;; CLK CKE H /CS /RAS /CAS BA0 BA1 A10 RAa RDa ADD RAa RDa DQM DQ CAa CDa CAb CDb CAc DDb1 DDb2 DAc1 CDc L Hi-Z Activate Command for Bank A DAa1 DDa1 Activate Command for Bank D Write Command for Bank A DAb1 Write Command for Bank A 81 Write Command for Bank D DAb2 Write Command for Bank D Write Command for Bank A DAc2 DAc3 DDc1 Write Command for Bank D DDc2 DDc3 DDc4 Precharge Command for Bank D (PRE Termination of Burst) µPD45128441-I, 45128841-I, 45128163-I Preliminary Data Sheet E0233N10 /WE 82 Full Page Random Column Write (Burst Length = Full Page, /CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 ;;;;;; ;;;;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;; ;;;;;;;; ;;;;;;;;;;;; CLK CKE H /CS /RAS /CAS BA0 BA1 A10 RAa RDa ADD RAa RDa DQM DQ CAa CDa CAb CDb CAc DDb1 DDb2 DAc1 CDc L Hi-Z Activate Command for Bank A DAa1 DDa1 Activate Command for Bank D Write Command for Bank A DAb1 Write Command for Bank A Write Command for Bank D DAb2 Write Command for Bank D Write Command for Bank A DAc2 DAc3 DDc1 Write Command for Bank D DDc2 DDc3 DDc4 Precharge Command for Bank D (PRE Termination of Burst) µPD45128441-I, 45128841-I, 45128163-I Preliminary Data Sheet E0233N10 /WE 13.27 PRE (Precharge) Termination of Burst (1/2) (Burst Length = 8, /CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK ;;;;; ;;;;;;;;;; ;;;;;;; ;;;;;;;;;; ;;;;;;;;;; ;;;;;;;;;; ;;;;;;;;;; ;;;;;;;;;; ;;;;;;;;;; CKE H /CS /RAS /CAS BA0 BA1 A10 RAa ADD RAa DQM DQ RAb CAa RAb RAc CAb RAc Write Masking L Hi-Z DAa1 Activate Command for Bank A DAa2 DAa3 DAa4 DAa5 QAb1 QAb2 Write Command for Bank A QAb3 QAb4 QAb5 Activate Command for Bank A Read Command for Bank A PRE Termination of Burst tRCD Precharge Command for Bank A tDPL 83 tRAS Activate Command for Bank A tRP Hi-Z PRE Termination of Burst tRAS Precharge Command for Bank A µPD45128441-I, 45128841-I, 45128163-I Preliminary Data Sheet E0233N10 /WE 84 PRE (Precharge) Termination of Burst (2/2) (Burst Length = 8, /CAS Latency = 3) T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 ;;;; ;; ;;;;; ;; ; ; ; ;; ; ;; ; ;; ; ; ;;;; ; ;; ; ;; ;; ; ;; ; ; ;;;; ; ;; ; ;; ; ; ; ;; ;; ; ;; ; ; ;;;; ; ;; ;; ; ; ; ; ;; ;; ;; ; ; ; ;;;; ; ; ; ;; ; ;; ; ;; ; ;; ; ;; ; ;;;; ; ;; ; ;; ; ; ; ;; ;; ; ;; ; ; ;;;; ; ;; ; ;; ; ; ; ;; ; ;; ; ;; ; ;;;; ; ; ;; ; ;; ; ; ;; ; ; ;; ; ;; ;;;; ; ;; ; ;; ; ; T0 CLK CKE H /CS /RAS /CAS BA0 BA1 A10 RAa ADD RAa DQM RAb CAa RAb RAc CAb RAc Write Masking L Hi-Z DAa1 DQ DAa2 DAa3 DAa4 Hi-Z DAa5 Write Command for Bank A Activate Command for Bank A PRE Termination of Burst tRCD QAb3 QAb4 Read Command for Bank A Precharge Command for Bank A tDPL tRAS QAb1 QAb2 Activate Command for Bank A tRP PRE Termination of Burst tRAS Activate Command for Bank A Precharge Command for Bank A µPD45128441-I, 45128841-I, 45128163-I Preliminary Data Sheet E0233N10 /WE µPD45128441-I, 45128841-I, 45128163-I 14. Package Drawing 54-PIN PLASTIC TSOP (II) (10.16 mm (400)) 54 28 detail of lead end F P E 1 27 A H I G J S L N C D M S B K M NOTES 1. Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. 2. Dimension "A" does not include mold fiash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm per side. ITEM A MILLIMETERS 22.22±0.05 B 0.91 MAX. C 0.80 (T.P.) D 0.32+0.08 −0.07 E 0.10±0.05 F 1.1±0.1 G 1.00 H 11.76±0.20 I 10.16±0.10 J 0.80±0.20 K 0.145+0.025 −0.015 L 0.50±0.10 M 0.13 N 0.10 P 3°+7° −3° S54G5-80-9JF-2 Preliminary Data Sheet E0233N10 85 µPD45128441-I, 45128841-I, 45128163-I 15. Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the µPD45128xxx. Type of Surface Mount Device µPD45128xxxG5 : 54-pin Plastic TSOP (II) (10.16mm (400)) 86 Preliminary Data Sheet E0233N10 µPD45128441-I, 45128841-I, 45128163-I 16. Revision History Version / Date 1.0 / Nov. 2001 Page Description This edition Previous edition Type of revision Preliminary Data Sheet E0233N10 Location 87 µPD45128441-I, 45128841-I, 45128163-I NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR MOS DEVICES Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function. CME0107 88 Preliminary Data Sheet E0233N10 µPD45128441-I, 45128841-I, 45128163-I The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. 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Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. M01E0107