VML VG3617161DT-8

VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Description
The VG3617161DT is CMOS Synchronous Dynamic RAM organized as 524,288-word X 16-bit X 2-bank.
It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 3.3V
power supply. This SDRAM is delicately designed with performance concern for current high-speed application. Programmable CAS Latency and Burst Length make it possible to be used in widely various domains. It
is packaged by using JEDEC standard pinouts and standard plastic 50-pin TSOP II.
Features
• Single 3.3V +/- 0.3V power supply
• Clock Frequency: 180MHz, 166MHz, 143MHz, 125MHz, 100MHz
• Fully synchronous with all signals referenced to a positive clock edge
• Programmable CAS Iatency (2,3)
• Programmable burst length (1,2,4,8,& Full page)
• Programmable wrap sequence (Sequential/Interleave)
• Automatic precharge and controlled precharge
• Auto refresh and self refresh modes
• Dual internal banks controlled by A11(Bank select)
• Simultaneous and independent two bank operation
• I/O level : LVTTL interface
• Random column access in every cycle
• X16 organization
• Byte control by LDQM and UDQM
• 4096 refresh cycles/64ms
• Burst termination by burst stop and precharge command
Document:1G5-0160
Rev.1
Page 1
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Pin Configuration
50-Pin Plastic TSOP(II)(400 mil)
VDD
50
49
VSS
3
4
48
DQ14
VSSQ
47
VSSQ
DQ2
5
46
DQ13
DQ3
6
45
DQ12
VDDQ
7
44
VDDQ
DQ4
8
43
DQ11
42
DQ10
DQ1
DQ5
9
VSSQ
10
DQ6
11
DQ7
12
VDDQ
13
LDQM
14
VG3617161DT
1
2
DQ0
DQ15
41
VSSQ
40
DQ9
39
DQ8
38
VDDQ
37
NC
WE
15
36
UDQM
CAS
16
35
CLK
RAS
17
34
CKE
CS
18
33
NC
(BS)A11
19
32
A9
A10
20
31
A8
A0
21
30
A7
A1
22
29
A6
A2
23
28
A5
A3
24
27
A4
VDD
25
26
VSS
Pin Description
(VG3617161DT)
Pin Name
Function
Pin Name
A0-A11
Address inputs
- Row address
A0-A10
- Column address A0-A8
A11: Bank select
DQ0~DQ15
Data-in/data-out
CLK
Clock input
RAS
Row address strobe
CKE
Clock enable
CAS
Column address strobe
WE
Write enable
VDDQ
Supply voltage for DQ
VSS
Ground
VSSQ
Ground for DQ
VDD
Power
Document:1G5-0160
LDQM,
UDQM
Function
CS
Rev.1
Lower DQ mask enable and
Upper DQ mark enable
Chip select
Page 2
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Block Diagram
Clock
Generator
Address
Mode
Register
Row
Address
Buffer
&
Refresh
Counter
Bank B
Row Decoder
CLK
CKE
Bank A
WE
Document:1G5-0160
Data Control Circuit
Rev.1
Input & Output
Buffer
CAS
DQM
Column Decoder &
Latch Circuit
Column
Address
Buffer
&
Burst
Counter
Latch Circuit
RAS
Control Logic
CS
Command Decoder
Sense Amplifier
Page 3
DQ
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
VIN,VOUT
-1.0 to +4.6
V
Supply voltage relative to Vss
VDD,VDDQ
-1.0 to +4.6
V
IOUT
50
mA
PD
1.0
W
Operating temperature
TOPT
0 to + 70
¢
J
Storage temperature
TSTG
-55 to + 125
¢
J
Short circuit output current
Power dissipation
Recommended DC Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Note
Supply Voltage
VDD
3.0
3.3
3.6
V
Input High Voltage, all inputs
VIH
2.0
Ð
¡
VDD+0.3
V
1
Input Low Voltage, all inputs
VIL
-0.3
Ð
¡
0.8
V
2
Note 1.Overshoot limit : VIH(MAX.)=VDDQ+2.0V with a pulse width < 3ns
2.Undershoot limit : VIL=VSSQ-2.0V with a pulse < 3ns and -1.5V with a pulse < 5ns
Parameter
IIL
Description
( 0V ≤ V
IN
≤V
DD
Input Leakage Current
All other pins not under test = OV)
Min.
Max.
Unit
-5
5
µA
IOL
Output Leakage Current
Output disable, ( 0V ≤ V
)
≤V
OUT
DDQ
-5
5
µA
VOH
LVTTL Output ”H” Level Voltage
(lOUT = -2mA)
2.4
-
V
VOL
LVTTL Output ”L” Level Voltage
(lOUT = 2mA)
-
0.4
V
Document:1G5-0160
Rev.1
Page 4
Note
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Capacitance
(Ta=25°C,f=1MHZ)
Parameter
Symbol
Typ
Max
Unit
Input capacitance(CLK)
C11
2.5
4
pF
Input capacitance(all input pins except data
pins)
C12
2.5
5
pF
Data input/output capacitance
CI/O
4.0
6.5
pF
Recommended D.C. Operating Conditions (VDD = 3.3V
Description/test condition
± 0.3V, Ta = 0 ~ 70°C)
-5.5
-6
-7
-8
Unit
Symbol Min. Max. Min. Max. Min. Max. Min. Max.
Note
Operating Current
t
≥t
, Outputs Open
RC RC ( min )
Address changed once during tCK(min).
Burst Length = 1 (One Bank Active)
IDD1
190
185
165
145
3,4
Precharge Standby Current in non power-down mode
IDD2N
95
85
75
65
3
IDD2NS
45
40
35
30
tCK = tCK(min), CS ≥ VI H (min), CKE ≥ V I H (min)
Input signals are changed once during 30ns.
Precharge Standby Current in non power-down mode
tCK = ∞ , CKE ≥ V I H (min), CLK
≤ VIL (max)
mA
Input signals are stable
Precharge Standby Current in power-down mode
tCK = tCK(min), CKE ≤ V I L (max)
IDD2P
4
4
4
4
Precharge Standby Current in power-down mode
IDD2PS
3.5
3.5
3.5
3.5
Active Standby Current in non power down mode
CKE ≥ V I H (min), tCK = tCK(min)(Both Bank Actioe)
IDD3N
85
75
65
55
Active Standby Current in power-down
CKE ≤ V I L (max), tCK = tCK(min), CS ≥ VIH(min)(Both
Bank Active)
IDD3P
6
6
6
6
Operating Current (Page Burst, and All Bank activated)
tCCD = tCCD(min), Outputs Open, Multi-bank interleave,
gapless data
IDD4
195
185
175
165
4,5
Refresh Current
t RC ≥ t RC (min) (tREF = 64ms)
IDD5
185
175
165
155
3
Self Refresh Current
IDD6
4
4
4
4
tCK = ∞ , CKE ≤ V I L (max), CLK
CKE
≤ 0.2V
Document:1G5-0160
≤ VIL (max)
Rev.1
Page 5
3
3
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
A.C Characteristics:
Test Conditions: (Ta=0 to 70°C V DD=3.3V ± 0.3V ,VSS=0V)
symbol
A.C. Parameter
-5.5
Min.
-6
Max.
Min.
-7
Max.
Min.
-8
Max.
Min.
tCH
Clock high time
2
2
2.5
3
tCL
Clock low time
2
2
2.5
3
tT
Transition time (Rise and Fall)
0.5
tCK3
Clock cycle time
CL* = 3
5.5
6
7
8
CL* = 2
8
8.5
10
12
tCK2
10
0.5
10
0.5
10
0.5
tIS
Data/Address/Control Input setup time
2
2
2
2
tIH
Data/Address/Control Input hold time
1
1
1
1
tLZ
Data output low impedance
1
1
1
1
tHZ3
Data output high impedance CL* = 3
tHZ2
tAC3
tAC2
Access time from CLK
(positive edge)
Max.
unit
ns
10
4.5
5
5
7
CL* = 2
6
6.5
7
8
CL* = 3
5
5.5
6
7
CL* = 2
7
7
7
8
9
tOH
Data output hold time
2.2
2.5
2.5
2.5
tRCD
RAS to CAS delay
16.5
18
20
20
tRRD
Row activate to row activate delay
11
12
14
16
tCCD
CAS to CAS Delay time
1
1
1
1
CLK
tWR
Write recovery time
1tCK
+2ns
1tCK
1
1
CLK
+2 ns
tRAS
Row activate to precharge time
tRP
Precharge to refresh/row activate
command
tDAL3
33
100,000
100,000
40
100,000
48
100,000
20
Data-in to ACT (REF) Command (CL = 2clk+
3)
tRP
2clk+
tRP
2clk+
tRP
2clk+
tRP
tDAL2
Data-in to ACT (REF) Command (CL = 1clk+t
RP
2)
1clk+
tRP
1clk+
tRP
1clk+
tRP
tRC
Row cycle time
55
54
62
72
ns
tRSC
(Special) Mode Register Set Cycle time
2
2
2
2
CLK
tREF
Refresh time
tSRX
Minimum CKE ”High”for Self-Refresh
exit
1
1
1
1
CLK
tBDL
Last data in to burst STOP command
1
1
1
1
CLK
tPDE
Power Down Exit set-up time
5
5
5
6
ns
64
Rev.1
64
20
ns
ns
18
Document:1G5-0160
16.5
36
64
note
64
Page 6
ms
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Note:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
2. All voltages are referenced to VSS.
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK
and tRC. Input signals are changed one time during tCK. Assume that there are only one read/write cycle during tRC (min).
4. These parameters depend on the output loading. Specified values are obtained with the output open.
5. Assume minimum column address update cycle tCCD (min).
6. Power-up sequence is described in Note 10.
7. A.C. Test Conditions
Reference Level of Output Signals
1.4V / 1.4V
Output Load
Reference to the Under Output Load (B)
Input Signal Levels
3.0V / 0.0V
Transition Time (Rise and Fall) of Input Signals
1ns
Reference Level of Input Signals
1.4V
3.3V
1.4V
1.2K Ω
50Ω
Output
ZO=50Ω
Output
30pF
870Ω
LVTTL D.C. Test Load (A)
30pF
LVTTL A.C. Test Load (B)
8. Transition times are measured between V IH and VIL. Transition (rise and fall) of input signals are fixed slope (1 ns).
9. tHZ defines the time at which the outputs achieve the open circuit condition and are not reference levels.
10. Power up Sequence
Power up must be performed in the following sequence.
1) Power must be applied to VDD and VDDQ (simultaneously) when all input signals are held “NOP” state and
CKE = ”H”, DQM = ”H”. The CLK signals must be started at the same time.
2) After power-up, a pause of 200u secouds minimum is required. Then, it is recommended that DQM is held
“high” (V DD levels) to ensure DQ output to be in the high impedance.
3) Both banks must be precharged.
4) Mode Register Set command must be asserted to initialize the Mode register.
Document:1G5-0160
Rev.1
Page 7
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
5) A minimum of 8 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of the
device. Sequence of 4 and 5 may be changed.
Document:1G5-0160
Rev.1
Page 8
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Basic Features and Function description
1.Simplified State Diagram
Self
Refresh
LF
SE
Mode
Register
Set
try
en
LF
SE
MRS
it
ex
AUTO
Refresh
REF
IDLE
E
CK
ACT
CK
E
Power
Down
CKE
ROW
ACTIVE
Au Write
to p
red with
har
ge
CKE
AutoRead w
Prec ith
harg
e
m
ter
tio
ina
n)
Precharge
Read with
Auto Precharge
CKE
READ A
CKE
READ A
SUSPEND
arg
e
rge
ha
POWER
ON
READ
SUSPEND
)
ter
min
atio
n
rec
WRITE A
CKE
CKE
CKE
ith e
d w arg
Rea Prech
o
Aut
E(P
PR
CKE
READ
Write
Write with
Auto Precharge
WRITE A
SUSPEND
Read
WRITE
Read
PR
E(P
rec
h
CKE
PRE
WRITE
SUSPEND
ad
Re
Write
h
wit rge
ad cha
Re Pre
to
Au
W
rit
e
T
BS
BS
T
CKE
Active
Power
Down
Precharge
Automatic sequence
Manual input
Note: After the AUTO refresh operation, precharge operation is
performed automatically and enter the IDLE state
Document:1G5-0160
Rev.1
Page 9
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
2.Truth Table
2.1 Command Truth Table
FUNCTION
Symbol
Device deselect
No operation
Mode register set
Bank activate
Read
Read with auto precharge
Write
Write with auto precharge
Precharge select bank
Precharge all banks
Burst stop
DESL
NOP
MRS
ACT
READ
READA
WRIT
WRITA
PRE
PALL
BST
CKE
n-1
H
H
H
H
H
H
H
H
H
H
H
n
X
X
X
X
X
X
X
X
X
X
X
CS
RAS
CAS
WE
A11
A10
A9A0
H
L
L
L
L
L
L
L
L
L
L
X
H
L
L
H
H
H
H
L
L
H
X
H
L
H
L
L
L
L
H
H
H
X
H
L
H
H
H
L
L
L
L
L
X
X
L
V
V
V
V
V
V
X
X
X
X
X
V
L
H
L
H
L
H
X
X
X
V
V
V
V
V
V
X
X
X
2.2 DQM Truth Table
CKE
FUNCTION
Symbol
Data write/output enable
Data mask/output disable
Upper byte write enable/output enable
Lower byte write enable/output enable
Upper byte write inhibit/output disable
Lower byte inhibit/output disable
ENB
MASK
ENBU
ENBL
MASKU
MASKL
n-1
H
H
H
H
H
H
DQM
n-1
X
X
X
X
X
X
U
L
L
H
L
X
H
X
X
L
X
H
2.3 CKE Truth Table
Current State
Function
Activating
Any
Clock suspend
Idle
Idle
Self refresh
Clock suspend mode entry
Clock suspend
Clock suspend mode exit
CBR refresh command
Self refresh entry
Self refresh exit
Idle
Power down
Power down entry
Power down exit
Symbol
REF
SELF
CKE
n-1
n
H
L
L
L
L
H
H
H
H
L
L
H
L
H
H
L
L
H
CS
RAS
CAS
WE
Address
X
X
X
L
L
L
H
X
X
X
X
X
L
L
H
X
X
X
X
X
X
L
L
H
X
X
X
X
X
X
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
H : High level, L : Low level
X : high or Low level(Don’t care), V : Valid Data input
Document:1G5-0160
Rev.1
Page 10
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
2.4 Operative Command Table
Current state
Idle
Row active
Read
Write
(1/3)
CS
RAS
CAS
WE
H
X
X
X
X
DESL
Nop or Power down
2
L
H
H
X
X
NOP or BST
Nop or Power down
2
L
H
L
H
BA,CA,A10
READ/READA
ILLEGAL
3
L
H
L
L
BA,CA,A10
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BR,RA
ACT
Row active
L
L
H
L
BA,A10
PRE/PALL
Nop
L
L
L
H
X
REF/SELF
Refresh or Self refresh
L
L
L
L
Op-Code
MPS
Mode register access
H
X
X
X
X
DESL
Nop
L
H
H
X
X
NOP or BST
Nop
L
H
L
H
BA,CA,A10
READ/READA
Begin read:Determine AP
5
L
H
L
L
BA,CA,A10
WRIT/WRITA
Begin write:Determine AP
5
L
L
H
H
BA,RA
ACT
ILLEGAL
3
L
L
H
L
BA,A10
PRE/PALL
Precharge
6
L
L
L
H
X
REF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
ILLEGAL
H
X
X
X
X
DESL
Continue burst to end → Row active
L
H
H
H
X
NOP
Continue burst to end → Row active
L
H
H
L
X
BST
Burst stop → Row active
L
H
L
H
BA,CA,A10
READ/READA
Term burst, new read:Determine AP
7
L
H
L
L
BA,CA,A10
WRIT/WRITA
Term burst, start write:Determine AP
7,8
L
L
H
H
BA,RA
ACT
ILLEGAL
L
L
H
L
BA,A10
PRE/PALL
Term burst,precharging
L
L
L
H
X
REF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
ILLEGAL
H
X
X
X
X
DESL
Continue burst to end → write recovering
L
H
H
H
X
NOP
Continue burst to end → Write recovering
L
H
H
L
X
BST
Burst stop → Row active
L
H
L
H
BA,CA,A10
READ/READA
Term burst, start read: determine AP
7,8
L
H
L
L
BA,CA,A10
WRIT/WRITA
Term burst, new write:Determine AP
7
L
L
H
H
BA,RA
ACT
ILLEGAL
3
L
L
H
L
BA,A10
PRE/PALL
Term burst precharging
9
L
L
L
H
X
REF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
ILLEGAL
Document:1G5-0160
Address
Command
Rev.1
Action
Notes
4
3
Page 11
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
(2/3)
Current state
CS
RAS
CA
WE
H
X
X
L
H
L
Read with auto
precharge
Write with auto
precharge
Precharging
Row activating
Document:1G5-0160
Address
Command
Action
Notes
X
X
DESL
Continue burst to end → Prech arg ing
H
H
X
NOP
Continue burst to end → Prech arg ing
H
H
L
X
BST
ILLEGAL
L
H
L
H
BA,CA,A10
READ/READA
ILLEGAL
L
H
L
L
BA,CA,A10
WRIT/WRITA
ILLEGAL
L
L
H
H
BA,RA
ACT
ILLEGAL
3
L
L
H
L
BA,A10
PRE/PALL
ILLEGAL
3
L
L
L
H
X
PEF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
ILLEGAL
H
X
X
X
X
DESL
Continue burst to end → Write
recovering with auto precharge
L
H
H
H
X
NOP
Continue burst to end → Write
recovering with auto precharge
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BA,CA,A10
READ/READA
ILLEGAL
L
H
L
L
BA,CA,A10
WRIT/WRITA
ILLEGAL
L
L
H
H
BA,RA
ACT
ILLEGAL
3
L
L
H
L
BA,A10
PRE/PALL
ILLEGAL
3
L
L
L
H
X
REF/SELF
ILLEGAL
L
L
L
L
Op-code
MRS
ILLEGAL
H
X
X
X
X
DESL
Nop → Enter idle after tRP
L
H
H
H
X
NOP
Nop → Enter idle after tRP
L
H
H
L
X
BST
Nop → Enter idle after tRP
L
H
L
H
BA,CA,A10
READ/READA
ILLEGAL
3
L
H
L
L
BA,CA,A10
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BA,RA
ACT
ILLEGAL
3
L
L
H
L
BA,A10
PRE/PALL
Nop → Enter idle after tRP
L
L
L
H
X
REF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
ILLEGAL
H
X
X
X
X
DESL
Nop → Enter row active after tRCD
L
H
H
H
X
NOP
Nop → Enter row active after tRCD
L
H
H
L
X
BST
Nop → Enter row active after tRCD
L
H
L
H
BA,CA,A10
READ/READA
ILLEGAL
3
L
H
L
L
BA,CA,A10
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BA,RA
ACT
ILLEGAL
3,10
L
L
H
L
BA,A10
PRE/PALL
ILLEGAL
3
L
L
L
H
X
REF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
ILLEGAL
Rev.1
Page 12
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
(3/3)
Current state
Write
recovering
Write
recovering
with auto
precharge
Refreshing
Mode register
accessing
CS
RAS
CA
WE
Address
Command
Action
H
X
X
L
H
L
Notes
X
X
DESL
Nop → Enter row active after tDPL
H
H
X
NOP
Nop → Enter row active after tDPL
H
H
L
X
BST
Nop → Enter row active after tDPL
L
H
L
H
BA,CA,A10
READ/READA
Start read, Determine AP
L
H
L
L
BA,CA,A10
WRIT/WRITA
New write, Determine AP
L
L
H
H
BA,RA
ACT
ILLEGAL
3
L
L
H
L
BA,A10
PRE/PALL
ILLEGAL
3
L
L
L
H
X
PEF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
ILLEGAL
H
X
X
X
X
DESL
Nop → Enter precharge after tDPL
L
H
H
H
X
NOP
Nop → Enter precharge after tDPL
L
H
H
L
X
BST
Nop → Enter precharge after tDPL
L
H
L
H
BA,CA,A10
READ/READA
ILLEGAL
3,8
L
H
L
L
BA,CA,A10
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BA,RA
ACT
ILLEGAL
3
L
L
H
L
BA,A10
REF/PALL
ILLEGAL
3
L
L
L
H
X
REF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
ILLEGAL
H
X
X
X
X
DESL
Nop → Enter idle after tRC
L
H
H
X
X
NOP/BST
Nop → Enter idle after tRC
L
H
L
X
X
READ/WRIT
ILLEGAL
L
L
H
X
X
ACT/PRE/PALL
ILLEGAL
L
L
L
X
X
REF/SELF/MRS
ILLEGAL
H
X
X
X
X
DESL
Nop → Enter idle after 2 Clocks
L
H
H
H
X
NOP
Nop → Enter idle after 2 Clocks
L
H
H
L
X
BST
ILLEGAL
L
H
L
X
X
READ/WRITE
ILLEGAL
L
L
X
X
X
ACT/PRE/PALL/
REF/SELF/MRS
ILLEGAL
Note 1. All entries assume that CKE was active (High level)during the preceding clock cycle.
2. If both banks are idle, and CKE is inactive(Low level), the device will enter Power down mode.
All input buffers except CKE will be disabled.
3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA),
depending on the state of that bank.
4. If both banks are idle, and CKE is inactive(Low level), the device will enter Self refresh mode.
All input buffers except CKE will be disabled.
5. IIIegal if tRCD is not satisfied.
6. IIIegal if tRAS is not satisfied.
7. Must satisfy burst interrupt condition.
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9. Must mask preceding data if tDPL is not satisfied.
10. IIIegal if tRRD is not satisfied.
Document:1G5-0160
Rev.1
Page 13
8
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
2.5 Command Truth Table for CKE
CKE
n-1
RAS
n
CS
RAS
CAS
WE
Address
Self refresh
recovery
H
L
L
L
L
L
H
X
H
H
H
H
L
H
X
H
L
L
L
X
H
X
X
H
H
L
X
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
INVALID,CLK(n-1)would exit S.R.
S.R. Recovery
S.R. Recovery
ILLEGAL
ILLEGAL
Maintain S.R.
Idle after tRC
H
H
L
H
H
X
X
Idle after tRC
H
H
L
L
L
L
H
L
X
H
L
L
H
L
L
L
X
X
X
X
H
L
X
H
H
L
X
X
X
X
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Power down
(P.D.)
H
H
H
H
H
H
L
L
H
L
ILLEGAL
ILLEGAL
Begin clock suspend next cycle
Begin clock suspend next cycle
ILLEGAL
ILLEGAL
Exit clock suspend next cycle
Maintain clock suspend
INVALID, CLK(n-1) would exit P.D.
EXIT P · D · → Idle
L
H
L
H
X
H
X
X
X
X
X
X
X
H
H
L
H
X
X
H
H
L
L
H
X
H
H
H
H
L
L
L
L
L
L
H
L
H
L
H
X
X
X
H
L
L
H
X
X
H
L
L
L
H
X
H
H
L
L
L
L
L
L
L
L
H
L
X
OpCode
L
H
X
H
X
X
X
X
X
X
X
X
X
X
H
L
L
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Current state
Self refresh
(S.R.)
Both banks
idle
Any state
other than
listed above
X
X
OpCode
Action
Notes
Maintain power down mode
Refer to operations in Operative
Command Table
Refer to operations in Operative
Command Table
Refer to operation in Operative
Command Table
Refresh
Refer to operations in Operative
Command Table
Refer to operations in Operative
Command Table
Refer to operations in Operative
Command Table
Refer to operations in Operative
Command Table
Self refresh
Refer to operations in Operative
Command Table
Power down
Refer to operations in Operative
Command Table
Begin clock suspend next cycle
Exit clock suspend next cycle
Maintain clock suspend
Note 1. H : Hight level, L : low level, X : High or low level(Don't care).
2. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied
before any command other than EXIT.
3. Power down and Self refresh can be entered only from the both banks idle state.
4. Must be legal command as defined in Operative Command Table.
5 .IIIegal if tSRX is not satisfied.
Document:1G5-0160
Rev.1
Page 14
2
2
2
2
5
5
2
2
3
3
4
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
3.Initiallization
The synchronous DRAM is initialized in the power on sequence. Once power has been applied, a
100us minimum delay is needed in which stable power and input signals are maintained. During this delay,
CKE and DQM recommend to be held high.
After the 100us delay, both banks must be precharged using the precharge command. Once precharge
is completed and the minimum tRP is satisfied, the mode register can be programmed.
Minimum two CBR refresh commands must be performed before or after the mode register set command.
4.Programming the Mode Register
The mode register is programmed by the mode register set command using address bits A11 through
A0 as data inputs. The register retains data until it is reprogrammed or until the device loses power.
The mode register has four fields;
Options
CAS latency
Wrap type
Burst length
: A11 through A7
: A6 through A4
: A3
: A2 through A0
Following mode register programming, no command can be asserted befor at least two clock cycles
have elapsed.
CAS Latency
CAS latency is the most critical parameter to be set. It tells the device how many clocks must elapse
before the data will be available. The SDRAM is capable of reconfiguring its internal architecture based
on the value of CAS latency.
The value is determined by the frequency of the clock and the speed grade of the device. The value
can be programmed as 2 or 3.
Burst Length
Burst Length is the number of words that will be output or input in read or write cycle. After a read burst
is completed, the output bus will become high impedance.
The burst length is programmable as 1,2,4,8 or full page.
Wrap Type (Burst Sequence)
The wrap type specifies the order in which the burst data will be addressed. The order is programmable
as either “Sequential” or “Interleave”. The method chosen will depend on the type of CPU in the system.
Some microprocessor cache systems are optimized for sequential addressing and others for interleaved addressing. Both sequences support bursts of 1,2,4 and 8. Only the sequential burst. supports the
full-page length.
Document:1G5-0160
Rev.1
Page 15
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
5.Mode Register
11
0
10
0
9
0
8
0
7
1
6
11
x
10
x
9
1
8
0
7
0
6
11
x
10
x
9
0
8
0
7
0
6
5
4
3
2
1
0
Reserved Test Set
5
4
LTMODE
3
2
WT
1
BL
0
5
4
LTMODE
3
2
WT
1
BL
0
Burst Read and Single Write
X=Don’t care
Mode Register Set
Bits2-0
Burst length
000
WT=0
1
WT=1
1
001
2
2
010
4
4
011
8
8
100
R
R
101
R
R
110
R
R
111
Full page
R
0
Wrap type
1
Sequential
Interleave
Bits6-4
Latency
mode
000
CAS Iatency
R
001
R
010
2
011
3
100
R
101
R
110
R
111
R
Remark R:Reserved
Document:1G5-0160
Rev.1
Page 16
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
5.1 Burst Length and Sequence
(Burst of Two)
Starting Address
(column address A0, binary)
Sequential Addressing
Sequence (decimal)
Interleave Addressing
Sequence(decimal)
0
0,1
0,1
1
1,0
1,0
(Burst of Four)
Starting Address
(column address A1-A0, binary)
Sequential Addressing
Sequence (decimal)
Interleave Addressing
Sequence(decimal)
00
0,1,2,3
0,1,2,3
01
1,2,3,0
1,0,3,2
10
2,3,0,1
2,3,0,1
11
3,0,1,2
3,2,1,0
(Burst of Eight)
Starting Address
(column address A2-A0, binary)
Sequential Addressing
Sequence (decimal)
Interl
eave Addressing
Sequence(decimal)
000
0,1,2,3,4,5,6,7
0,1,2,3,4,5,6,7
001
1,2,3,4,5,6,7,0
1,0,3,2,5,4,7,6
010
2,3,4,5,6,7,0,1
2,3,0,1,6,7,4,5
011
3,4,5,6,7,0,1,2
3,2,1,0,7,6,5,4
100
4,5,6,7,0,1,2,3
4,5,6,7,0,1,2,3
101
5,6,7,0,1,2,3,4
5,4,7,6,1,0,3,2
110
6,7,0,1,2,3,4,5
6,7,4,5,2,3,0,1
111
7,0,1,2,3,4,5,6
7,6,5,4,3,2,1,0
Full page burst is an extension of the above tables of sequential addressing, with the length being 512/
256 words for 2Mx8/1Mx16 devices, respectively.
Document:1G5-0160
Rev.1
Page 17
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
6.Address Bits of Bank-Select and Precharge
Row A0 A1 A2 A3 A4 A5 A6
A7 A8 A9 A10 A11
(Activate command)
Row A0 A1 A2 A3 A4 A5 A6
0
Select Bank A ”Activate” command
1 Select Bank B ”Activate” command
A7 A8 A9 A10 A11
(Precharge)
A10 A11 Result
0
0
0
1
Precharge Bank B
1
x
Precharge All Banks
Precharge Bank A
x:Don’t care
Col. A0 A1 A2 A3 A4 A5 A6
0
Disables Auto-Precharge (End of Burst)
1
Enables Auto-Precharge (End of Burst)
A7 A8 A9 A10 A11
(CAS strobes)
0 Enable Read/Write commands for Bank A
1 Enable Read/Write commands for Bank B
Document:1G5-0160
Rev.1
Page 18
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
7.PRECHARGE
The PRECHARGE command can be asserted anytime after tRAS(min) is satisfied.
Soon after the PRECHARGE command is asserted, PRECHARGE operation is performed. The synchronous DRAM
enters the idle state after tRP(min) is satisfied. The parameter t RP is the time required to perform the PRECHARGE.
The earliest timing in a READ cycle that a PRECHARGE command can be asserted without losing any data in the
burst is as followed.
PRECHARGE
Burst lengh=4
T0
T1
T3
T2
T4
T6
T5
T7
CLK
Command
Read
PRE
CAS latency=2
DQ
Q0
Command
Q1
Q2
Hi-Z_
Q3
PRE
Read
CAS latency=3
Hi-Z
DQ
Q0
Q1
Q2
Q3
CAS latency= 2: One clock earlier than the last output data.
3: Two clocks earlier than the last output data.
(tRAS is satisfied)
In order to write all data to the memory cell correctly, the asynchronous parameter”t DPL” must be satisfied.
The tDPL(MIN.) specification defines the earliest time that a PRECHARGE command can be asserted after a WRITE
cycle. The minimum number of clocks are calculated by dividing tDPL(min.) by the clock cycle time.
In summary, the PRECHARGE command can be asserted relative to the reference clock of the last valid data.
In the following table, minus means clocks before the reference, plus means time after the reference.
CAS latency
READ
WRITE
2
-1
+tDPL(min.)
3
-2
+tDPL(min)
Document:1G5-0160
Rev.1
Page 19
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
8.AUTO PRECHARGE
During a READ or WRITE command cycle, A10 controls whether AUTO PRECHARGE is selected. If A10 is
high in the READ or WRITE command (READ with AUTO PRECHARGE command or WRITE with AUTO PRECHARGE command), AUTO PRECHARGE is selected and precharging begins automatically after the burst
access.
In the WRITE cycle, tDAL(min.) must be satisfied to assert the next active command to the bank being precharged.
When using AUTO PRECHARGE in the READ cycle, knowing when the PRECHARGE starts is important
because the tRAS must be satisfied. Once AUTO PRECHARGE has started, an active command to the bank can
be asserted after tRP(min.) has been satisfied.
The timing at which the AUTO PRECHARGE cycle begins depends both on the CAS Iatency programmed
into the mode register and on whether the cycle is READ or WRITE.
8.1 READ with AUTO PRECHARGE
During a READA cycle, the AUTO PRECHARGE begins one clock earlier(CAS Iatency of 2) or two
clocks earlier(CAS Iatency of 3) than the last data word output.
READ with AUTO PRECHARGE
Burst lengh=4
T0
T1
T3
T2
T4
T6
T5
T7
T8
CLK
Command
READA B
Auto precharge starts
CAS latency=2
DQ
QB0
QB1
QB2
Hi-Z
QB3
Auto precharge starts
Command
READA B
CAS latency=3
DQ
QB0
QB1
QB2
QB3
Hi-Z
Remark READA means READ with AUTO PRECHARGE
Document:1G5-0160
Rev.1
Page 20
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
8.2 WRITE with AUTO PRECHARGE
During a WRITA cycle, the AUTO PRECHARGE starts at tDPL(min.) after the last data word input to
the device
WRITE with AUTO PRECHRGE
Burst lengh=4
T0
T1
T3
T2
T4
T5
T6
T7
CLK
Command
WRITA B
AUTO PRECHARGE starts
tDPL
CAS latency=2
DB0
DQ
DB1
DB2
DB3
Hi-Z_
AUTO PRECHARGE starts
Command
WRITA B
tDPL
CAS latency=3
DB0
DQ
DB1
DB2
DB3
Hi-Z
Remark WRITA means WRITE with AUTO PRECHARGE
In summary, the auto precharge cycle begins relative to a reference clock that indicates the last data word is
valid.
In the table below, minus means clocks before the reference; plus means clocks after the reference.
CAS latency
READ
WRITE
2
-1
+tDPL(min.)
3
-2
+tDPL(min)
Document:1G5-0160
Rev.1
Page 21
T8
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
9.READ/WRITE Command Interval
9.1 READ to READ command interval
When a new READ command is asserted during a READ cycle, it will be effective after the CAS latency,
even if the previous READ operation has not completed. READ will be interrupted by another READ.
A READ command can be asserted in every clock without restriction.
READ to READ Command Interval
Burst lengh=4, CAS latency=2
T0
T1
T3
T2
T4
T6
T5
T7
T8
CLK
Read B
Read A
Command
DQ
QA0
QB0
QB1
QB2
Hi-Z_
QB3
1 cycle
9.2 WRITE to WRITE Command Interval
When a new WRITE command is asserted during a WRITE cycle, the previous burst will be terminated
and the new burst will begin with the new WRITE command. WRITE will be interrupted by another WRITE.
A WRITE command can be asserted in every clock without restriction.
WRITE to WRITE Command Interval
Burst lengh=4, CAS latency=2
T0
T1
T3
T2
T4
T5
T6
T7
CLK
Command
Write A
Write B
DQ
QA0
QB0
QB1
QB2
QB3
Hi-Z_
1 cycle
Document:1G5-0160
Rev.1
Page 22
T8
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
9.3 WRITE to READ Command Interval
The WRITE command to READ command interval is a minimum of 1 cycle. Only the WRITE data preceding the READ command will be written. The data bus must be in high-impedance at least one cycle prior
to the first DOUT.
WRITE to READ Command Interval
Burst lengh=4
T0
T1
T2
T3
T4
T6
T5
T8
T7
CLK
1 cycle
Command
WRITE A
Read B
CAS latency=2
Hi-Z
DA0
DQ
Command
Write A
QB0
QB1
QB2
QB3
QB1
QB2
Read B
CAS latency=3
DA0
DQ
Hi-Z
QB0
QB3
9.4 READ to WRITE Command Interval
During READ cycle, READ can be interrupted by WRITE. The data bus must be in high-impedance
using DQM before the WRITE command. DQM must be high at least 3 clocks prior to the WRITE command.
This restriction is necessary to avoid a data bus conflict.
Document:1G5-0160
Rev.1
Page 23
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
READ to WRITE Command Interval
T0
T1
T3
T2
T4
T6
T5
T7
CAS latency=2
T8
CLK
Read
Command
Write
DQM
DQ
Hi-Z
D0
D1
D2
D3
1 cycle
T0
T1
T3
T2
T4
T6
T5
T7
Burst length=8, CAS latency=2
T8
T9
CLK
Command
Write
Read
DQM
Q0
DQ
Q2
Q1
D0
D2
D1
Hi-Z is
necessary
example: Burst length=4, CAS latency=3
T0
T1
T2
T3
T4
T6
T5
T8
T7
CLK
Command
Read
Write
DQM
DQ
Q2
Hi-Z is
D0
D1
D2
necessary
The minimum command interval = (4+1) cycles
Document:1G5-0160
Rev.1
Page 24
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
10.BURST TERMINATION
There are two methods to terminate a BURST operation other than using a READ or a WRITE command.
One is the BURST STOP command and the other is the PRECHARGE command.
10.1 BURST STOP Command
During a READ BURST. when the BURST STOP command is asserted, the BURST READ outputs
are terminated and the data bus goes to high-impedance after the CAS latency from the BURST STOP
command.
During a WRITE BURST. when the BURST STOP command is asserted, any data provided at that
cycle will not be written. The BURST WRITE is effectively terminated and no further data can be written
until a new WRITE command is asserted.
Burst Termination
T0
T1
T3
T2
T4
Burst lengh=X, CAS Intency=2,3
T7
T6
T5
CLK
BST
Read
Command
CAS latency=2
DQ
Q0
CAS latency=3
Q1
Q2
Q0
Q1
Hi-Z
Hi-Z
Q2
DQ
Remark BST: Burst stop command
T0
T1
T3
T2
T4
T5
Burst lengh=X, CAS latency=2,3
T7
T6
CLK
Command
BST
Write
CAS latency=2,3
Q0
Q0
Q1
Q2
Hi-Z_
DQ
Remark BST: Burst stop command
Document:1G5-0160
Rev.1
Page 25
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
10.2 PRECHARGE TERMINATION
10.2.1 PRECHARGE TERMINATION in READ Cycle
During a READ cycle, the BURST READ operation can be terminated by a PRECHARGE
command. When the PRECHARGE command is asserted, the BURST READ operation is terminated and PRECHARGE starts.
Read data will remain valid until one clock(CAS latency of 2)or two clocks(CAS latency of 3)
after the PRECHARGE command and the same bank can be activated again after tRP(min) from
the PRECHARGE command.
PRECHARGE TERMINATION in READ Cycle
T0
T1
T3
T2
T4
T6
T5
T7
Burst lengh= X
T8
CLK
Command
PRE
Read
ACT
CAS latency=2
Q0
DQ
Q1
Q2
Hi-Z
Q3
tRP
command
Read
ACT
PRE
tRP
CAS latency=3
DQ
Document:1G5-0160
Q0
Rev.1
Q1
Q2
Q3
Hi-Z
Page 26
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
10.2.2 PRECHARGE TERMINATION in WRITE Cycle
During a WRITE cycle, the BURST WRITE operation can be terminated by a PRECHARGE
command. when the PRECHARGE command is asserted, the BURST WRITE operation in immediately terminated and PRECHARGE starts.
The same bank can be activated again after tRP(min.) from the PRECHARGE command. The
DQM must be high to mask invalid data in.
When CAS latency is 2 or 3, the data written prior to the PRECHARGE command will be correctly stored. However, invalid data may be written at the same clock as the PRECHARGE command. To prevent this from happening, DQM must be high at the same clock as the PRECHARGE
command. This will mask the invalid data.
PRECHARGE TERMINATION in WRITE Cycle
T0
T1
T3
T2
T4
T6
T5
T7
Burst lengh = X
T8
CLK
Command
PRE
Write
ACT
CAS latency=2
DQM
DQ
D0
D1
D2
D3
Hi-Z
D4
tRP
command
Write
PRE
ACT
CAS latency=3
DQM
DQ
D0
D1
D2
D3
D4
Hi-Z
tRP
Document:1G5-0160
Rev.1
Page 27
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Timing Diagram
Document:1G5-0160
Rev.1
Page 28
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Mode Register Set
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
CKE
t
RSC
CS
RAS
CAS
WE
A11(BS)
A10
A0-A9
Key
DQM
t
DQ
RP
Hi-Z
Precharge
Command
All Banks
Document:1G5-0160
Mode Register
Set Command
Rev.1
Command
Page 29
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
AC Parameters for Write Timing (1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
t
CL
t
CH
CKE
Begin Auto Precharge Begin Auto Precharge
Bank A
Bank B
t
CMS
t
CMH
t
CKS
t
CKH
CS
RAS
CAS
WE
A11(BS)
A10
RAa
t
t
AS
A0~A9
RBa
RAc
RBb
RAc
RBb
Activate
Command
Bank A
Activate
Command
Bank B
RAb
AH
RAa
RBa
CAa
CBa
RAb
CAb
DQM
t
RCD
DQ
t
RRD
t
DS
t
DAL
t
RC
t
DH
t
DPL
t
RP
DAa0 DAa1 DAa2 DAa3 DBa0 DBa1 DBa2 DBa3 DAb0 DAb1 DAb2 DAb3
Activate
Write with
Command Auto Precharge
Command
Bank A
Bank A
Document:1G5-0160
Write with
Activate
Command Auto Precharge
Command
Bank B
Bank B
Activate
Command
Bank A
Rev.1
Write with
Auto Precharge
Command
Bank A
Precharge
Command
Bank A
Page 30
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
AC Parameters for Write Timing (2 of 2)
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6
CLK
CKE
t
CL
t
CH
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
t
CK3
t
CMS
t
CKS
Begin Auto Precharge
Bank A
Begin Auto Precharge
Bank B
t
CKH
t
CMH
CS
RAS
CAS
WE
A11(BS)
A10
RAa
RBa
tAH
tAS
RAa
A0~A9
RAc
RAb
CAa
RBa
CBa
RAb
RAc
CAb
DQM
tRCD
DQ
t
DAL
t
RRD
tDS
tRC
DAa0 DAa1 DAa2 DAa3
Activate
Command
Bank A
Document:1G5-0160
Write with
Auto Precharge
Command
Bank A
Activate
Command
Bank B
t
DH
DBa0 DBa1 DBa2 DBa3
Write with
Auto Precharge
Command
Bank B
Rev.1
Activate
Command
Bank A
t
DPL
t
RP
DAb0 DAb1 DAb2 DAb3
Write without
Auto Precharge
Command
Bank A
Precharge
Command
Bank A
Activate
Command
Bank A
Page 31
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
AC Parameters for Read Timing (1 of 2)
Burst Length=2, CAS Latency=2
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
CLK
tCH tCL
tCK2
Begin Auto
Precharge
Bank B
tCMS
t
CMH
CKE
tCKS
t
CKH
CS
RAS
CAS
WE
A11(BS)
A10
RAa
tAS
A0-A9
RAb
RBa
tAH
RAa
CAa
RBa
CBa
RAb
tRRD
tRAS
tRC
DQM
t
AC2
tLZ
t
RCD
DQ
Hi-Z
QAa0
Activate
Command
Bank A
Document:1G5-0160
tAC2
tOH
Read
Command
Bank A
Activate
Command
Bank B
Rev.1
tHZ
tOH
QAa1
Read with
Auto Precharge
Bank B
tRP
tHZ
QBa0
Precharge
Command
Bank A
QBa1
Activate
Command
Bank A
Page 32
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
AC Parameters for Read Timing (2 of 2)
Burst Length=2, CAS Latency=3
T0
CLK
t
CH tCL
CKE
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14 T15
t
CK3
Begin Auto
Precharge
Bank B
t
CMS
tCKS
t
CMH
t
CKH
CS
RAS
CAS
WE
A11(BS)
A10
RBa
RAa
RAb
t
AH
t
AS
A0-A9
CAa
RAa
RAb
CBa
RBa
t
RRD
t
RAS
t
RP
t
RC
DQM
tAC3
tLZ
t
RCD
DQ
tAC3
tOH
tHZ
tOH
Hi-Z
QAa0
Activate
Command
Bank A
Document:1G5-0160
Read
Command
Bank A
Activate
Command
Bank B
Rev.1
QAa1
Read with
Auto Precharge
Command
Bank B
t
QBa0
Precharge
Command
Bank A
HZ
QBa1
Activate
Command
Bank A
Page 33
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Power on Sequence and Auto Refresh (CBR)
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
High level
is required
CKE
t
RSC
Minimum of 2 Refresh Cycles are required
CS
RAS
CAS
WE
A11(BS)
A10
Address Key
A0~A9
DQM
High Level is Necessary
t
RP
t
RC
DQ
Inputs
Precharge 1st Auto
must
Command Refresh
be stable All Banks Command
for 100us
Document:1G5-0160
2nd Auto
Refresh
Command
Rev.1
Mode
Command
Register
Set Command
Page 34
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Clock Suspension During Burst Read (Using CKE) (1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
CLK
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RAa
A0~A9
RAa
CAa
DQM
DQ
t
HZ
Hi-Z
QAa0
Activate
Command
Bank A
Document:1G5-0160
Read
Command
Bank A
QAa1
Clock
Suspended
1 Cycle
QAa2
QAa3
Clock
Suspended
2 Cycles
Rev.1
Clock
Suspended
3 Cycles
Page 35
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Clock Suspension During Burst Read (Using CKE) (2 of 2)
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7
CLK
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK3
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RAa
A0~A9
RAa
CAa
DQM
t
HZ
DQ
Hi-Z
QAa0
Activate
Command
Bank A
Document:1G5-0160
Read
Command
Bank A
QAa1
QAa2
Clock
Suspended
1 Cycle
Clock
Suspended
2 Cycles
Rev.1
QAa3
Clock
Suspended
3 Cycles
Page 36
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Clock Suspension During burst Write (Using CKE) (1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
CLK
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RAa
A0~A9
RAa
CAa
DQM
DQ
Hi-Z
QAa0
Activate
Command
Bank A
Document:1G5-0160
QAa1
Clock
Suspended
1 Cycle
Write
Command
Bank A
QAa2
Clock
Suspended
2 Cycles
QAa3
Clock
Suspended
3 Cycles
Rev.1
Page 37
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Clock suspension during Burst write (Using CKE) (2 of 2)
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7
CLK
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK3
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RAa
A0~A9
RAa
CAa
DQM
t
DQ
Hi-Z
QAa0
Activate
Command
Bank A
Document:1G5-0160
QAa1
Clock
Suspended
1 Cycle
Write
Command
Bank A
QAa2
Clock
Suspended
2 Cycles
QAa3
Clock
Suspended
3 Cycles
Rev.1
Page 38
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Power Down Mode and Clock Mask
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
CLK
t
CK2
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CKH
t
CKS
t
CKS
CKE
VALID
CS
RAS
CAS
WE
A11(BS)
A10
RAa
A0~A9
RAa
CAa
DQM
DQ
t
HZ
Hi-Z
QAa0 QAa1
Activate
Command
Bank A
ACTIVE
STANDBY
Power Down
Mode Entry
Document:1G5-0160
QAa2
Precharge
Command
Read
Command
Bank A
Power Down
Mode Exit
QAa3
Clock Mask
Start
Rev.1
Clock Mask
End
Power Down
Mode Entry
Precharge
Standby
Power
Down
Mode
Exit
Command
Page 39
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Auto Refresh (CBR)
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
CLK
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RAa
A0~A9
RAa
CAa
DQM
t
DQ
RP
t
RC
t
RC
Hi-Z
Q0
Precharge CBR Refresh
Command
Command
All Banks
Document:1G5-0160
CBR Refresh
Command
Rev.1
Q1
Q2
Q3
Activate
Read
Command Command
Page 40
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Self Refresh (Entry and Exit)
T0 T1 T2 T3 T4 T5 T6 T7
CLK
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
SRX
t
SRX
t
PDE
t
CKS
CKE
CS
RAS
CAS
WE
A11(BS)
A10
A0~A9
t
RC
t
RC
DQM
DQ
Hi-Z
All Banks
must be idle
Document:1G5-0160
Self refresh
Entry
Self Refresh
Exit
Self Refresh
Exit
Self Refresh
Exit
Rev.1
Activate
Command
Page 41
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Random Column Read (Page Within same Bank)(1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
CLK
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RAa
A0~A9
RAa
RAd
RAa
CAa
CAb
CAc
RAd
CAd
DQM
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QAb0 QAb1 QAc0 QAc1 QAc2 QAc3
Precharge
Command
Bank A
Document:1G5-0160
Read
Command
Bank A
Read
Read
Command Command
Bank A
Bank A
Rev.1
QAd0 QAd1 QAd2 QAd3
Precharge Activate
Read
Command Command Command
Bank A
Bank A
Bank A
Page 42
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Random Column Read (Page Within same Bank)(2 of 2)
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7
CLK
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK3
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RAa
A0~A9
RAa
RAd
CAa
CAb
CAc
RAd
CAd
DQM
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QAb0 QAb1 QAc0 QAc1 QAc2 QAc3
Activate
Command
Bank A
Document:1G5-0160
Read
Command
Bank A
Read
Read
Command Command
Bank A
Bank A
Rev.1
Precharge
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
Page 43
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Random Column Write (Page Within same Bank) (1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
CLK
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RAa
A0~A9
RBa
RAd
CBa
CBb
CBc
RBd
CBd
DQM
DQ
Hi-Z
DBa0 DBa1 DBa2 DBa3 DBb0 DBb1 DBc0 DBc1 DBc2 DBc3
Activate
Command
Bank B
Document:1G5-0160
Write
Command
Bank B
Write
Write
Command Command
Bank
B
Bank B
Rev.1
DBd0 DBd1 DBd2 DBd3
Precharge Activate
Write
Command Command Command
Bank B
Bank B
Bank B
Page 44
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Random Column Write (Page Within same Bank) (2 of 2)
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7
CLK
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK3
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RBa
A0~A9
RBa
RBd
CBa
CBb
CBc
CBd
RBd
DQM
DQ
Hi-Z
DBd0 DBd1 DBd2
DBa0 DBa1 DBa2 DBa3 DBb0 DBb1 DBc0 DBc1 DBc2 DBc3
Activate
Command
Bank B
Document:1G5-0160
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Rev.1
Precharge
Command
Bank B
Activate
Command
Bank B
Write
Command
Bank B
Page 45
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Random Row Read (Interleaving Banks) (1 of 2)
Burst Length=8, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
CLK
CKE
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
High
CS
RAS
CAS
WE
A11(BS)
A10
RBa
A0~A9
RBa
RBb
RAa
RAa
CBa
t
RCD
RBb
CAa
t
AC2
t
CBb
RP
DQM
DQ
Hi-Z
Activate
Command
Bank B
QBb0 QBb1
QBa0 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7
Read
Command
Bank B
Document:1G5-0160
Activate
Command
Bank A
Precharge Active
Command Command
Bank B
Bank B
Read
Command
Bank A
Rev.1
Read
Command
Bank B
Page 46
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Random Row Read (Interleaving Banks) (2 of 2)
Burst Length=8, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7
CLK
CKE
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK3
High
CS
RAS
CAS
WE
A11(BS)
A10
RBa
A0~A9
RBa
RBb
RAa
RAa
CBa
t
t
RCD
CAa
RBb
t
AC3
CBb
RP
DQM
DQ
Hi-Z
QBa0 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QBb0
Activate
Command
Bank B
Document:1G5-0160
Read
Command
Bank B
Activate
Command
Bank A
Read
Command
Bank A
Rev.1
Precharge
Command
Bank B
Activate
Command
Bank B
Read
Precharge
Command Command
Bank B
Bank B
Page 47
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Random Row Write (Interleaving Banks) (1 of 2)
Burst Length=8, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
CLK
CKE
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
High
CS
RAS
CAS
WE
A11(BS)
A10
RAa
A0~A9
RAa
DQ
CAa
RBa
t
RCD
DQM
RAb
RBa
Hi-Z
Activate
Command
Bank A
CBa
t
DPL
RAb
t
RP
CAb
t
DPL
QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QBa0 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 DAb0 DAb1 DAb2 DAb3 DAb4
Write
Command
Bank A
Document:1G5-0160
Activate
Command
Bank B
Precharge Active
Command Command
Bank A
Bank A
Write
Command
Bank B
Rev.1
Write
Command
Bank A
Precharge
Command
Bank B
Page 48
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Random Row Write (Interleaving Banks) (2 of 2)
Burst Length=8, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7
CLK
CKE
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK3
High
CS
RAS
CAS
WE
A11(BS)
A10
RAa
A0~A9
RAa
CAa
RBa
RAb
CBa
t
RCD
DQM
DQ
RBa
Hi-Z
Activate
Command
Bank A
Document:1G5-0160
RAb
t
DPL
CAb
t
DPL
t
RP
DAa0 DAa1 DAa2 DAa3 DAa4 DAa5 DAa6 DAa7 DBa0 DBa1 DBa2 DBa3 DBa4 QBa5 DBa6 DBb7 DAb0 DAb1 DAb2 DAb3
Write
Command
Bank A
Activate
Command
Bank B
Write
Command
Bank B
Rev.1
Precharge
Command
Bank A
Activate
Command
Bank A
Precharge
Write
Command Command
Bank B
Bank A
Page 49
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Read and Write Cycle (1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
CLK
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RAa
A0~A9
RAa
CAb
CAa
CAc
DQM
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3
Activate
Command
Bank A
Document:1G5-0160
Write
Command
Bank A
DAb0 DAb1
DAb3
The Write Data
Write
Command is Masked with a
Bank A
Zero Clock
latency
Rev.1
QAc0 QAc1
Read
Command
Bank A
QAc3
The Read Data
is Masked with
Two Clocks
Latency
Page 50
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Read and Write Cycle (2 of 2)
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK3
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RAa
A0~A9
RAa
CAa
CAb
CAc
DQM
DQ
Hi-Z
DAb0 DAb1
QAa0 QAa1 QAa2 QAa3
Activate
Command
Bank A
Read
Command
Bank A
DAb3
Write
The Write Data Read
Command is Masked with a Command
Bank A
Bank A
Zero Clock
latency
Document:1G5-0160
Rev.1
QAc0 QAc1
QAc3
The Read Data
is Masked with
Two Clock
Latency
Page 51
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Interleaved Column Read Cycle (1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RAa
A0~A9
RAa
CAb
t
DQM
DQ
RBa
RCD
RBa
CBa
CBb
CBc
CAb
CBd
t
AC2
Hi-Z
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBb0 QBb1 QBc0 QBc1 QAb0 QAb1 QBd0 QBd1 QBd2 QBd3
Activate
Command
Bank A
Document:1G5-0160
Read
Read
Read
Activate
Read
Read
Read
Command Command Command Command Command Command Command
Bank A
Bank A
Bank B
Bank B
Bank B
Bank B
Bank B
Precharge
Command
Bank A
Rev.1
Precharge
Command
Bank B
Page 52
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Interleaved Column Read Cycle (2 of 2)
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK3
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RAa
A0~A9
RAa
RBa
CAa
CBa
RBa
CBb
CBc
CAb
DQM
t
RCD
t
RRD
DQ
t
AC3
Hi-Z
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBb0 QBb1 QBc0 QBc1 QAb0 QAb1 QAb2 QAb3
Activate
Command
Bank A
Read
Command
Bank A
Read
Read
Read
Read
Precharge Precharge
Command Command Command Command Command Command
Bank A
Bank B
Bank B Bank B
Bank B
Bank A
Activate
Command
Bank B
Document:1G5-0160
Rev.1
Page 53
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Interleaved Column Write Cycle (1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RAa
A0~A9
RAa
RBa
CAa
RBa
CBa
CBb
CBc
CAb
t
RCD
CBb
t
RP
t
DPL
DQM
t
DQ
RRD
Hi-Z
DAa0 DAa1 DAa2 DAa3 DBa0 DBa1 DBb0 DBb1 DBc0 DBc1 DAb0 DAb1 DBd0 DBd1 DBd2 DBd3
Activate
Write
Write
Write
Write
Write
Activate
Command Command Command Command Command Command Command
Bank
B
Bank
B
Bank A
Bank
A
Bank
B
Bank B
Bank A
Document:1G5-0160
Rev.1
Precharge
Command
Bank A
Write
Command
Bank B
Precharge
Command
Bank B
Page 54
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Interleaved Column Write Cycle (2 of 2)
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK3
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RAa
A0~A9
RAa
RBa
CAa
RBa
CBa
CBb
t
RCD
CBc
CAb
CBd
t
DPL
t
DPL
DQM
t
DQ
t
RP
RRD
Hi-Z
DAa0 DAa1 DAa2 DAa3 DBa0 DBa1 DBb0 DBb1 DBc0 DBc1 DAb0 DAb1 DAd0 QAd1 QAd2 QAd3
Activate
Command
Bank A
Write
Command
Bank A
Write
Write
Write
Write
Write
Command Command Command Command Command
Bank A
Bank B
Bank B Bank B
Bank B
Activate
Command
Bank B
Document:1G5-0160
Precharge
Command
Bank B
Precharge
Command
Bank A
Rev.1
Page 55
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Auto Precharge after Read Burst (1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK2
High
Start Auto Precharge
Bank B
Start Auto Precharge
Bank A
Start Auto Precharge
Bank B
CS
RAS
CAS
WE
A11(BS)
A10
RAa
A0~A9
RAa
RBa
CAa
RBa
RBb
CBa
CAb
RBb
RAc
CBb
RAc
CAc
DQM
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QAc2
Activate
Read
Activate
Read with
Command Command Command Auto Precharge
Bank A
Bank A
Bank B Command
Bank A
Document:1G5-0160
Read with Activate
Activate
Auto Precharge Command
Command
Command Bank B Read with
Bank A
Bank A
Auto Precharge
Command
Read with
Bank B
Auto Precharge
Command
Bank A
Rev.1
Page 56
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Auto Precharge after Read Burst (2 of 2)
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK3
High
Start Auto Precharge
Bank B
Start Auto Precharge
Bank A
Start Auto Precharge
Bank B
CS
RAS
CAS
WE
A11(BS)
A10
RAa
A0~A9
RAa
RBa
CAa
RBa
RBb
CBa
CAb
RBb
CBb
DQM
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3 QBb0 QBb1 QBb2 QBb3
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank B
Document:1G5-0160
Read with
Auto Precharge
Command
Bank B
Read with
Read with
Auto Precharge
Auto Precharge
Command
Command
Bank A
Bank B
Activate
Command
Bank B
Rev.1
Page 57
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Auto Precharge after Write Burst (1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK2
High
Start Auto Precharge
Bank B
Start Auto Precharge
Bank A
Start Auto Precharge
Bank B
CS
RAS
CAS
WE
A11(BS)
A10
RAa
A0~A9
RAa
RBa
CAa
RBa
RBb
CBa
CAb
RBb
RAc
CBb
RAc
CAc
DQM
DQ
Hi-Z
DAa0 DAa1 DAa2 DAa3 DBa0 DBa1 DBa2 DBa3 DAb0 DAb1 DAb2 DAb3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DAc2 DAc3
Activate
Write
Write with
Activate
Command Command Command Auto Precharge
Command
Bank A
Bank B
Bank A
Bank B
Document:1G5-0160
Activate
Write with
Activate
Command
Auto Precharge Command
Bank A
Command
Bank B
Write with
Bank A
Write with
Auto Precharge
Auto Precharge
Bank A
Command
Bank B
Rev.1
Start Auto
Precharge
Bank A
Page 58
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Auto Precharge after Write Burst (2 of 2)
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK3
High
Start Auto Precharge
Bank B
Start Auto Precharge
Bank A
Start Auto Precharge
Bank B
CS
RAS
CAS
WE
A11(BS)
A10
RAa
A0~A9
RAa
RBa
CAa
RBa
RBb
CBa
RBb
CAb
CBb
DQM
DQ
Hi-Z
DAa0 DAa1 DAa2 DAa3 DBa0 DBa1 DBa2 DBa3 DAb0 DAb1 DAb2 DAb3
Activate
Command
Bank A
Activate
Command
Bank B
Write
Command
Bank A
Document:1G5-0160
Write with
Auto Precharge
Command
Bank B
Write with
Auto Precharge
Command
Bank A
Rev.1
Activate
Command
Bank B
DBb0 DBb1 DBb2 DBb3
Write with
Auto precharge
Command
Bank B
Page 59
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Full Page Read Cycle (1 of 2)
Burst Length=Full Page, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
CLK
CKE
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
High
CS
RAS
CAS
WE
A11(BS)
A10
RAa
A0~A9
RAa
RBb
RBa
CAa
CBa
RBa
RBb
t
RP
DQM
DQ
Hi-Z
QAa
Activate
Command
Bank A
Read
Command
Bank A
QAa+1 QAa+2 QAa-2 QAa-1
Activate
Command
Bank B
QAa
QAa+1 QBa
Read
Command
Bank B
Full page burst operation does not
terminate when the burst length is
satisfied; the burst counter
increments and continues bursting
beginning with the starting address
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Document:1G5-0160
QBa+1 QBa+2 QBa+3 QBa+4 QBa+51QBa+6
Precharge
Command
Bank B
Activate
Command
Bank B
Burst Stop
Command
Rev.1
Page 60
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Full Page Read Cycle (2 of 2)
Burst Length=Full Page, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7
CLK
CKE
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK3
High
CS
RAS
CAS
WE
A11(BS)
A10
RAa
A0~A9
RAa
RBb
RBa
CAa
CBa
RBa
RBb
t
RP
DQM
DQ
Hi-Z
QAa
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank B
QAa+1 QAa+2 QAa-2 QAa-1
QAa
Read
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Document:1G5-0160
QAa+1 QBa0
QBa+1 QBa+2 QBa+3 QBa+4 QBa+5
Full page burst operation
does not teminate when
the burst length is satisfied;
the burst counter increments
and continues bursting
beginning with the starting
address
Rev.1
Precharge
Command
Bank B
Activate
Command
Bank B
Burst Stop
Command
Page 61
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Full Page Write Cycle (1 of 2)
Burst Length=Full Page, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
CLK
CKE
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
High
CS
RAS
CAS
WE
A11(BS)
A10
RAa
A0~A9
RAa
RBb
RBa
CAa
RBb
CBa
RBa
DQM
DQ
t
BDL
Hi-Z
DAa
Activate
Command
Bank A
DAa+1 DAa+2 DAa+3 DAa-1
Write
Command
Bank A
DAa
DAa+1
Activate
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Document:1G5-0160
DBa
DBa+1 DBa+2 DBa+3 DBa+4 DBa+5 DBa+6
Write
Command
Bank B
Data is ignored
Full page burst operation
does not terminate when
the burst length is satisfied;
the burst counter increments
and continues bursting
beginning with the starting
address
Rev.1
Precharge
Command
Bank B
Activate
Command
Bank B
Burst Stop
Command
Page 62
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Full Page Write Cycle (2 of 2)
Burst Length=Full Page, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7
CLK
CKE
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK3
High
CS
RAS
CAS
WE
A11(BS)
A10
RAa
A0~A9
RAa
RBb
RBa
CAa
RBb
CBa
RBa
DQM
DQ
tBDL
Data is ignored.
Hi-Z
DAa
Activate
Command
Bank A
DAa+1 DAa+2 DAa+3 DAa-1
Write
Command
Bank A
DAa
DAa+1
Activate
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Document:1G5-0160
DBa
DBa+1 DBa+2 DBa+3 DBa+4 DBa+5
Write
Command
Bank B
Full page burst operation
does not terminate when
the burst length is satisfied;
the burst counter increments
and continues bursting
beginning with the starting
address
Rev.1
Precharge
Command
Bank B
Activate
Command
Bank B
Burst Stop
Command
Page 63
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Byte Write Operation
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
CLK
CKE
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
High
CS
RAS
CAS
WE
A11(BS)
A10
RAa
A0~A9
RAa
CAa
CAz
CAb
LDQM
UDQM
Hi-Z
DQ0~DQ7
DQ8~DQ15
Hi-Z
Activate
Command
Bank A
Read
Command
Bank A
Document:1G5-0160
Upper Byte
is masked
Lower Byte
is masked
Write
Command
Bank A
Read
Write Upper
Command
is masked
Bank A
Rev.1
Lower Byte
is masked
Lower Byte
is masked
Page 64
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Burst Read and Single Write Operation
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
CLK
CKE
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
High
CS
RAS
CAS
WE
A11(BS)
A10
RAa
A0~A9
RAa
CAa
CAb
CAc
CAd
CAe
LDQM
UDQM
Hi-Z
DQ0~DQ7
DQ8~DQ15
Hi-Z
Activate
Command
Bank A
Read
Command
Bank A
Document:1G5-0160
Read
Single Write Single Write
Command
Command
Command
Bank A
Bank A
Bank A
Rev.1
Lower Byte
is masked
Upper Byte
is masked
Single Write
Command
Bank A
Lower Byte
is masked
Page 65
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Full Page Random Column Read
Burst Length=Full Page, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
CLK
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RAa
RBa
A0~A9
RAa
RBa
RBb
CAa
CBa
CAb
CAc
CBb
CBc
RBb
t
RP
DQM
DQ
Hi-Z
QAa0 QBa0
Activate
Command
Bank A
Activate
Command
Bank B
Read
Command
Bank B
Read
Command
Bank A
Document:1G5-0160
QAb0
QAb1
Read
Command
Bank B
QBb0
QBb1
Read
Command
Bank A
QAc0
QAc1
QAc2
Read
Command
Bank B
QBc0
QBc1
QBc2
Precharge
Command Bank B
(Precharge Termination)
Activate
Command
Bank B
Read
Command
Bank A
Rev.1
Page 66
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Full Page Random Column Write
Burst Length=Full Page, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
CLK
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RAa
RBa
A0~A9
RAa
RBa
RBb
CAa
CBa
CAb
CAc
CBb
CBc
RBb
t
RP
DQM
DQ
Hi-Z
QAa0
Activate
Command
Bank A
Activate
Command
Bank B
QBa0
QAb1
Write
Command
Bank B
Write
Command
Bank A
Document:1G5-0160
QAb0
QBb0
QBb1
Write
Command
Bank B
QAc0
QAc1
Write
Command
Bank A
QAc2
QBc0
QBc1
Write
Command
Bank B
QBc2
Precharge
Command Bank B
(Precharge Termination)
Write Data
is masked
Write
Command
Bank A
Rev.1
Activate
Command
Bank B
Page 67
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Precharge Termination of a Burst (1 of 2)
Burst Length=4,8 or Full Page, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
CLK
CKE
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
High
CS
RAS
CAS
WE
A11(BS)
A10
RAa
A0~A9
RAa
RAb
CAa
RAb
t
DPL
t
RAc
CAb
RAc
t
RP
CAc
t
RP
RP
DQM
DQ
Hi-Z
QAa0
Activate
Command
Bank A
QAa1
Write
Command
Bank A
QAa2
QAb0
Da3
Precharge
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
Precharge Termination
of a Write Burst. Write
data is masked.
Document:1G5-0160
QAb1
QAb2
Precharge
Command
Bank A
Activate
Command
Bank A
QAc0
Read
Command
Bank A
QAc1
QAc2
Precharge
Command
Bank A
Precharge Termination
of a Read Burst.
Rev.1
Page 68
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Precharge Termination of a Burst (2 of 2)
Burst Length=4,8 or Full Page, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7
CLK
CKE
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK3
High
CS
RAS
CAS
WE
A11(BS)
A10
RAa
A0~A9
RAa
RAb
CAa
RAb
t DPL
DQM
DQ
t
t
RAc
CAb
t
RP
RAc
t
RAS
RP
RCD
Hi-Z
DAa0
Activate
Command
Bank A
Write
Command
Bank A
Precharge
Command
Bank A
Write Data
is masked
Document:1G5-0160
QAb0
DAa1
Activate
Command
Bank A
Read
Command
Bank A
QAb1
QAb2
Activate
Command
Bank A
QAb3
Activate
Command
Bank A
Precharge Termination
of a Read Burst.
Precharge Termination
of a Write Burst.
Rev.1
Page 69
VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Ordering information
Part Number
Frequency@CL3
Package
166MHz
143MHz
125MHz
100MHz
400mil
50-Pin
Plastic TSOP
VG3617161DT-6
VG3617161DT-7
VG3617161DT-8
VG3617161DT-10
VG3617161DT- 6
• VG
• VIS Memory Product
• 36
• Technology/Design Rule
• 17161
• Device Type/Configuration
•B
• Mask/Design Version
•T
• Package Type, T: TSOP
•6
• Cycle time, 6: 6ns, 7: 7ns, 8: 8ns, 10: 10ns
Packaging Information
•400mil, 50-Pin Plastic TSOP
MILLIMETERS
DIM
MIN.
A
---
INCHES
NOM.
MAX.
MIN.
NOM.
---
1.20
---
---
0.047
MAX.
A1
0.05
---
0.15
0.002
---
0.006
A2
0.95
1.00
1.05
0.037
0.039
0.041
b
0.30
---
0.45
0.012
---
0.018
b1
0.30
---
0.40
0.012
---
0.016
c
0.12
---
0.21
0.005
---
0.008
c1
0.11
---
0.16
0.0045
---
0.006
21.08
0.820
0.825
0.830
D
20.82
ZD
20.95
0.875 REF.
e
50
26
RAD R1
RAD R
A2
B
E1
A1
L
DETAIL A
0¢X~5¢X
b
0.0344 REF.
0.80 BASIC
c
B
b1
0.0315 BASIC
E
11.56
11.76
11.96
0.455
0.463
0.471
E1
10.03
10.16
10.29
0.395
0.400
0.405
L
0.40
0.50
0.60
0.016
0.020
0.024
R
0.11
---
0.25
0.004
---
0.010
R1
0.11
---
---
0.004
---
---
1
SECTION B-B
25
D
c1
c
BASE METAL
WITH PLATING
NOTE:
1. CONTROLLING DIMENSION : MILLIMETERS
2. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION.
MOLD PROTRUSION SHALL NOT EXCEED 0.15mm(0.006") PER SIDE.
DIMENSION E1 DOES NOT INCLUDE INTERLEAD PROTRUSION.
INTERLEAD PROTRUSION SHALL NOT EXCEED 0.25mm(0.01") PER SIDE.
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSIONS/INTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD TO
BE WIDER THAN THE MAX b DIMENSION BY MORE THAN 0.13mm.
DAMBAR INTRUSION SHALL NOT CAUSE THE LEAD TO BE NARROWER
THAN THE MIN b DIMENSION BY MORE THAN 0.07mm.
Document:1G5-0160
DETAIL A
ZD
A
E
b
48- e
SEATING PLANE
0.100(0.004)
Rev.1
Page 70