VML VG37648041AT

VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
Description
The 256Mb DDR SDRAM is a high-speed COMS, dynamic random-access memory containing
268,435,456 bits. It is internally configured as a quad-bank DRAM.
The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write
access for the 256Mb DDR SDRAM effectively consists of a single 2n-bit wide, one clock cycle
data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle
data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data
capture at the receiver. DQS is an intermittent strobe transmitted by the DDR SDRAM during
READs and by the memory controller during WRITEs. DQS is edge-aligned with data for
READs and center-aligned with data for WRITEs.
The 256Mb DDR SDRAM operates from a differential clock (CLK and CLK#; the crossing of
CLK going HIGH and CLK# going LOW will be referred to as the postive edge of CLK). Commands (address and control signals) are registered at verey positive edge of CLK. Input data is
registered on both edges of DQS, and output data is referenced to both edges of DQS, as well
as to both edges of CLK.
Read and Write assesses to the DDR SDRAM are burst oriented; accesses start at a
selected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then followed
by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0,BA1 select the bank; A0-A12
select the row). The address bits registered coincident with sthe READ or WRITE command
are used to select the starting column location for the burst access.
The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2,4 or 8
locations. An AUTO PRECHARGE function may be enabled to provide a selftimed row precharge that is initiated at the end of the burst access.
As with standard SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows
for concurrent operation, thereby providing high effective bandwidth by hiding row precharge
and activation time.
The 256Mb DDR SDRAM is designed to operate in either low-power memory systems. An
auto refresh mode is provided, along with a power-saving, power-down mode. All inputs are
compatible with the JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class II compatible.
Initial devices will have a VDD supply of 3.3V (nominal). Eventually, all devices will migrate
to a VDD supply of 2.5V(nominal). During this initial period of product availability. this split will
be vendor and device specific.
This data sheet includes all features and functionality required for JEDEC DDR devices;
options not required but listed, are noted as such. Certain vendors may elect to offer a superset
of this specification by offering improved timing and/or including optional features. Users benefit
from knowing that any system design based on the required aspects of this specification are
supported by all DDR SDRAM vendors; conversely, users seeking to use any superset specifications bear the responsibility to verify support with individual vendors.
Document : 1G5-0157
Rev.1
Page 1
VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
Note: The functionality described in, and the timing specifications included in this data
sheet are for the DLL Enabled mode of operation. This is the only normal operating
mode for these DDR devices.
Features
• Double-data-rate architecture: two data transfers per clock cycle
• Bidirectional, intermittent data strobe (DQS) is transmitted/received with data, to be used in
capturing data at the receiver
• DQS is edge-aligned with data for READs: center-aligned with data for WRITEs
• Differential clock inputs (CLK and CLK#)
• DLL aligns DQ and DQS transitions with CLK transitions
• Commands entered on each positive CLK edge; data referenced to both edges of DQS
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• Burst lengths:2,4, or 8
• CAS Latency: 2 or 2.5
• AUTO PRECHARGE option for each burst access
• Auto Refresh and Self Refresh Modes
• 7.81us Auto Refresh Interval
• 2.5V (SSTL_2 compatible) I/O
• VDDQ=+2.5V
• VDD=+3.3V
± 0.2V
± 0.3V
Document : 1G5-0157
Rev.1
Page 2
VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
Pin Configuration
256M DDR SDRAM (x4/x8/x16) Pin-out
64M X 4
32M X 8
16M X 16
66
VSS
VSS
VSS
65
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
NC
VSSQ
NC
DQ3
VDDQ
NC
NC
VSSQ
NC
DQ2
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DQS
NC
VREF
VSS
UD
DM
VDD
VDD
VDD
1
NC
DQ0
DQ0
2
VDDQ
VDDQ
VDDQ
3
NC
NC
DQ1
4
DQ0
VSSQ
DQ1
VSSQ
DQ2
VSSQ
5
66 PIN TSOP(II)
(400 mil x 875 mil)
6
(0.65 mm PIN PITCH) 61
NC
NC
DQ3
NC
DQ2
DQ4
7
8
VDDQ
VDDQ
VDDQ
9
NC
NC
DQ5
DQ1
DQ3
DQ6
10
11
VSSQ
VSSQ
VSSQ
12
13
Top View
64
63
62
60
Bank Address:
BA0-BA1
59
58
57
Row Address:
A0-A12
56
55
54
NC
NC
NC
NC
DQ7
NC
14
VDDQ
VDDQ
VDDQ
15
NC
NC
NC
NC
LDQS
NC
16
51
17
50
VDD
VDD
VDD
18
49
NC
LDM
19
48
UDQS
NC
VREF
VSS
20
47
UDM
46
CK
CK
CK
45
CK
CKE
NC
CK
CKE
NC
CK
CKE
NC
A12
A11
A12
A11
A12
A11
A9
A8
A9
A8
A7
A6
A7
A6
NC
NC
NC
NC
WE
WE
WE
21
CAS
CAS
CAS
22
RAS
Auto Precharge:
A10
53
52
RAS
RAS
23
44
CS
CS
CS
24
43
NC
BA0
NC
BA0
NC
BA0
25
42
26
41
27
40
BA1
BA1
A10/AP A10/AP
A0
A0
A1
A1
A2
A2
A3
A3
VDD
VDD
BA1
A10/AP
A0
A1
A2
A3
VDD
28
39
A9
A8
29
38
37
A7
A6
30
31
36
A5
A5
A5
32
35
33
34
A4
VSS
A4
VSS
A4
VSS
Column Address Table
Document : 1G5-0157
Organization
Column Address
64Mx4
A0-A9,A11
32Mx8
A0-A9
16Mx16
A0-A8
Rev.1
Page 3
VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
FUNCTIONAL BLOCK DIAGRAM- X4 CONFIGURATION
CKE
CLK#
CLK
Generator
COMMAND
DECODE
CS#
WE#
CAS#
RAS#
LOGIC
BANK2
BANK1
MODE REGISTERS
REFRESH
COUNTER 13
ROWADDRESS
MUX
BANK3
CLK
13
13
8192
13
BANK0
BANK0
ROWMEMORY
ADDRESS 8192
ARRAY
LATCH
(8192x1024x8)
&
DECODER
SENSE AMPLIFIERS
DATA
DLL
4
8
READ
LATCH
15
COL0
MASK
ADDRESS
RESGISTER
(x8)
COLUMN
DECODER
10
11
1
COLUMN
ADDRESS
COUNTER/
LATCH
8
WRITE
FIFO
&
DRIVERS
ctk ctk
out in
CLK
COL0
DO0
DQ3,DM
INPUT
REGISTERS
1
1
I/O GATING
DM MASK LOGIC
BANK0
CONTROL
LOGIC
1024
A0-A12
BA0-BA1
DRVRS
DQS
GENERATOR
8
2
2
4
MUX
4
2
8
DOS
1
1
1
4
4
RCVRS
4
4
4
DATA
COL0
1
1
Note 1: This Functional Block Diagram is intended to facilitate user understanding of the operation of the
device; it does not necessarily represent an actual circuit implementation.
Note 2: DM is a unidirectional signal (input only) but is internally loaded to match the load of the bidirectional
DQ and DQS signals.
Document : 1G5-0157
Rev.1
Page 4
DQS
VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
FUNCTIONAL BLOCK DIAGRAM- X8 CONFIGURATION
CKE
CLK#
CLK
Generator
COMMAND
DECODE
CS#
WE#
CAS#
RAS#
LOGIC
BANK2
BANK1
MODE REGISTERS
REFRESH
COUNTER 13
ROWADDRESS
MUX
BANK3
CLK
13
13
8192
13
BANK0
BANK0
ROWMEMORY
ADDRESS 8192
ARRAY
LATCH
(8192x512x16)
&
DECODER
SENSE AMPLIFIERS
DATA
16
READ
LATCH
15
1
MASK
(x16)
COLUMN
DECODER
9
COLUMN
ADDRESS
COUNTER/
LATCH
16
WRITE
FIFO
&
DRIVERS
ctk ctk
out in
CLK
COL0
DO0
DQ7,DM
INPUT
REGISTERS
1
1
I/O GATING
DM MASK LOGIC
BANK0
CONTROL
LOGIC
ADDRESS
RESGISTER
10
DRVRS
DQS
GENERATOR
16
COL0
512
A0-A12
BA0-BA1
4
MUX
8
2
2
DLL
8
2
16
DQS
1
1
1
8
8
RCVRS
8
8
8
DATA
COL0
1
1
Note 1: This Functional Block Diagram is intended to facilitate user understanding of the operation of the
device; it does not necessarily represent an actual circuit implementation.
Note 2: DM is a unidirectional signal (input only)m but is internally loaded to match the load of the bidirectional DQ and DQS signals.
Document : 1G5-0157
Rev.1
Page 5
DQS
VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
FUNCTIONAL BLOCK DIAGRAM- X16 CONFIGURATION
CKE
CLK#
CLK
Generator
COMMAND
DECODE
CS#
WE#
CAS#
RAS#
LOGIC
BANK2
BANK1
MODE REGISTERS
REFRESH
COUNTER 13
ROWADDRESS
MUX
BANK3
CLK
13
13
8192
13
BANK0
BANK0
ROWMEMORY
ADDRESS 8192
ARRAY
LATCH
(8192x256x32)
&
DECODER
SENSE AMPLIFIERS
DATA
32
READ
LATCH
15
1
MASK
(x32)
COLUMN
DECODER
8
COLUMN
ADDRESS
COUNTER/
LATCH
32
WRITE
FIFO
&
DRIVERS
ctk ctk
out in
CLK
COL0
DO0DQ15,LDM
UDM
INPUT
REGISTERS
1
1
I/O GATING
DM MASK LOGIC
BANK0
CONTROL
LOGIC
ADDRESS
RESGISTER
9
DRVRS
DQS
GENERATOR
32
COL0
256
A0-A12
BA0-BA1
16
MUX
16
2
2
DLL
16
2
32
DQS
1
1
1
16
16
RCVRS
16
16
DATA
16
COL0
1
1
Note 1: This Functional Block Diagram is intended to facilitate user understanding of the operation of the
device; it does not necessarily represent an actual circuit implementation.
Note 2: LDM and VDM are unidirectional signal (input only) but is internally loaded to match the load of the
bidirectional DQ and DQS signals.
Document : 1G5-0157
Rev.1
Page 6
LDQS,
UDQS
VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
PIN DESCRIPTIONS
Symbol
Type
Description
CLIK,CLK#
Input
Clock: CLK and CLK# are differential clock inputs. All address and control input signals
are sampled on the positive edge of CLK/negative edge of CLK#. Ouptut(read) data is
referenced to both edges of CLK. Internal clock signals are dervied from CLK/CLK#.
CKE
Input
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals,
and device input buffers and output drivers. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE
POWER-DOWN (row ACTIVE in any bank). CKE is synchronous for all functions
except for disabling outputs, which is achieved asynchronously. Input buffers, excluding
CLK, CLK# and CKE are disabled during power-down and self refresh modes, providing low standby power. CKE will recognize an LVCMOS LOW level prior to VREF being
stable on power-up.
CS#
Input
Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides
for external bank selection on systems with multiple banks. CS# is considered part of
the command code.
RAS#,CAS#,
WE#
Input
Command Inputs: RAS#, CAS# and WE# (along with CS#) define the command being
entered.
DM
Input
Input Data Mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH along with that input data during a WRITE access. DM is sampled
on both edges of DQS. DM pins include dummy loading internally, to match the DQ and
DQS loading. For the x16, LDM corresponds to the data on DQ0-DQ7; UDM corresponds to the data on DQ8-DQ15.
BA0,BA1
Input
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or
PRECHARGE command is being applied.
A0-A12
Input
Address Inputs: Provide the row address for ACTIVE commands, and the column
address and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine whether the PRECHARGE applies to one bank (A10
LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is
selected by BA0,BA1. The address inputs also provide the op-code durinbg a LOAD
MODE REGISTER command.
DQ
I/O
Data Input/Output: Data bus
DQS
I/O
Data Strobe: Output with read data, input with write data. Edge-aligned with read data,
centered in write data. Used to capture write data. For the x16, LDQS corresponds to
the data on DQ0-DQ7; UDQS corresponds to the data on DQ8-DQ15.
NC
-
No Connect: these pins should be left unconnected.
VDDQ
Supply
DQ Power Supply:+2.5V
VSSQ
Supply
DQ Ground.
VDD
Supply
Power Supply: +3.3V
VSS
Supply
Ground.
VREF
Input
Document : 1G5-0157
± 0.2V .
± 0.3V .
SSTL_2 reference voltage.
Rev.1
Page 7
VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
Description
The 256Mb DDR SDRAM is a high-speed COMS, dynamic random-access memory containing
268,435,456 bits. The 256Mb DDR SDRAM is internally configured as a quad bank DRAM.
The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write
access for the 256Mb DDR SDRAM effectively consists of a single 2n-bit wide, one clock cycle
data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle
data transfers at the I/O pins.
Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a
selected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command. which is then followed
by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0,BA1 select the bank; A0-A11
select the row). The address bits registered coincident with the READ or WRITE command are
used to select the starting column location for the burst access.
Prior to normal operation, the DDR SDRAM must be initialized. the following sections provide detailed information covering device initialization, register definition, command descriptions and device operation.
Initialization
DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power must first be applied to
VDD, then to VDDQ, and finally to VREF (and to the system VTT). VTT must be applied after VDDQ
to avoid device latch-up, which may cause permanent damage to the device. VREF can be applied
any time after V DDQ, but is expected to be nominally coincident with VTT. Except for CKE, inputs
are not recognized as valid until after V REF is applied. CKE is an SSTL_2 input, but will detect an
LVCMOS LOW level after V DD is applied. Maintaining an LVCMOS LOW level on CKE during
power-up will put the DQ and DQS outputs in the High-Z stage, where they will remain until driven
in normal operation (by a read access). After all power supply and reference voltages are stable,
and the clock is stable, the DDR SDRAM requires a 200 µ s delay prior to applying an executable
a command.
Once the 200 µ s delay has been satisfied, a COMMAND INHIBIT or NOP comand should be
applied, and CKE should be brought HIGH. Following the NOP command, a PRECHARGE ALL
command should be applied. Next a LOAD MODE REGISTER command should be issued for the
Extended Mode Register to enable the DLL, then a LOAD MODE REGISTER comand should be
issued for the base mode Register, to reset the DLL, and to program the operating parameters.
200 clock cycles are required between the DLL reset and any read command. A PRECHARGE
ALL command should be applied, placing the device in the “all banks idle” stage.
Document : 1G5-0157
Rev.1
Page 8
VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
Once in the idle state, two AUTO REFRESH cycles must be performed. Additionally, a LOAD
MODE REGISTER command for the base Mode Register, with the reset DLL bit deactivated (i.e.
to program operating parameters without resetting the DLL) must be performed. Following these
cycles, the DDR SDRAM is ready for normal operation.
Register Definition
Base Mode Register
The base mode register is used to define the specific mode of operation of the DDR SDRAM.
This definition includes the selection of a burst length, a burst type, a CAS latency, and an operating mode, as shown in Figure 1. The base mode register is programmed via the LOAD MODE
REGISTER command (with BA0=0 and BA1=0) and will retain the stored information unitil it is
programmed again or the device loses power.
Base mode register bits M0-M2 specify the burst length, M3 specifies the type of burst
(sequential or interleaved), M4-M6 specify the CAS latency, and M7-M11 specify the operating
mode.
The base mode register must be loaded when all banks are idle, and the controller must wait
the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation.
Burst Length
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being
programmable, as shown in Figure 1. the burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4,
or 8 locations are available for both the sequential and the interleaved burst types.
Reserved states should not be used, as unknown operation or incompatibility with future
versions may result.
When a READ or WRITE command is issued, a block of columns equal to the burst length is
effectively selected. All accesses for that burst take place within this block, meaning that the burst
will wrap within the block if a boundary is reached. The block is uniquely selected by A1-Ai when
the burst length is set to two, by A2-Ai when the burst length is set to four and by A3-Ai when the
burst length is set to eight (where Ai is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location
within the block. The programmed burst length applies to both READ and WRITE bursts.
Document : 1G5-0157
Rev.1
Page 9
VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
Burst Type
BA0 BA0 A12 A11 A10 A9
14 13 12 11 10 9
0* 0*
A8
A7 A6
7 6
8
Operating Mode
A4 A3
A5
5 4
3
A1
A2
Address Bus
A0
1 0
2
Mode Register (Mx)
CAS Latency BT Burst Length
* M13 and M14 (BA0 and BA1)
must be 0,0 to select the
base mode register (vs. the
extended mode register).
Burst Length
M2 M1 M0
M12 M11
M3=1
0
0
0
Reserved
Reserved
0
0
1
2
2
0
1
0
4
4
0
1
1
8
8
1
0
0
Reserved
Reserved
1
0
1
Reserved
Reserved
1
1
0
Reserved
Reserved
1
1
1
Reserved
Reserved
M3
Burst Type
0
Sequential
1
Interleaved
M6 M5 M4
M3=0
CAS Latency
0
0
0
Reserved
0
0
1
Reserved
0
1
0
2
0
1
1
3(optional)
1
0
0
Reserved
1
0
1
1.5(optional)
1
1
0
2.5
1
1
1
Reserved
M10
M9
M8
M7
M6-10
Operating Mode
0
0
0
0
0
0
Valid
Normal Operation
0
0
0
0
1
0
Valid
Normal Operation/Reset DLL
-
-
-
-
-
-
-
All other states reserved
Figure 1
BASE MODE REGISTER DEFINITION
Document : 1G5-0157
Rev.1
Page 10
VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
Table 1
BURST DEFINITION
Burst Length
Starting Column
Address:
Order of Accesses Within a Burst
A0
2
0
0-1
0-1
1
1-0
1-0
0
0-1-2-3
0-1-2-3
0 1
1-2-3-0
1-0-3-2
1 0
2-3-0-1
2-3-0-1
1 1
3-0-1-2
3-2-1-0
A1-A0
0
4
A2 A1 A0
8
0
0
0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
0
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
NOTE:
1. For a burst length of two, A1-Ai selects the two-data-element block; A0 selects the first access within the block.
2. For a burst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within the block.
3. For a burst length of eight, A3-Ai selects the eight-data-element block; A0-A2 selects the first access within the block.
4.Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the
block.
Document : 1G5-0157
Rev.1
Page 11
VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred
to as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the burst length, the burst type and the starting
column address, as shown in Table 1.
Read Latency
The READ latency is the delay, in clock cycles, between the registration of a READ command and the
availability of the first piece of output data. The latency can be set to 2 or 2.5 clocks (latencies of 1.5 or 3
are optional, and one or both of these optional latencies might be supported by some vendors).
If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available
nominally coincident with clock edge n + m. Table 2 below indicated the operating frequencies at which
each CAS latency setting can be used.
Reserved stated should not be used as unknown operation, or incompatibility with future versions may
result.
Operating Mode
The normal operating mode is selected by setting M7-M12 to zero; to reset the DLL and select normal
operation , program M7, M9-M12 to 0 and M8 to 1. All other combinations of values for M7-M12 are
reserved for future use and/ or test modes.
Test Modes and reserved states should not be used because unknown operation or incompatibility with
future versions may result.
Table 2
CAS LATENCY
MAXIMUM OPERATING
CAS
LATENCY
=1.5
CAS
LATENCY
=2
CAS
LATENCY
=2.5
CAS
LATENCY
=3
-75
100
133
150
200
-8
100
125
143
166
SPEED
GRADE
* Values are nominal (i.e. may have been rounded off; exact tCK should be used)
Document : 1G5-0157
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Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
CLK#
CLK
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tAC
max
CL=2
DQS
DQ
tAC
min
CLK#
CLK
COMMAND
READ
NOP
NOP
tAC
max
CL=2.5
DQS
DQ
AC
DON’T CARE
UNDEFINED
Burst Length=4 in the cases shown
Figure 2a
REQUIRED CAS LATENCIES
Document : 1G5-0157
Rev.1
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VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
CLK#
CLK
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tAC
max
CL=1.5
DQS
DQ
tAC
min
CLK#
CLK
COMMAND
READ
NOP
tAC
max
CL=3
DQS
DQ
tAC
min
DON’T CARE
UNDEFINED
Burst Length=4 in the cases shown
Figure 2b
OPTIONAL CAS LATENCIES
Document : 1G5-0157
Rev.1
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VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
EXTENDED MODE REGISTER
The Extended Mode Resister is used to enable or disable the DLL of the DDR SDRAM, as shown in Figure
3. The Extended Mode Register is programmed via the LOAD MODE REGISTER command (with BA0=1 and
BA1=0) and will retain the stored information until it is programmed again or the device loses power.
The Extended Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Voolating either of these requirements will result in
unspecified operaiton.
BA0 BA1 A12 A11 A10 A9
14 13 12 11 10 9
1* 0*
A8
8
A7 A6
7 6
A4 A3
A5
5 4
A2
2
3
A1
Address Bus
A0
1 0
Operating Mode
Extended Mode Register (Ex)
DLL
* E13 and E12 (BA0 and BA1)
must be 1,0 to select the
Extended Mode Register (vs. the
base Mode Register).
E0
DLL
0
Enable
1
Disable
E12
E11
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
E0
Operating Mode
0
0
0
0
0
0
0
0
0
0
0
0
Valid
Normal Operation
-
-
-
-
-
-
-
-
-
-
-
-
-
All other stateds reserved
Figure 3
EXTENDED MODE REGISTER DEFINITION
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Rev.1
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Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
COMMANDS
Truth Table 1 provides a quick reference of available commands. This is followed by a verbal description of
each command. Two additional Truth Tables appear following the Operation section; these tables provide current state/next state information.
TRUTH TABLE 1-Commands and DM Operation
(Notes:1)
Burst Length
CS#
RAS#
CAS#
WE#
DM
ADDR
DQs
NOTES
COMMAND INHIBIT (NOP)
H
X
X
X
X
X
X
NO OPERATION (NOP)
L
H
H
H
X
X
X
ACTIVE (Select bank and activate row)
L
L
H
H
X
Bank/Row
X
3
READ (Select bank and column, and start
READ burst)
L
H
L
H
X
Bank/col
X
4
WRITE (Select bank and column, and
start WRITE burst)
L
H
L
L
X
Bank/Col
Valid
4
BURST TERMINATE
L
H
H
L
X
X
Active
9
PRECHARGE (Deactivate row in bank or
banks)
L
L
H
L
X
Code
X
5
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
L
L
L
H
X
X
X
6,7
LOAD MODE REGISTER
L
L
L
L
X
Op-Code
X
2
Write Enable
-
-
-
-
L
-
Active
8
Write Inhibit
-
-
-
-
H
-
High-Z
8
NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH.
2. BA0-BA1 select either the Base or the Extended Mode Register (BA0=0, BA=1 selects Base
Mode Register; BA0=1, BA1=0 selects Extended Mode Register; other combinations of BA0-BA1
are reserved; A0-A12 provide the op-code to be written to the selected mode Register.
3. BA0-BA1 provide bank address and A0-A12 provide row address.
4. BA0-BA1 provide bank address; A0-Ai provide column address (where i=8 for x16, 9 for x8 and 11
for x4 except A10); A10 HIGH enables the auto precharge feature (nonpersistent), A10 LOW disables the auto precharge feature.
5. A10 LOW: BA0-BA1 determine which bank is precharged.
A10 HIGH: all banks are precharged and BA0-BA1 are “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Used to mask write data; provided conicident with the corresponding data.
9. Applies only to read bursts with autoprecharge disabled; this command is undefined (and should
not be used) for read bursts with autoprecharge enabled, and for write bursts
Document : 1G5-0157
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Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
COMMAND INHIBIT
The COMMAND INHIBIT function prevents new commands from being executed by the DDR SDRAM.
The DDR SDRAM is effectively deselected. Operations already in progress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform a NOP to an DDR SDRAM which is selected
(CS# is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected.
LOAD MODE REGISTER
The mode registers are loaded via inputs A0-A12 See mode register descriptions in the Register Definition section. The LOAD MODE REGISTER command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met.
ACTIVE
The ACTIVE command is used to open (or activate) a row in particular bank for a subsequent access. The
value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A12 selects the row.
This row remains active (or open) for accesses until a PRECHARGE command is issued to that bank . A
PRECHARGE command must be issued befor opening a different row in the same bank.
READ
The READ command is used to initaiate a burst read access to an active row. The value on the BA0, BA1
inputs selects the bank, and the address provided on inputs A0-Ai(where i=8 for x 16, 9 for x8 or 11 for x 4,
except A10) selects the starting column location. The value on input A10 determines whether or not AUTO
PRECHARGE is used. If AUTO PRECHARGE is selected, the row being accessed will be precharged at the
end of the READ burst; if AUTO PRECHARGE is not selected, the row will remain open for subsequent
accesses.
WRITE
The WRITE command is used to initaiate a burst write access to an active row. The value on the BA0,
BA1 inputs selects the bank, and the address provided on inputs A0-Ai(where i=8 for x 16, 9 for 8 or 11 for x
4, except A10) selects the starting column location. The value on input A10 determines whether or not
AUTO PRECHARGE is used. If AUTO PRECHARGE is selected, the row being accessed will be precharged at the end of the WRITE burst; if AUTO PRECHARGE is not selected, the row will remain open for
subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DM
input logic level appearing coincident whith the data. If a given DM signal is registered LOW, the corresponding data will be written to memory; if the DM signal is registered HIGH, the corresponding data inputs
will be ignored, and a WRITE will not be executed to that byte/column location.
Document : 1G5-0157
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Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all
banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in
the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1
are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated
prior to any READ or WRITE commands being issued to that bank.
AUTO PRECHARGE
AUTO PRECHARGE is a feature which performs the same individual-bank precharge function described
above, but without requiring an explicit command. This is accomplished by using A10 to enable AUTO PRECHARGE in conjunction with a specific READ or WRITE command. A precharge of the bank/row that is
addressed with the READ or WRITE command is automatically performed upon completion of the READ or
WRITE burst. AUTO PRECHARGE is nonpersistent in that it is either enabled or disabled for each individual
READ or WRITE command.
AUTO PRECHARGE ensures that the precharge is initiated at the earliest valid stage within a burst. The
user must not issue another command to the same bank until the precharge time ( tRP) is completed. This is
determined as if an explicit PRECHARGE command was issued at the earliest possible time, as described
for each burst type in the Operation section of this data sheet.
BURST TERMINATE
The BURST TERMINATE command is used to truncate read bursts (with autoprecharge disabled). The
most recently registered READ command prior to the BURST TERMINATE command will be truncated, as
shown in the Operation section of this data sheet.
AUTO REFRESH
AUTO REFRESH is used during normal operation of the DDR SDRAM and is analagous to CAS#
BEFORE-RAS# (CBR) REFRESH in conventional DRAMs. This command is nonpersistent, so it must be
issued each time a refresh is required.
The addressing is generated by the internal refresh controller. This makes the address bits a “Don’t Care”
during an AUTO REFRESH command. The 256Mb DDR SDRAM requires AUTO REFRESH cycles at an
average interval of 7.81 µ s(maximum).
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Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
SELF REFRESH
The SELF REFRESH command can be used to retain data in the DDR SDRAM, even if the rest of the
system is powered down. When in the self refresh mode,the DDr SDRAM retains data without external
clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). The DLL is automatically disabled upon entering SELF REFRESH, and is automatically
enabled upon exiting SELF REFRESH (200 clock cycles must then occur befor a READ command can be
issued). Input signals except CKE are “Don’t Care” during SELF REFRESH.
Once self refresh mode is engaged, the DDR SDRAM provides its own internal clocking, causing it to perform its own AUTO REFRESH cycles. The DDR SDRAM must remain in self refresh mode for a minimum
period equal to tRAS and may remain in self refresh mode for an indefinite period beyond that.
The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable prior
to CKE going back HIGH. Once CKE is HIGH, the DDR SDRAM must have NOP commands issued for
t
XSR because time is required for the completion of any internal refresh in progress. A simple algorithm for
meeting both refresh and DLL requirements is to apply NOPs for 200 clock cycles before applying any other
command.
OPERATIONS
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be issued to a bank within the DDR SDRAM, a row in that
bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and
the row to be activated.
After opening a row (issuing an ACTIVE command). a READ or WRITE command may be issued to that
row, subject to the tRCD specification.
A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous
active row has been “closed” (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC.
A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed,
which results in a reduction of total row-access overhead. The minimum time interval between successive
ACTIVE commands to different banks is defined by tRRD.
Document : 1G5-0157
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Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
CLK#
CLK
CKE
HIGH
CS#
RAS#
CAS#
WE#
A0-A12
BA0,1
RA
BA
=DON’T CARE
RA =Row Address
BA =Bank Address
Figure 4
ACTIVATING A SPECIFIC ROW IN A SPECIFIC BANK
Document : 1G5-0157
Rev.1
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VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
CLK#
CLK
COMMAND
A0-A12
BA0,BA1
ACT
NOP
NOP
ACT
NOP
NOP
RD/
WR
Row
Row
Col
Bank x
Bank y
Bank y
NOP
tRCD
tRRD
DON’T CARE
Figure 5
tRCD AND tRRD Definition
READs
READ bursts are initiated with a READ command, as shown in Figure 6.
The starting column and bank addresses are provided with the READ command and AUTO PRECHARGE is
either enabled or disabled for that burst access. If AUTO PRECHARGE is enabled, the row being accessed is precharged at the completion of the burst. For the generic READ commands used in the following illustrations, AUTO
PRECHARGE is disabled.
During READ bursts, the valid data-out element from the starting column address will be available following the
CAS latency after the READ command. Each subsequent data-out element will be valid nominally at the next positive or negative clock edge (i.e. at the next crossing of CLK and CLK#). Figure 7 shows general timing for each
posible CAS latency setting. DQS is driven by the DDR SDRAM along with output data. The initial LOW state on
DQS is known as the read preamble; the LOW state coincident with the last data-out element is known as the read
postamble.
Upon completion of a burst, assuming no other commands have been initiated, the DQs will go High-Z.
Data fom any READ burst may be concatenated with or truncated with data from a subsequent READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follow either the last element of a completed burst or the last desired data element of a longer burst which is being
truncated. The new READ command should be issued x cycles after the first READ command, where x equals the
number of desired data element pairs (pairs are required by the 2n prefetch architecture). This is shown in Figure
8. A READ command can be initiated on any clock cycle following a previous READ command. Non consecutive
READ data is shown for illustration in figure 9. Full-speed random read accesses within a page (or pages) can be
performed as shown in Figure 10.
Document : 1G5-0157
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VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
CLK#
CLK
CKE
HIGH
CS#
RAS#
CAS#
WE#
x4:A0-A9
x8:A0-A8
x16:A0-A7
CA
x4:A12
x8:A9,A12
x16:A8,A9,A12
EN AP
A10
DIS AP
BA0,1
BA
=DON’T CARE
CA = Column Address
BA = Bank Address
EN AP = Enable Autoprecharge
DIS AP = Disable Autoprecharge
Figure 6
READ COMMAND
Document : 1G5-0157
Rev.1
Page 22
VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
CLK#
CLK
COMMAND
READ
ADDRESS
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Bank a,
Col n
CL=2
DQS
DO
n
DQ
CLK#
CLK
COMMAND
READ
ADDRESS
NOP
NOP
Bank a,
Col n
CL=2.5
DQS
DQ
DO
n
DON’T CARE
UNDEFINED
DO n=Data Out from column n
Burst Length=4
3 subsequent elements of Data Out appear in the programmed order following DO n
Figure 7a
READ BURST - REQUIRED CAS LATENCIES
Document : 1G5-0157
Rev.1
Page 23
VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
CLK#
CLK
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
tAC
max
CL=1.5
DQS
DQ
tAC
min
CLK#
CLK
COMMAND
READ
ADDRESS
NOP
NOP
NOP
NOP
NOP
Bank a,
Col n
CL=3
DQS
DO
n
DQ
DON’T CARE
UNDEFINED
DO n=Data Out from column n
Burst Length=4
3 subsequent elements of Data Out appear in the programmed order following DO n
Figure 7b
READ BURST - OPTIONAL CAS LATENCIES
Document : 1G5-0157
Rev.1
Page 24
VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
CLK#
CLK
COMMAND
READ
ADDRESS
NOP
Bank,
Col n
READ
NOP
NOP
NOP
Bank,
Col b
CL=2
DQS
DO
b
DO
n
DQ
CLK#
CLK
COMMAND
READ
ADDRESS
NOP
READ
NOP
NOP
NOP
Bank,
Bank,
Col n
Col b
CL=2.5
DQS
DO
n
DQ
DO
b
DON’T CARE
UNDEFINED
Do n(or b)= Data Out from column n (or column b)
Burst Length= 4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first)
3 subsequent elements of Data Out appear in the programmed order following DO n
3 (or 7) subsequent elements of Data Out appear in the programmed order following DO b
Figure 8a
CONSECUTIVE READ BURSTS - REQUIRED CAS LATENCIES
Document : 1G5-0157
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VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
CLK#
CLK
COMMAND
READ
ADDRESS
NOP
READ
Bank,
Col n
NOP
NOP
NOP
Bank,
Col b
CL=1.5
DQS
DO
b
DO
n
DQ
CLK#
CLK
COMMAND
READ
ADDRESS
NOP
READ
NOP
NOP
NOP
Bank,
Col b
Bank,
Col n
CL=3
DQS
DO
n
DQ
DO
b
DON’T CARE
UNDEFINED
Do n(or b)= Data Out from column n (or column b)
Burst Length= 4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first)
3 subsequent elements of Data Out appear in the programmed order following DO n
3 (or 7) subsequent elements of Data Out appear in the programmed order following DO b
Figure 8b
CONSECUTIVE READ BURSTS - OPTIONAL CAS LATENCIES
Document : 1G5-0157
Rev.1
Page 26
VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
CLK#
CLK
COMMAND
READ
ADDRESS
NOP
NOP
READ
NOP
NOP
Bank,
Col b
Bank,
Col n
CL=2
DQS
DO
b
DO
n
DQ
CLK#
CLK
COMMAND
READ
ADDRESS
NOP
Bank,
Col n
NOP
READ
NOP
NOP
NOP
Bank,
Col b
CL=2.5
DQS
DO
n
DQ
DO
b
DON’T CARE
UNDEFINED
DO n(or b)=Data Out from column n (or column b)
Burst Length=4
3 Subsequent elements of Data Out appear in the programmed order following DO n(and following DO b)
Figure 9a
NON-CONSECUTIVE READ BURSTS-REQUIRED CAS LATENCIES
Document : 1G5-0157
Rev.1
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VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
CLK#
CLK
COMMAND
READ
ADDRESS
NOP
NOP
NOP
NOP
READ
Bank,
Col b
Bank,
Col n
CL=1.5
DQS
DO
b
DO
n
DQ
CLK#
CLK
COMMAND
READ
ADDRESS
NOP
Bank,
Col n
NOP
READ
NOP
NOP
NOP
Bank,
Col b
CL=3
DQS
DO
n
DQ
DO
b
DON’T CARE
UNDEFINED
DO n(or b)=Data Out from column n (or column b)
Burst Length=4
3 Subsequent elements of Data Out appear in the programmed order following DO n(and following DO b)
Figure 9b
NON-CONSECUTIVE READ BURSTS-OPTIONAL CAS LATENCIES
Document : 1G5-0157
Rev.1
Page 28
VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
CLK#
CLK
COMMAND
READ
ADDRESS
READ
READ
READ
Bank,
Col x
Bank,
Col b
Bank,
Col g
Bank,
Col n
NOP
NOP
CL=2
DQS
DO
n
DQ
DO
n’
DO
x
DO
b
DO
x’
DO
g
DO
b’
CLK#
CLK
COMMAND
ADDRESS
READ
READ
READ
NOP
Bank,
Col n
Bank,
Col x’
Bank,
Col b
Bank,
Col g
NOP
NOP
CL=2.5
DQS
DQ
DO
n
DO
n’
DO
x
DO
x’
DO
b
DO
b’
DON’T CARE
UNDEFINED
DO n, etc.= Data Out from column n, etc.
n’, etc.=odd or even complement of n, etc. (i.e. column address LSB inverted)
Burst Length=2,4 or 8 in cases shown
Reads are to active rows in any banks
Figure 10a
RANDOM READ ACCESSES - REQUIRED CAS LATENCIES
Document : 1G5-0157
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VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
CLK#
CLK
COMMAND
READ
ADDRESS
Bank,
Col n
READ
READ
READ
Bank,
Col x
Bank,
Col b
Bank,
Col g
NOP
CL=1.5
DQS
DO
n’
DO
n
DQ
DO
x’
DO
x
DO
b
DO
b’
CLK#
CLK
COMMAND
ADDRESS
READ
READ
READ
READ
Bank,
Col n
Bank,
Col x
Bank,
Col b
Bank,
Col g
NOP
NOP
CL=3
DQS
DO
n
DQ
DO
n’
DO
x
DO
x’
DO
b
DON’T CARE
UNDEFINED
DO n, etc.= Data Out from column n, etc.
n’, etc.=odd or even complement of n, etc. (i.e. column address LSB inverted)
Burst Length=2,4 or 8 in cases shown
Reads are to active rows in any banks
Figure 10b
RANDOM READ ACCESSES - OPTIONAL CAS LATENCIES
Document : 1G5-0157
Rev.1
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VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
Data from any READ burst may be truncated with a BURST TERMINATE command, as shown in Figure 11. The
BURST TERMINATE latency is equal to the read (CAS) latency, i.e. the BURST TERMINATE command should be
issued x cycles after the READ command, where x equals the number of desired data element pairs (pairs are
required by the 2n prefetch architecture).
Data from any READ burst must be completed or truncated before a subsequent WRITE command can be
issued. If truncation is necessary, the BURST TERMINATE command must be used, as shown in Figure 12. The
tDDS MIN case is shown; the tDDS MAX case has a longer bus idle time (tDDS MIN and tDDS MAX are defined in
the section on WRITEs).
A READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that
AUTO PRECHARGE was not activated). The PRECHARGE command should be issued x cycles after the READ
command, where x equals the number of desired data element paires (pairs are required by the 2n prefetch architecture). This is shown if Figure 13 for READ latencies of 2.2.5 and 3. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. Note that part of the row precharge time is
hidden during the access of the last data elements.
In the case of a READ being executed to completion. a PRECHARGE command issued at the optimum time
(asdescribed above) provides the same operation that would result from the same READ burst with AUTO PRECHARGE enabled. The disadvantage of the precharge command is that it requires that the command and address
buses be available at the appropriate time to issue the command. The advantage of the PRECHARGE command is
that it can be used to truncate bursts.
Document : 1G5-0157
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Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
CLK#
CLK
COMMAND
READ
ADDRESS
NOP
NOP
NOP
NOP
NOP
NOP
NOP
BST
Bank a,
Col n
CL=2
DQS
DO
n
DQ
CLK#
CLK
COMMAND
READ
ADDRESS
NOP
BST
Bank a,
Col n
CL=2.5
DQS
DO
n
DQ
DON’T CARE
UNDEFINED
DO n=Data Out from column n
Cases shown are bursts of 8 terminated after 4 data elements
3 subsequent elements of Data Out appear in the programmed order following DO n
Figure 11a
TERMINATING A READ BURST - REQUIRED CAS LATENCIES
Document : 1G5-0157
Rev.1
Page 32
VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
CLK#
CLK
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
tAC
max
CL=1.5
DQS
DQ
tAC
min
CLK#
CLK
COMMAND
READ
ADDRESS
NOP
NOP
NOP
NOP
NOP
Bank a,
Col n
CL=3
DQS
DO
n
DQ
DON’T CARE
UNDEFINED
DO n= Data Out from coulmn n
Burst Length=4
3 subsequent elements of Data Out appear in the programmed order following DO n
Figure 11b
TERMINATING A READ BURST - OPTIONAL CAS LATENCIES
Document : 1G5-0157
Rev.1
Page 33
VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
CLK#
CLK
COMMAND
READ
ADDRESS
BST
NOP
WRITE
NOP
NOP
WRITE
NOP
Bank,
Col b
Bank,
Col n
tDSS
min
CL=2
DQS
DO
n
DQ
D1
b
DO
n’
DM
CLK#
CLK
COMMAND
READ
ADDRESS
BST
NOP
NOP
Bank,
Col b
Bank,
Col n
tDSS
min
CL=2.5
DQS
DQ
DO
n
DO
n’
D1
b
DM
DON’T CARE
UNDEFINED
DO n(or b)=Data Out from column n (or column b)
Burst Length= 4 in the cases shown (applies for bursts of 8 as well; if burst length is 2,
the BST command shown can be NOP)
3 subsequent elements of Data Out appear in the programmed order following DO n (and following DO b)
Figure 12a
READ TO WRITE - REQUIRED CAS LATENCIES
Document : 1G5-0157
Rev.1
Page 34
VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
CLK#
CLK
COMMAND
READ
ADDRESS
BST
NOP
NOP
WRITE
Bank,
Col b
Bank,
Col n
tDSS
min
CL=1.5
DQS
DO
n
DQ
D1
b
DO
n’
DM
CLK#
CLK
COMMAND
READ
ADDRESS
BST
NOP
WRITE
NOP
NOP
Bank,
Col b
Bank,
Col n
tDSS
min
CL=3
DQS
DQ
DO
n
DO
n’
D1
b
DM
DON’T CARE
UNDEFINED
DO n(or b)=Data Out column n (or column b)
Burst Length= 4 in the cases shown (applies for bursts of 8 as well; if burst length is 2,
the BST command shown can be NOP)
3 subsequent elements of Data Out appear in the programmed order following DO n (and following DO b)
Figure 12b
READ TO WRITE -OPTIONAL CAS LATENCIES
Document : 1G5-0157
Rev.1
Page 35
VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
CLK#
CLK
COMMAND
READ
NOP
PRE
NOP
NOP
ACT
tRP
ADDRESS
Bank a,
Row
Bank
(a or all)
Bank a,
Col n
CL=2
DQS
DO
n
DQ
CLK#
CLK
COMMAND
READ
NOP
PRE
NOP
t
ADDRESS
NOP
RP
Bank a,
(a or all)
Bank a,
Col n
ACT
Bank a,
Row
CL=2.5
DQS
DQ
DO
n
DON’T CARE
UNDEFINED
DO n=Data Out from column n
Cases shown are either uninterrupted bursts of 4, or interrupted bursts of 8
3 subsequent elements of Data Out appear in the programmed order following DO n
Figure 13a
READ TO PRECHARGE - REQUIRED CAS LATENCIES
Document : 1G5-0157
Rev.1
Page 36
VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
CLK#
CLK
COMMAND
READ
NOP
PRE
NOP
NOP
ACT
tRP
ADDRESS
Bank a,
Row
Bank
(a or all)
Bank a,
Col n
CL=1.5
DQS
DO
n
DQ
CLK#
CLK
COMMAND
READ
NOP
PRE
NOP
NOP
ACT
tRP
ADDRESS
Bank
(a or all)
Bank a,
Col n
Bank a,
Row
CL=3
DQS
DO
n
DQ
DON’T CARE
UNDEFINED
DO n=Data Out from column n
Cases shown are either uninterrupted bursts of 4, or interrupted bursts of 8
3 subsequent elements of Data Out appear in the programmed order following DO n
Figure 13b
READ TO PRECHARGE - OPTIONAL CAS LATENCIES
Document : 1G5-0157
Rev.1
Page 37
VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
WRITEs
WRITE bursts are initiated with a WRITE command, as shown in figure 14.
The starting column and bank addresses are provided with the WRITE command, and AUTO PRECHARGE
is either enabled or disabled for that acess. If AUTOPRECHARGE is enabled, the row being accessed is precharged at the completion of the burst. For the generic WRITE commands used in the following illustrations,
AUTOPRECHARGE is disabled.
During WRITE bursts, the first valid data-in element will be registered on the first rising edge of DQS following the write command, and subsequent data elements will be registered on successive edges of DQS. The
LOW state on DQS between the WRITE command and the first rising edge is known as the write preamble; the
LOW state on DQS following the last data-in element is known as the write postamble. The time between the
WRITE command and the first corresponding rising edge of DQS (tDSS) is specified with a relatively wide range
(from 75% to 125% of 1 clock cycle), so most of the WRITE diagrams that follow are drawn for the two extreme
cases (i.e. tDSS MIN and tDSS MAX). Figures 15 and 16 show the two extremes of tDSS for a burst of 4. Upon
completion of a burst, assuming no other commands have been initiated, the DQs will remain High-Z and any
additional input data will be ignored.
Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE command. In
either case, a continuous flow of input data can be maintained. The new WRITE command can be issued on any
clock following the previous WRITE command. The first data element from the new burst is applied after either
the last element of a completed burst or the last desired data element of a longer burst which is being truncated.
The new WRITE command should be issued x cycles after the first WRITE command, where x equals the
number of desired data element pairs (pairs are required by the 2n prefetch architecture). Figures 17 and 18
show concatenated bursts of 4. An example of non-consecutive WRITEs is shown in Figure 19. Full-speed random write accesses within a page or pages can be performed as shown in Figures 20 and 21.
Data for any WRITE burst may be followed by a subsequent READ command. To follow a WRITE without
truncating the write burst, tWTR should be met as shown in Figures 22 and 23.
Data for any WRITE burst may be truncated by a subsequent READ command, as shown in Figures 24-27.
Note that only the data-in pairs that are registered prior to the tWTR period are written to the internal array, and
any subsequent data-in should be masked with DM(through one-half clock after the READ command).
Document : 1G5-0157
Rev.1
Page 38
VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
CLK#
CLK
CKE
HIGH
CS#
RAS#
CAS#
WE#
x4:A0-A11
x8:A0-A9
x16:A0-A8
CA
x4:A12
x8:A9,A12
x16:A8,A9,A12
EN AP
A10
DIS AP
BA0,1
BA
=DON’T CARE
CA = Column Address
BA = Bank Address
EN AP = Enable Autoprecharge
DIS AP = Disable Autoprecharge
Figure 14
WRITE COMMAND
Document : 1G5-0157
Rev.1
Page 39
VIS
Preliminary
T0
T1
T2
T3
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
T4
T5
T6
T7
CLK#
CLK
COMMAND
WRITE
ADDRESS
NOP
NOP
NOP
Bank a,
Col b
tDSS
max
DQS
DQ
Dl
b
DM
DON’T CARE
UNDEFINED
Dl b=Data In for column b
3 subsequent elements of Data In are applied in the programmed order following Dl b
A non-interrupted burst of 4 is shown
A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled)
Figure 15
WRITE BURST - MAX DSS
Document : 1G5-0157
Rev.1
Page 40
VIS
Preliminary
T0
T1
T2
T3
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
T4
T5
T6
CLK#
CLK
COMMAND
WRITE
ADDRESS
NOP
NOP
NOP
Bank a,
Col b
tDSS
min
DQS
DQ
Dl
b
DM
DON’T CARE
UNDEFINED
Dl b=Data In for column b
3 subsequent elements of Data In are applied in the programmed order following Dl b
A non-interrupted burst of 4 is shown
A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled)
Figure 16
WRITE BURST - MIN DSS
Document : 1G5-0157
Rev.1
Page 41
VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
Data for any WRITE burst may be followed by a subsequent PRECHARGE command. To follow a WRITE with
out truncating the write burst, tWR should be met as shown in Figures 28 and 29.
Data for any WRITE burst may be truncated by a subsequent PRECHARGE command, as shown in Figures
30-33. Note that only the data -in pairs that are registered prior to the tWR period are written to the internal array,
and any subsequent data-in should be masked with DM (through one-half clock after the READ command). Following the PRECHARGE command, a subsequent command to the same bank can not be issued until tRP is
met.
In the case of a write burst being executed to completion, a PRECHARGE command issued at the optimum
time (as described above) provides the same operation that would result from the same burst with AUTO PRECHARGE. The disadvantage of the PRECHARGE command is that it requires that the command and address
buses be available at the appropriate time to issue the command. The advantage of the PRECHARGE command
is that it can be used to truncate bursts.
Document : 1G5-0157
Rev.1
Page 42
VIS
Preliminary
T0
T1
T2
T3
T4
T5
T6
T7
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
T8
T9
T10
T11
CLK#
CLK
COMMAND
WRITE
ADDRESS
NOP
WRITE
NOP
NOP
NOP
Bank,
Col n
Bank,
Col b
tDSS
max
DQS
DQ
Dl
n
Dl
b
DM
DON’T CARE
UNDEFINED
Dl b, etc. = Data In for column b, etc.
3 subsequent elements of Data In are applied in the programmed order following Dl b
3 subsequent elements of Data In are applied in the programmed order following Dl n
A non-interrupted burst of 4 is shown
Each Write command may be to any bank
Figure 17
WRITE TO WRITE - MAX DSS
Document : 1G5-0157
Rev.1
Page 43
VIS
Preliminary
T0
T1
T2
T3
T4
T5
T6
T7
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
T8
T9
T10
T11
CLK#
CLK
COMMAND
WRITE
ADDRESS
NOP
WRITE
NOP
NOP
NOP
Bank,
Col n
Bank,
Col b
tDSS
min
DQS
DQ
Dl
b
Dl
n
DM
DON’T CARE
UNDEFINED
Dl b, etc. = Data In for column b, etc.
3 subsequent elements of Data In are applied in the programmed order following Dl b
3 subsequent elements of Data In are applied in the programmed order following Dl n
A non-interrupted burst of 4 is shown
Each Write command may be to any bank
Figure 18
WRITE TO WRITE - MIN DSS
Document : 1G5-0157
Rev.1
Page 44
VIS
Preliminary
T0
T1
T3
T2
T4
T5
T6
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
T7
T9
T8
T10
CLK#
CLK
COMMAND
WRITE
ADDRESS
NOP
NOP
Bank,
Col b
WRITE
NOP
Bank,
Col n
tDSS
max
DQS
DQ
Dl
n
Dl
b
DM
DON’T CARE
UNDEFINED
Dl b, etc. = Data In for column b, etc.
3 subsequent elements of Data In are applied in the programmed order following Dl b
3 subsequent elements of Data In are applied in the programmed order following Dl n
A non-iterrupted burst of 4 is shown
Each Write command may be to any bank
Figure 19
WRITE TO WRITE - MAX DSS, NON-CONSECUTIVE
Document : 1G5-0157
Rev.1
Page 45
VIS
Preliminary
T0
T1
T3
T2
T4
T5
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
T6
T7
T9
T8
CLK#
CLK
COMMAND
WRITE
ADDRESS
Bank,
Col b
WRITE
WRITE
WRITE
WRITE
Bank,
Col x
Bank,
Col n
Bank,
Col a
Bank,
Col g
tDSS
max
DQS
DQ
Dl
b
Dl
b’
Dl
x
Dl
x’
Dl
n
Dl
n’
Dl
a
Dl
a’
DM
DON’T CARE
UNDEFINED
Dl b, etc.=Data In for coulmn b, etc.
b’,etc.=odd or even complement of b, etc.(i.e. column address LSB inverted)
Programmed burst Length=2,4 or 8 in cases shown
Each Write command may be to any bank.
Figure 20
RANDOM WRITE CYCLES - MAX DSS
Document : 1G5-0157
Rev.1
Page 46
VIS
Preliminary
T0
T1
T3
T2
T4
T5
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
T6
T7
T8
CLK#
CLK
COMMAND
WRITE
ADDRESS
Bank,
Col b
WRITE
WRITE
WRITE
WRITE
Bank,
Col x
Bank,
Col n
Bank,
Col a
Bank,
Col g
tDSS
min
DQS
DQ
Dl
b
Dl
b’
Dl
x
Dl
x’
Dl
n
Dl
n’
Dl
a
Dl
a’
DM
DON’T CARE
UNDEFINED
Dl b, etc.=Data In for coulmn b, etc.
b’,etc.=odd or even complement of b, etc.(i.e. column address LSB inverted)
Programmed burst Length=2,4 or 8 in cases shown
Each Write command may be to any bank.
Figure 21
RANDOM WRITE CYCLES - MIN DSS
Document : 1G5-0157
Rev.1
Page 47
VIS
Preliminary
T0
T1
T2
T3
T4
T5
T6
T7
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
T8
T10
T9
T11
CLK#
CLK
COMMAND
WRITE
NOP
NOP
NOP
READ
NOP
tWTR
ADDRESS
Bank,
Col n
Bank,
Col b
tDSS
CL
max
DQS
DQ
Dl
b
DM
DON’T CARE
UNDEFINED
Dl b=Data In for column b
3 subsequent elements of Data In are applied in the programmed order following Dl b
A non-interrupted burst of 4 is shown
tWTR is referenced from the first positive CLK edge after the last Data In pair
A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled)
The READ and WRITE commands are not necessarily to the same bank
Figure 22
WRITE TO READ - MAX DSS, NON-INTERRUPTING
Document : 1G5-0157
Rev.1
Page 48
VIS
Preliminary
T0
T1
T2
T3
T4
T5
T6
T7
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
T8
T10
T9
T11
CLK#
CLK
COMMAND
WRITE
NOP
NOP
NOP
READ
NOP
tWTR
ADDRESS
Bank,
Col n
Bank,
Col b
tDSS
CL
min
DQS
DQ
Dl
b
DM
DON’T CARE
UNDEFINED
Dl b=Data In for column b
3 subsequent elements of Data In are applied in the programmed order following Dl b
A non-interrupted burst of 4 is shown
tWTR is referenced from the first positive CLK edge after the last Data In pair
A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled)
The READ and WRITE commands are not necessarily to the same bank
Figure 23
WRITE TO READ - MIN DSS, NON-INTERRUPTING
Document : 1G5-0157
Rev.1
Page 49
VIS
Preliminary
T0
T1
T2
T3
T4
T5
T6
T7
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
T8
T10
T9
T11
CLK#
CLK
COMMAND
WRITE
NOP
NOP
NOP
READ
NOP
tWTR
ADDRESS
Bank,
Col n
Bank,
Col b
tDSS
CL
max
DQS
DQ
Dl
b
DM
DON’T CARE
UNDEFINED
Dl b=Data In for column b
An interrupted burst of 8 is shown, 4 data elements are written
3 subsequent elements of Data In are applied in the programmed order following Dl b
tWTR is referenced from the first positive CLK edge after the last Data In pair
A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled)
The READ and WRITE commands are not necessarily to the same bank
Figure 24
WRITE TO READ - MAX DSS, INTERRUPTING
Document : 1G5-0157
Rev.1
Page 50
VIS
Preliminary
T0
T1
T2
T3
T4
T5
T6
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
T7
T8
T10
T9
T11
CLK#
CLK
COMMAND
WRITE
NOP
NOP
NOP
READ
NOP
tWTR
ADDRESS
Bank,
Col n
Bank,
Col b
tDSS
CL
min
DQS
DQ
Dl
b
DM
DON’T CARE
UNDEFINED
Dl b=Data In for column b
An interrupted burst of 8 is shown, 4 data elements are written
3 subsequent elements of Data In are applied in the programmed order following Dl b
tWTR is referenced from the first positive CLK edge after the last desired Data In pair
A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled)
The READ and WRITE commands are not necessarily to the same bank
Figure 25
WRITE TO READ - MIN DSS, INTERRUPTING
Document : 1G5-0157
Rev.1
Page 51
VIS
Preliminary
T0
T1
T2
T3
T4
T5
T6
T7
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
T8
T10
T9
T11
CLK#
CLK
COMMAND
WRITE
NOP
NOP
NOP
READ
NOP
tWTR
ADDRESS
Bank,
Col n
Bank,
Col b
tDSS
CL
min
DQS
DQ
Dl
b
DM
DON’T CARE
UNDEFINED
Dl b= Data In for column b
An interrupted burst of 8 is shown, 3 data elements are written
2 subsequent elements of Data In are applied in the programmed order following Dl b
tWTR is referenced from the first positive CLK edge after the last desired Data in pair (not the last desired
data in element)
A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled)
The READ and WRITE commands are not necessarily to the same bank
Figure 26
WRITE TO READ - MIN DSS, ODD NUMBER OF DATA, INTERRUPTING
Document : 1G5-0157
Rev.1
Page 52
VIS
Preliminary
T0
T1
T2
T3
T4
T5
T6
T7
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
T8
T10
T9
T11
CLK#
CLK
COMMAND
WRITE
NOP
NOP
NOP
READ
NOP
tWTR
ADDRESS
Bank,
Col n
Bank,
Col b
tDSS
CL
nom
DQS
DQ
Dl
b
DM
DON’T CARE
UNDEFINED
Dl b= Data In for column b
An interrupted burst of 8 is shown, 4 data elements are written
3 subsequent elements of Data In are applied in the programmed order following Dl b
tWTR is referenced from the first positive CLK edge after the last desired Data In pair
A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled)
The READ and WRITE commands are not necessarily to the same bank
Figure 27
WRITE TO READ - NOMINAL DSS, INTERRUPTING
Document : 1G5-0157
Rev.1
Page 53
VIS
Preliminary
T0
T1
T2
T3
T4
T5
T6
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
T7
T8
T9
T10
T11
CLK#
CLK
COMMAND
WRITE
NOP
NOP
NOP
NOP
PRE
tWR
ADDRESS
Bank,
(a or all)
Bank a,
Col b
tDSS
tRP
max
DQS
DQ
Dl
b
DM
DON’T CARE
UNDEFINED
Dl b=Data In for column b
3 subsequent elements of Data In are applied in the programmed order following Dl b
A non-interrupted burst of 4 is shown
tWTR is referenced from the first positive CLK edge after the last Data In pair
A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled)
Figure 28
WRITE TO PRECHARGE - MAX DSS, NON-INTERRUPTING
Document : 1G5-0157
Rev.1
Page 54
VIS
Preliminary
T0
T1
T2
T3
T4
T5
T6
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
T7
T8
T9
T10
T11
CLK#
CLK
COMMAND
WRITE
NOP
NOP
NOP
NOP
PRE
tWR
ADDRESS
Bank,
(a or all)
Bank a,
Col b
tDSS
tRP
min
DQS
DQ
Dl
b
DM
DON’T CARE
UNDEFINED
Dl b=Data In for column b
3 subsequent elements of Data In are applied in the programmed order following Dl b
A non-interrupted burst of 4 is shown
tWR is referenced from the first positive CLK edge after the last Data In pair
A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled)
Figure 29
WRITE TO PRECHARGE - MIN DSS, NON-INTERRUPTING
Document : 1G5-0157
Rev.1
Page 55
VIS
Preliminary
T0
T1
T2
T3
T4
T5
T6
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
T7
T8
T10
T9
T11
CLK#
CLK
COMMAND
WRITE
NOP
NOP
PRE
NOP
NOP
tWR
ADDRESS
Bank,
(a or all)
Bank a,
Col b
tDSS
tRP
max
*2
DQS
DQ
Dl
b
DM
*1
*1
DON’T CARE
UNDEFINED
Dl b =Data In for column b
An interrupted burst of 4 or 8 is shown, 2 data elements are written
1 subsequent element of Data In is applied in the programmed order following Dl b
tWR is referenced from the first positive CLK edge after the last desired Data In pair
A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled)
*1=can be don’t care for programmed burst length of 4
*2=for programmed burst length of 4, DQS becomes don’t care at this point
Figure 30
WRITE TO PRECHARGE - MAX DSS, INTERRUPTING
Document : 1G5-0157
Rev.1
Page 56
VIS
Preliminary
T0
T1
T2
T3
T4
T5
T6
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
T7
T8
T9
T10
T11
CLK#
CLK
COMMAND
WRITE
NOP
NOP
PRE
NOP
NOP
tWR
ADDRESS
Bank,
(a or all)
Bank a,
Col b
tDSS
min
tRP
*2
DQS
DQ
Dl
b
DM
*1
*1
*1
DON’T CARE
UNDEFINED
Dl b=Data In for column b
An interrupted burst of 4 or 8 is shown, 2 data elements are written
1 subsequent element of Data In is applied in the programmed order following Dl b
tWR is referenced from the first positive CLK edge after the last desired Data In pair
A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled)
*1=can be don’t care for programmed burst length of 4
*2=for programmed burst length of 4, DQS becomes don’t care at this point
Figure 31
WRITE TO PRECHARGE - MIN DSS, INTERRUPTING
Document : 1G5-0157
Rev.1
Page 57
VIS
Preliminary
T0
T1
T2
T3
T4
T5
T6
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
T7
T9
T8
T10
T11
CLK#
CLK
COMMAND
WRITE
NOP
NOP
PRE
NOP
NOP
tWR
ADDRESS
Bank,
(a or all)
Bank a,
Col b
tDSS
min
tRP
*2
DQS
DQ
Dl
b
DM
*1
*1
*1
DON’T CARE
UNDEFINED
Dl b=Data In for column b
An interrupted burst of 4 or 8 is shown, 1 data elements are written
tWR is referenced from the first positive CLK edge after the last desired Data In pair
A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled)
*1=can be don’t care for programmed burst length of 4
*2=for programmed burst length of 4, DQS becomes don’t care at this point
Figure 32
WRITE TO PRECHARGE - MIN DSS, ODD NUMBER OF DATA, INTERRUPTING
Document : 1G5-0157
Rev.1
Page 58
VIS
Preliminary
T0
T1
T2
T3
T4
T5
T6
T7
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
T8
T10
T9
T11
CLK#
CLK
COMMAND
WRITE
NOP
NOP
NOP
PRE
NOP
tWR
ADDRESS
Bank,
(a or all)
Bank a,
Col b
tDSS
tRP
*2
nom
DQS
DQ
Dl
b
DM
*1
*1
*1
DON’T CARE
UNDEFINED
Dl b=Data In for column b
An interrupted burst of 4 or 8 is shown, 2 data elements are written
1 subsequent element of Data In is applied in the programmed order following Dl b
tWR is referenced from the first positive CLK edge after the last desired Data In pair
A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled)
*1=can be don’t care for programmed burst length of 4
*2=for programmed burst length of 4, DQS becomes don’t care at this point
Figure 33
WRITE TO PRECHARGE - NOMINAL DSS, INTERRUPTING
Document : 1G5-0157
Rev.1
Page 59
VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
CLK#
CLK
CKE
HIGH
CS#
RAS#
CAS#
WE#
A0-A9,A11,A12
ALL BANKS
A10
ONE BANK
BA0,1
BA
=DON’T CARE
BA=Bank Address (if A10 LOW, otherwise don’t care’)
Figure 34
PRECHARGE COMMAND
Document : 1G5-0157
Rev.1
Page 60
VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or the open
row in all banks. The bank(s) will be available for a subsequent row access some specified time (tRP)
after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be
precharged, and in the case where only one bank is to be prcharged, inputs BA0,BA1 select the bank.
When all banks are to be precharged, inputs BA0,BA1 are treated as “Don’t Care.” Once a bank has
been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands
being issued to that bank.
POWER-DOWN
Power-down is entered when CKE is registered LOW (no accesses can be in progress). If powerdown occurs when all banks are idle, this mode is referred to as precharge power down; if powerdown occurs when there is a row active in either bank, this mode is referred to as active power-down.
Entering power-down deactivates the input and output buffers, excluding CLK, CLK# and CKE. For
maximum power savings, the user has the option of disabling the DLL prior to entering Power-down.
In that case, the DLL must be enabled after exiting power-down, and 200 clock cycles must occur
before a READ command can be issued. In either case, CKE LOW and a stable clock signal should
be maintained at the inputs of the DDR SDRAM, and all other input signals are “Don’t Care”. The
device may not remain in the power-down state loger than the refresh period (64ms) since no refersh
operations are performed in this mode.
The power-down state is exited when CKE is registered HIGH, and a command may be
applied be applied one clock cycle later.
CLK#
CLK
tIS
tIS
CLK#
CLK
COMMAND
VALID
No column
access
in progress
NOP
VALID
Exit power-down
mode
Enter power-down
mode
DON’T CARE
Figure 35
POWER-DOWN
Document : 1G5-0157
Rev.1
Page 61
VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
TRUTH TABLE 2-CKE
(Notes: 1-4)
CKEn-1
CKE n
CURRENT STATE
COMANDn
ACTIONn
L
L
Power-Down
X
Maintain Power-Down
Self Refresh
X
Maintain Self Refresh
Power-Down
COMMAND INHIBIT or NOP
Exit Power-Down
5
Self Refresh
COMMAND INHIBIT or NOP
Exit Self Refresh
6
All Banks Idle
COMMAND INHIBIT or NOP
Precharge Power-Down Entry
Bank(s) Active
COMMAND INHIBIT or NOP
Active Power-Down Entry
All Banks Idle
AUTO REFERESH
Self Refresh Entry
L
H
H
H
L
H
NOTES
See Truth Table 3
NOTE: 1. CKEn is the logic state of CKE at clock edge n, CKE n-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n, and ACTIONn is result of COMMANDn4. All states and sequences not shown are illegal or reserved.
5.Exiting power-down at clock edge n will put the device in the “all banks idle” state in time for clock edge n+1
6. Exiting self refreshh at clock edge n will put the device in the “all banks idle” state once tXSR is met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring during the X
‘ SR period. A
minimum of two NOP commands must be provided during tXSR period. A minimum of 200 clock cycles is
needed before applying a read command, for the DLL to lock.
Document : 1G5-0157
Rev.1
Page 62
VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
TRUTH TABLE 3-Current State Bank n - Command to Bank n
(Notes: 1-6; notes appear below and on next page)
CURRENT STATE
CS#
RAS#
CAS#
WE#
COMMANDACTION
Any
H
X
X
X
COMMAND INHBIT (NOP/continue previous operation
L
H
H
H
NO OPERATION (NOP/continue previous operation)
L
L
H
H
ACTIVE (select and activate row)
L
L
L
H
AUTO REFRESH
7
L
L
L
L
LOAD MODE REGISTER
7
L
H
L
H
READ (select column and start READ burst)
10
L
H
L
L
WRITE (select column and start WRITE burst)
10
L
L
H
L
PRECHARGE (deactivate row in bank or banks)
8
L
H
L
H
READ (select column and start new READ burst)
10
L
H
L
L
WRITE (select column and start WRITE burst)
10
L
L
H
L
PRECHARGE(truncate READ burst, start PRECHARGE)
8
L
H
H
L
BURST TERMINATE
9
L
H
L
H
READ (select column and start READ burst)
10
L
H
L
L
WRITE (select column and start new WRITE burst)
10
L
L
H
L
PRECHARGE (truncate WRITE burst, start PRECHARGE)
8
Idle
Row Active
Read
(AutoPrecharge
Disabled)
Write
(AutoPrecharge
Disabled)
NOTES
NOTE:
1. This table applies when CKEn-1 was HIGH and CKEn Is HIGH (see Turn Table 2) and after tXSR has
been met (if the previous state was self refresh).
2. This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the
commands shown are those allowed to be issued to that bank when in that state, Exceptions are
covered in the notes below.
3.Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/
accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated.
Write: A WRITE burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated.
Document : 1G5-0157
Rev.1
Page 63
VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
4. The following states must not be interrupted by a command issued to the same bank, COMMAND
INHIBIT or NOP commands, or allowable commands to the other bank should be issued on any clock
edge occurring during these states. Allowable commands to the other bank are determined by its current state and Truth Table3, and according to Truth Table 4.
Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once
t
RP is met, the bank will be in the idle state.
Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once
tRCD
is met, the bank will be in the “row active” state.
Read w/AutoPrecharge Enabled: Starts with registration of
a READ command with AUTO PRECHARGE
enabled and ends when tRP has been met. Once tRP is met, the bank will be
in the idle state.
Write w/AutoPrecharge Enabled: Starts with registration of a WRITE command with AUTO PRECHARGE
enabled and ends when tRP has been met. Once tRP is met, the bank will be
in the idle state.
Write w/Auto
Precharge Enabled: Starts with registrayion of a WRITE command with AUTO PRECHARGE
enabled and ends when tRP has been met. Once tRP is met, the bank will be
in the idle state.
5.The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP
commands must be applied on each positive clock edge during these states.
Refreshing: Starts with registration of an AUTO REFERESH command and ends when tRC is met.
Once tRC is met, the DDR SDRAM will be in the “all banks idle” state.
Accessing Mode
Register: Starts with registration of a LOAD MODE REGISTER command and ends when tMTC has
been met. Once tMTC is met, the DDR SDRAM will be in the “all banks idle” state.
Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is
met. Once tRP is met, all banks will be in the idle state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; reguired that all banks are idle.
8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging.
9. Not bank-specific; BURST TERMINATE affects the most recent READ burst, regardless of bank.
10. READs or WRITEs listed in the Command/Action column include READs or WRITEs with AUTO
PRECHARGE enabled and READs or WRITEs with AUTO PRECHARGE disabled.
Document : 1G5-0157
Rev.1
Page 64
VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
TRUTH TABLE 4-Current State Bank n - Command to Bank m
(Notes: 1-6; notes appear below and on next page)
CURRENT STATE
CS#
RAS#
CAS#
WE#
COMMANDACTION
Any
H
X
X
X
COMMAND INHBIT (NOP/continue previous operation
L
H
H
H
NO OPERATION (NOP/continue previous operation)
Idle
X
X
X
X
Any Command Otherwiswe Allowed to Bank m
Read
Activating,
Active, or
Precharging
L
L
H
H
ACTIVE (select andactivate row)
L
H
L
H
READ (select column and start READ burst)
7
L
H
L
L
WRITE(select column and start WRITE burst)
7
L
L
H
L
PRECHARGE
L
L
H
H
ACTIVE (select and activate row)
L
H
L
H
READ (select column and start new READ burst)
7
L
H
L
L
WRITE (select column and start WRITE burst)
7
L
L
H
L
PRECHARGE
L
L
H
H
ACTIVE (select and activate row)
L
H
L
H
READ (select column and start READ burst)
7
L
H
L
L
WRITE (select column and start new WRITE burst)
7
L
L
H
L
PRECHARGE
L
L
H
H
ACTIVE (select and activate row)
L
H
L
H
READ (select column and start new READ burst)
7
L
H
L
L
WRITE (select column and start WRITE burst)
7
L
L
H
L
PRECHARGE
L
L
H
H
ACTIVE (select and activate row)
L
H
L
H
READ (select column and start READ burst)
7
L
H
L
L
WRITE (select column and start new WRITE burst)
7
L
L
H
L
PRECHARGE
Read
(AutoPrecharge
Disabled)
Write
(AutoPrecharge
Disabled)
Read
(With AutoPrecharge)
Write
(With AutoPrecharge)
NOTES
NOTE:
1. This table applies when CKEn-1 was HIGH and CKEn Is HIGH (see Truth Table 2) and after tXSR has
been met (if the previous state was self refresh).
2. This table describes alternate bank operation, except where noted, i.e., the current state is for bank n
and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such
a state that the given command is allowable). Exceptions are covered in the notes below.
Document : 1G5-0157
Rev.1
Page 65
VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses
and no register accesses are in progress.
Read: A READ burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated.
Write: A WRITE burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated.
Read with Auto
Precharge Enabled: See following text
Write with Auto
Precharge Enabled: See following text
The Read with Auto Precharge Enabled or Write with Auto Precharge Enabled states can each be
broken into two parts: the access period and the precharge period. The precharge period is defined
as if the same burst was executed with Auto Precharge disabled and then followed with the earliest
possible PRECHARGE command that still accesses all of the data in the burst. The access period
starts with registration of the command and ends where the precharge period (or tRP) begins.
During the precharge period of the Read with Auto Precharge Enabled or Write with Auto Precharge
Enabled states, ACTIVE, PRECHARGE, READ and WRITE commands to the other bank may be
applied; during the access period, only ACTIVE and PRECHARGE commands to the other bank may
be applied. In either case, all other related limitations apply (e.g. following a Read with Auto Precharge by a Write command to another bank is subject to the same data path limitations as when following a Read by a Write).
4. AUTO REFERESH, LOAD MODE REGISTER and PRECHARGE ALL commands may only be issued
when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented
by the current state only.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with AUTO PRECHARGE enabled and READs or WRITEs with AUTO PRECHARGE disabled.
Document : 1G5-0157
Rev.1
Page 66
VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
Simplified state Diagram
Power
Applied
POWER
ON
SELF
REFRESH
REFS
REFSX
MRS
MRS
EMRS
AUTO
REFRESH
REFA
IDLE
CKEL
CKEH
POWER
DOWN
POWER
DOWN
ACT
CKEH
CKEL
ROW
ACTIVE
BURST STOP
Read
Write
Read
Write
WRITE
Read
READ
Write
Read A
Write A
Read
A
Write
A
WRITE A
PRE
PRE
PRE
PRE
READ A
Precharge
PREALL
Automatic Sequence
Command Sequence
Document : 1G5-0157
Rev.1
Page 67
VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
Absolute Maximum ratings
Paramefer
Sysbol
Value
Unit
VDD
-1.0 + 4.6
V
VDDQ
-1.0 + 3.6
V
Voltage on input pin relative to Vss
VIN
-1.0 + 3.6
V
Voltage on I/O pin relative to Vss
VI/O
-0.5 to VDDQ+0.5
V
VOUT
50
mA
PD
1.0
W
Operating temperature (ambient)
T OPT
0 to + 70
°C
Storage temperature (plastic)
PRE
-55 to + 125
°C
Supply voltage relative to Vss (With VDD 3.3V)
Voltage on VDDQ relative to Vss
Short circuit output current
Power dissipation
Recommended DC Operating Conditions
Max
Unit
3.3
3.6
V
2.3
2.5
2.7
V
VREF
1.15
1.25
1.35
V
6
VTT
VREF0.04
VREF
VREF+0.04
V
7
Input high Voltage, all inputs
VIH(DC)
VREF
+0.18
-
VDD+0.3
V
Input Low voltage, all inputs
VIL(DC)
-0.3
-
VREF-0.18
V
Input Voltage Level. CLK and CLK#
inputs
VIN(DC)
-0.3
-
VDDQ+0.3
V
Input Differential Voltage, CLK and CLK#
inputs
VID(DC)
0.36
-
VDD+0.6
V
8
Input Crossing Point Voltage, CLK and
CLK# inputs
VIX(DC)
1.15
-
1.35
V
9
II
-5
-
5
uA
Output Leakage Current
(DQs are disbled; ) 0V ≥ VOUT ≤ VDDQ
IOZ
-5
-
5
uA
Output Levels
Output High Current (V out=1.95V)
Output Low current (Vout=0.35V)
IOH
IOL
-15.2
-
15.2
mA
Parameter
Symbol
Min
VDD
3.0
I/O Supply Voltage
VDDQ
I/O Reference Voltage
Supply voltage (with VDD 3.3V)
I/O Termination Voltage (system)
Input Leakage Current
Any input 0V ≥ VIN ≤ VDD
(All other pins not under test=0V)
Document : 1G5-0157
Rev.1
Typ
Notes
Page 68
VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
Capacitance
(Ta=25°C, f=1MHZ)
Parameter
Symbol
Typ
Max
Unit
NOTES
Input capacitance: CLK, CLK#
C11
2.5
3.5
pF
13
Input capacitance (all input pins except data pins)
C12
2.5
3.5
pF
13
Data input/output capacitance: DQs, DQS, DM
CI/O
4.0
5.5
pF
13
Recommended Electrical Characteristic and D.C. Operating Conditions (VDDQ=+2.5 ± 0.2V ,VDD=3.3V, Ta=0-70°C
Max
Description/test condition
Symbol
Operating Current: Active Mode
-75
Unit
Notes
-8
ICC1
≥ t RC ( MIN ) , Burst=4, READ or Write
R
CL=2.5, tCK=7ns for -8
t
Precharge Standby Current: Power-down mode, All banks idle
CKE ≥ VIL ( MAX )
CL=2.5, tCK=7ns for -8
Precharge Standby Current: CS ≥ V
IH
(MIN), All banks idle
ICC2P
20
ICC2N
30
mA
CKE ≥ VIL ( MIN )
CL=2.5, tCK=7ns for -8
Active Standby Current: CS ≥ V
IH
(MIN), All banks active after tRAS
ICC3
met, no access in progress
CKE ≤ VIL ( MIN )
CL=2.5, tCK=7ns for -8
Operating Current:
Burst=4, Continue burst
ICC4
180
ICC5
210
ICC6
2
CKE ≤ CIL ( MAX ) READ or WRITE, All banks active, address
transition once per clock cycle;
CL=2.5, tCK=7ns for-8
Auto refresh Current:
t
RC
≥t
RC ( MIN )
Self Refresh Current: CKE ≤ 0.2V
Document : 1G5-0157
Rev.1
11
Page 69
VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
AC OPERATIONS AND CONDITIONS:
Description
Parameter
Min.
Max.
Unit
Input High Voltage: DQ, DQS and DM signals
VIH(AC)
VREF+0.35
TBD
V
Input Low Voltage: DQ, DQS and DM signals
VIL(AC)
TBD
VREF-0.35
V
Input Differential Voltage, CLK and CLK# inputs
VID(AC)
0.7
VDDQ+0.6
V
8
Input Crossing Point Voltage, CLK and CLK# inputs
VIX(AC)
1.15
1.35
V
9
Document : 1G5-0157
Rev.1
NOTES
Page 70
VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
A.C Characteristics:
Test Conditions: (Ta=0 to 70°C V DDQ=2.5V
± 0.2V , VDD=3.3V ± 0.3V , or VDD=2.5V ± 0.2V
A.C. Parameter
Symbol
-75
-8
Unit
Min.
Max.
Min.
Max.
tCK
Note
Access time from CLK/CLK#
tAC
-0.1
+0.1
-0.1
+0.1
tCK
Clock high time
tCH
0.45
0.55
0.45
0.55
tCK
Clock low time
tCL
0.45
0.55
0.45
0.55
ns
CL=3
tCK3Q
5
15
6
15
ns
CL=2.5
tCK2.5
6.2
15
7
15
ns
CL=2
tCK2
7.5
15
8
15
ns
CL=1.5
tCK15
10
15
10
15
tCK
Data-in hold time
tDH
0.075
0.075
tCK
Data-in setup time
tDS
0.075
0.075
tCK
18
Data-out high imedance from CLK/CLK#
tHZ
-0.1
+0.1
-0.1
+0.1
tCK
18
Data-out low impedance from CLK/CLK#
tLZ
-0.1
+0.1
-0.1
+0.1
tCK
tDSDQ
-0.075
+0.075
-0.075
+0.075
tCK
DQ/DQS output valid time
tDV
0.35
Write command to first DQS latching transition
tDSS
0.75
1.25
0.75
1.25
tCK
DQ/DQS input valid time
tDSLH
0.40
0.60
0.40
0.60
tCK
LOAD MODE REGISTER COMMAND cycle time
tMRD
2
2
tCK
22
Write preamble setup time
tWPR
0
0
ns
19
Write postamble
tWPO
0.4
tCK
20
Write command to DQS Low-Z
tWCP
0
0
ns
Input hold time
tIH
0.15
0.15
tCK
Input setup time
tIS
0.15
0.15
tCK
Read preamble
tRPR
0.9
1.1
0.9
1.1
tCK
Read postamble
tRPO
0.4
0.6
0.4
0.6
tCK
ACTIVE to PRECHARGE command
tRAS
45
120,000
48
120,000
ns
AUTO REFRESH, ACTIVE command period
tRC
65
70
ns
ACTIVE to READ or WRITE delay
tRCD
20
20
ns
Refresh period (8192 rows)
tREF
PRECHARGE command period
tRP
20
20
ns
tRRD
15
20
ns
Clock cycle time
DQS-DQ Skew
ACTIVE bank A to Active bank B command
Transition time
0.35
0.6
0.4
64
tCK
0.6
64
tT
ms
ns
Write recovery time
tWR
2
2
tCK
Write data In to Read Command Delay
tWTR
1
1
tCK
Exit SELF REFRESH to ACTIVE command
tXSR
60
70
ns
Document : 1G5-0157
Rev.1
Page 71
21
VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
NOTES
1. All voltages referenced to Vss.
2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full
voltage range specified.
3. Outputs measured with equivalent load:
VTT
Output 25Ω
(VOUT)
25Ω
(Test point)
30pF
4.AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is
still referenced to VREF (or to the crossing point for CLK/CLK#), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC).
5.The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the
signal does not ring back above (below) the DC input LOW(HIGH) level.
6.VREF is expected to track variations in the DC level of V DDQ of the transmitting device. peak-to-peak noise
on VREF may not exceed +/-2% of the DC value.
7.VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected
to be set equal to VREF and must track variations in the DC level of V REF.
8.VID is the magnitude of the difference between the input level on CLK and the input level on CLK#.
9.The value of VIX is expected to equal VREF and must track variations in the DC level of V REF.
10.IDD is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle time and the outputs open.
11.Enables on chip refresh and address counters.
12.IDD specifications are tested after the device is properly initialized.
13.This parameter is sampled. VDDQ+2.5V
± 0.2V , VDD=+3.3V ± 3.3V
, f=1MHz, tA=25°C
14.Input slew rate=1V/ns+/-20%.
15.The CLK/CLK# input reference level (for timeing referenced to CLK/CLK#) is the point at which CLK and
CLK# cross; the input reference level for signals other than CLK/CLK#, is VREF.
16.Inputs are not recognized as valid until VREF stabilizes. Exceptions: during the period before VREF stabi
lizes, CKE=<0.3VDDQ is recognized as LOW.
17.The output timing reference level, as measured at the test point indicated in Note 3, is VTT.
18.tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving
(HZ), or begins driving (LZ).
19.The maximum limit for this parameter is not a device limit. The device will operate with a greater value for
this parameter, but system performance (bus turnaround) will degrade accordingly.
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Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
20.The minimum limit for this parameter is not a device limit. The device will operate with a negative value for
this parameter, but system performance (bus turnaround) will degrade accordingly.
21.CLK must be toggled a minimum of two times during this period.
22.The specific reguirement is that DQS be valid (HIGH or LOW) on or befor this CLK edge. The case shown
(DQS going from High-Z to logic LOW) applies when no writes were previously in progress on the bus. If
a previous write was in progress. DQS could be HIGH at this time depending on tDSS.
Document : 1G5-0157
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VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
DATA INPUT TIMING
tDSL
tDSH
DQS
tDS
tDS
DQ
Dl
n
DM
tDH
tDH
DON’T CARE
UNDEFINED
Dl n=Data In for column n
Burst Length=4 in the case shown
3 subsequent elements of Data In are applied in the programmed
order following Dl n
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VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
DATA OUTPUT TIMING
tDSDQ
min
tDSDQ
max
DQS
Do
n
DQ
tDSDQ
tDSDQ
min
min
DQS,DO
tDV
tDV
DON’T CARE
UNDEFINED
Burst Length=4 in the case shown
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VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
INITIALIZE AND LOAD MODE REGISTERS
VDD
VDDQ
tVTD
VTT
(system*)
VREF
tCK
tCH tCL
CLK#
CLK
tIS tIH
CKE
LVCMOS LOW LEVEL
NOP
COMMAND
PRE
LMR
LMR
PRE
AR
ACT
AR
DM
tIS tIH
A0,A9,
A11,A12
CODE
ALL BANKS
ALL BANKS
A10
CODE
tIS tIH
DQS
High-Z
DQ
High-Z
CODE
RA
tIS tIH
tIS tIH
BA0=H,
BA1=L
BA0,BA1
RA
CODE
BA0=L,
BA1=L
BA
T=200 µs
tMRD
Power-up:
VDD and
CLK stable
Load
Extended
Mode
Register
200
cycles
of CLK...
Load
Base
Mode
Register
tRP
tRC
tRC
DON’T CARE
UNDEFINED
•=VTT is not applied directly to the device, however tVTD must be greater than or equal to
zero to avoid device latch-up.
••=t MRD is required before any command can be applied, and 200 cycles of CLK are required before a
READ command can be applied.
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VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
POWER-DOWN MODE
t
CK
t
CH
t
CL
CLK#
CLK
tIS
tIH
tIS
tIS
CKE
tIS tIH
COMMAND
VALID*
tIS
ADDR
VALID
NOP
tIH
VALID
VALID
DQS
DQ
DM
Enter
Power-Down
Mode
Exit
Power-Down
Mode
DON’T CARE
UNDEFINED
No column accesses are allowed to be in progress at the time Power-Down in entered
*= If this command is a PRECHARGE (or if the device is already in the idle state) then the Power-Down
mode shown is Precharge Power Down. If this command is an ACTIVE (or if at lease one row is already
active) then the Power-Down mode shown is Active Power Down.
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VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
AUTO REFRESH MODE
tCK
tCH
tCL
CLK#
CLK
tIS tIH
CKE
VALID
VALID
tIS tIH
COMMAND
NOP
PRE
NOP
NOP
AR
NOP
AR
NOP
NOP
A0-A8
ACT
RA
A9,A11,A12
RA
ALL BANKS
A10
RA
ONE BANK
tIS tIH
BA0,BA1
BA
*Bank(s)
DQS
DQ
DM
tRC
tRP
tRC
DON’T CARE
UNDEFINED
DIS AP=Disable Autoprecharge
*=*Don’t Care”, if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active(i.e. must precharge all active banks)
PRE=PRECHARGE, ACT=ACTIVE, RA=Row Address, BA=Bank Address, AR=AUTOREFRESH
NOP commands are shown for ease of illustration; other valid commands may be possible at these times
DM, DQ and DQS signals are all *Don’t Care”/High-Z for operations shown
Document : 1G5-0157
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VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
SELF REFRESH MODE
t
CK
t
CH
clock must be stable before
exiting Self Refresh mode
t
CL
CLK#
CLK
tIS
tIH
tIS
tIH
tIS
tIS
CKE
COMMAND
NOP
AR
VALID
NOP
tIS tIH
VALID
ADDR
DQS
DQ
DM
tRP*
200 cycles
of CLK**
EXIT
Self Refresh
Mode
Enter
Self Refresh
Mode
DON’T CARE
UNDEFINED
*=Device must be in the “All banks idle” state prior to entering Self Refresh mode
**=tRC is required before any command can be applied, and 200 cycles of CLK are required before a READ
command can be applied.
The minimum time in Self Refresh mode is tRAS MIN.
Document : 1G5-0157
Rev.1
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VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
READ-WITHOUT AUTO PRECHARGE
tCH
tCK
tCL
CLK#
CLK
tIS tIH
tIH
CKE
VALID
VALID
VALID
NOP
NOP
NOP
tIS tIH
COMMAND
NOP
READ
NOP
PRE
NOP
NOP
ACT
tIS tIH
x4:A0,A9,A11
x8:A0,A9
x16:A0,A8
RA
Col n
x4:A12
x8:A9,A12
x16:A8,A9,A12
RA
tIS tIH
ALL BANKS
A10
RA
DIS AP
ONE BANK
tIS tIH
BA0,BA1
Bank x
Bank x
*Bank x
CL=2
tRP
tRPR
tAC
tLZ
tRPO
max
tHZ
max
max
DQS
tLZ
min
DQ
DO
n
tAC
min
tHZ
min
DM
DON’T CARE
UNDEFINED
DO n=Data Out from column n
Burst Length=4 in the case shown
3 subsequent elements of Data Out are provided in the programmed order following Do n
DIS AP= Disable Autoprecharge
*=”Don’t Care”, if A10 is HIGH at this point
PRE=PRECHARGE, ACT=ACTIVE,RA=Row Address, BA=Bank Address
NOP commands are shown for ease of illustration; other commands may be valid at these times
Document : 1G5-0157
Rev.1
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VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
READ-WITH AUTO PRECHARGE
tCH
tCK
tCL
CLK#
CLK
tIS tIH
tIH
CKE
VALID
VALID
VALID
NOP
NOP
NOP
tIS tIH
COMMAND
NOP
READ
NOP
PRE
NOP
NOP
ACT
tIS tIH
x4:A0,A9,A11
x8:A0,A9
x16:A0,A8
RA
Col n
x4:A12
x8:A9,A12
x16:A8,A9,A12
RA
EN AP
A10
RA
tIS tIH
BA0,BA1
Bank x
Bank x
CL=2
tRP
tRPR
tAC
tLZ
tRPO
max
tHZ
max
max
DQS
tLZ
min
DQ
DO
n
tAC
min
tHZ
min
DM
DON’T CARE
UNDEFINED
DO n=Data Out from column n
Burst Length=4 in the case shown
3 subsequent elements of Data Out are provided in the programmed order following DO n
EN AP=Enable Autoprecharge
ACT=ACTIVE, RA=Row Address
NOP commands are shown for ease of illustration; other commands may be valid at these times
Document : 1G5-0157
Rev.1
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VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
BANK READ ACCESS
tCH
tCK
tCL
CLK#
CLK
tIS tIH
CKE
VALID
tIS tIH
COMMAND
NOP
ACT
NOP
READ
NOP
PRE
NOP
ACT
NOP
NOP
tIS tIH
x4:A0,A9,A11
x8:A0,A9
x16:A0,A8
RA
x4:A12
x8:A9,A12
x16:A8,A9,A12
RA
Col n
RA
RA
tIS tIH
A10
RA
RA
ONE BANK
DIS AP
tIS tIH
BA0,BA1
ALL BANKS
Bank x
*Bank x
Bank x
Bank x
tRC
tRAS
tRCD
CL=2
tRP
tRPR
tAC
tLZ
tRPO
max
tHZ
max
max
DQS
tLZ
min
DQ
DO
N
tAC
min
tHZ
min
DM
DON’T CARE
UNDEFINED
DO n=Data Out from column n
Burst Length=4 in the case shown
3 subsequent elements of Data Out are provided in the programmed order following DO n
DIS AP=Disable Autoprecharge
*=”Don’t Care”, if A10 is HIGH at this point
PRE=PRECHARGE, ACT=ACTIVE, RA=Row Address, BA=Bank Address
NOP commands are shown for ease of illustration; other commands may be valid at these times
Document : 1G5-0157
Rev.1
Page 82
VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
WRITE-WITHOUT AUTO PRECHARGE
tCH
tCK
tCL
CLK#
CLK
tIS tIH
tIH
CKE
VALID
tIS tIH
COMMAND
NOP
NOP
WRITE
NOP
NOP
NOP
PRE
NOP
NOP
ACT
tIS tIH
x4:A0,A9,A11
x8:A0,A9
x16:A0,A8
Col n
RA
x4:A12
x8:A9,A12
x16:A8,A9,A12
RA
tIS tIH
ALL BANKS
A10
RA
DIS AP
ONE BANK
tIS tIH
BA0,BA1
Bank x
*Bank x
tDSS
DQS
tDSH
tWR
BA
tRP
tWPO
tWCP
tDSL
DQ
tWPR
Dl
n
DM
DON’T CARE
UNDEFINED
DI n=Data In for column n
Burst Length=4 in the case shown
3 subsequent elements of Data In are provided in the programmed order following DI n
DIS AP=Disable Autoprecharge
*=”Don’t Care”, if A10 is HIGH at this point
PRE=PRECHARGE, ACT=ACTIVE, RA=Row Address, BA=Bank Address
NOP commands are shown for ease of illustration; other commands may be possible at these times
Document : 1G5-0157
Rev.1
Page 83
VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
WRITE-WITH AUTO PRECHARGE
tCH
tCK
tCL
CLK#
CLK
tIS tIH
CKE
VALID
VALID
VALID
NOP
NOP
NOP
tIS tIH
COMMAND
NOP
NOP
WRITE
NOP
NOP
NOP
ACT
tIS tIH
x4:A0,A9,A11
x8:A0,A9
x16:A0,A8
Col n
RA
x4:A12
x8:A9,A12
x16:A8,A9,A12
RA
EN AP
A10
RA
tIS tIH
BA0,BA1
Bank x
BA
tDSS
DQS
tDSH
tWR
tRP
tWPO
tWCP
tDSL
tWPR
DQ
Dl
n
DM
DON’T CARE
UNDEFINED
DI n=Data In for column n
Burst Length=4 in the case shown
3 subsequent elements of Data In are provided in the programmed order following DI n
DIS AP=Disable Autoprecharge
*=”Don’t Care”, if A10 is HIGH at this point
PRE=PRECHARGE, ACT=ACTIVE, RA=Row Address, BA=Bank Address
NOP commands are shown for ease of illustration; other commands may be possible at these times
Document : 1G5-0157
Rev.1
Page 84
VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
BANK WRITE ACCESS
tCH
tCK
tCL
CLK#
CLK
tIS tIH
CKE
VALID
tIS tIH
COMMAND
NOP
ACT
NOP
NOP
WRITE
NOP
NOP
NOP
PRE
NOP
tIS tIH
x4:A0,A9,A11
x8:A0,A9
x16:A0,A8
RA
x4:A12
x8:A9,A12
x16:A8,A9,A12
RA
A10
BA0,BA1
Col n
tIS tIH
ALL BANKS
tIS tIH
DIS AP
ONE BANK
Bank x
Bank x
RA
*Bank x
tRAS
tRCD
tDSS
tDSH
tWR
tWPO
DQS
tWCP
tDSL
tWPR
DQ
Dl
n
DM
DON’T CARE
UNDEFINED
DI n=Data In for column n
Burst Length=4 in the case shown
3 subsequent elements of Data In are provided in the programmed order following DI n
DIS AP=Disable Autoprecharge
*=”Don’t Care”, if A10 is HIGH at this point
PRE=PRECHARGE, ACT=ACTIVE, RA=Row Address, BA=Bank Address
NOP commands are shown for ease of illustration; other commands may be possible at these times
Document : 1G5-0157
Rev.1
Page 85
VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
WRITE-DQM OPERATION
tCH
tCK
tCL
CLK#
CLK
tIS tIH
CKE
VALID
tIS tIH
COMMAND
NOP
NOP
WRITE
NOP
NOP
NOP
PRE
NOP
NOP
ACT
tIS tIH
x4:A0,A9,A11
x8:A0,A9
x16:A0,A8
Col n
RA
x4:A12
x8:A9,A12
x16:A8,A9,A12
RA
tIS tIH
ALL BANKS
A10
RA
DIS AP
ONE BANK
tIS tIH
BA0,BA1
Bank x
*Bank x
tDSS
DQS
tDSH
tWR
BA
tRP
tWPO
tWCP
tDSL
DQ
tWPR
Dl
n
DM
DON’T CARE
UNDEFINED
DI n=Data In for column n
Burst Length=4 in the case shown
3 subsequent elements of Data In are provided in the programmed order following DI n (The second element
of the four is masked)
DIS AP=Disable Autoprecharge
*=”Don’t Care”, if A10 is HIGH at this point
PRE=PRECHARGE, ACT=ACTIVE, RA=Row Address, BA=Bank Address
NOP commands are shown for ease of illustration; other commands may be possible at these times
Document : 1G5-0157
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