WINBOND W27L520

Preliminary W27L520
64K × 8 ELECTRICALLY ERASABLE EPROM
GENERAL DESCRIPTION
The W27L520 is a high speed, low power Electrically Erasable and Programmable Read Only
Memory organized as 65,536 × 8 bits. It includes latches for the lower 8 address lines to multiplex
with the 8 data lines. To cooperate with the MCU, this device could save the external TTL
component, also cost and space. It requires only one supply in the range of 3.0V in normal read
mode. The W27L520 provides an electrical chip erase function. It will be a great convenient when you
need to change/update the contents in the device.
FEATURES
• High speed access time: 70/90 nS (max.)
• Read operating current: 8 mA (max.)
• Erase/Programming operating current
30 mA (max.)
• Standby current: 20 µA (max.)
• Unregulated battery power supply range,
3.0V to 3.6V
• +13V erase and programming voltage
PIN CONFIGURATIONS
compatible
• Three-state outputs
• Available packages: 20-pin TSSOP and 20-pin
SOP
BLOCK DIAGRAM
A10
1
20
A12
2
19
A8
AD1
A14
3
18
AD3
ALE
VDD
4
17
AD5
5
AD7
OE/VPP
6
TSSOP 16
Top View
15
GND
7
14
AD6
A13
8
13
AD4
A11
9
12
AD2
A9
10
11
AD0
A15
• High Reliability CMOS Technology
- 2K V ESD Protection
- 200 mA Latchup Immunity
• Fully static operation
• All inputs and outputs directly LVTTL/CMOS
ALE
CONTROL
OE / VPP
L
A
T
C
H
E
S
AD7 - AD0
DECODER
OUTPUT
BUFFER
MEMORY
ARRAY
A15 - A8
VDD
GND
OE/VPP
A15
1
20
VDD
2
19
ALE
A13
3
18
A14
A11
4
17
A12
A9
5
SOP
16
Top View
A10
AD0
6
15
A8
AD2
AD4
7
14
AD1
8
13
AD6
GND
9
12
AD3
AD5
10
11
AD7
PIN DESCRIPTION
SYMBOL
AD0−AD7
A8−A15
ALE
OE/VPP
VDD
GND
-1-
DESCRIPTION
Address/Data Inputs/Outputs
Address Inputs
Address Latch Enable
Output Enable, Program/Erase
Supply Voltage
Power Supply
Ground
Publication Release Date: 4/26/2000
Revision A2
Preliminary W27L520
FUNCTIONAL DESCRIPTION
Read Mode
Unlike conventional UVEPROMs, which has CE and OE two control functions, the W27L520 has one
OE/VPP and one ALE (address_latch_enable) control functions. The ALE makes lower address A[7:0]
to be latched in the chip when it goes from high to low, so that the same bus can be used to output
data during read mode. i.e. lower address A[7:0] and data bus DQ[7:0] are multiplexed. OE/VPP
controls the output buffer to gate data to the output pins. When addresses are stable, the address
access time (TACC) is equal to the delay from ALE to output (TCE), and data are available at the
outputs TOE after the falling edge of OE/VPP, if TACC and TCE timings are met.
Erase Mode
The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs,
which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half
an hour), the W27L520 uses electrical erasure. Generally, the chip can be erased within 100 mS by
using an EPROM writer with a special erase algorithm.
There are two ways to enter Erase mode. One is to raise OE/VPP to VPE (13V), VDD = VDE (6.5V), A9
= VHH (13V), A10 = high A8&A11 = low, and all other address pins include AD[7:0] keep at fixed low
or high. Pulsing ALE high starts the erase operation. The other way is somewhat like flash, by
programming two consecutive commands into the device and then enter Erase mode. The two
commands are loading Data = AA(hex) to Addr. = 5555(hex) and Data = 10(hex) to Addr. =
2AAA(hex). Be careful to note that the ALE pulse widths of these two commands are different: One is
50uS, while the other is 100mS. Please refer to the Smart Erase Algorithm 1 & 2.
Erase Verify Mode
The device will enter the Erase Verify Mode automatically after Erase Mode. Only power down the
device can force the device enter Normal Read Mode again.
Program Mode
Programming is the only way to change cell data from "1" to "0." The program mode is entered when
OE/VPP is raised to VPP (13V), VDD = VDP (6.5V), the address pins equal the desired addresses, and
the input pins equal the desired inputs. Pulsing ALE high starts the programming operation.
Program Verify Mode
The device will enter the Program Verify Mode automatically after Program Mode. Only power down
the device can force the device enter Normal Read Mode again.
Erase/Program Inhibit
Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different
data. When ALE low, erasing or programming of non-target chips is inhibited, so that except for the
ALE and OE/VPP pins, the W27L520 may have common inputs.
Standby Mode
The standby mode significantly reduces VDD current. This mode is entered when ALE and OE/VPP
keep high. In standby mode, all outputs are in a high impedance state.
System Considerations
-2-
Preliminary W27L520
An EPROM's power switching characteristics require careful device decoupling. System designers are
interested in three supply current issues: standby current levels (ISB), active current levels (IDD), and
transient current peaks produced by the falling and rising edges of ALE Transient current magnitudes
depend on the device output's capacitive and inductive loading. Proper decoupling capacitor selection
will suppress transient voltage peaks. Each device should have a
0.1 µF ceramic capacitor connected between its VDD and GND. This high frequency, low inherentinductance capacitor should be placed as close as possible to the device. Additionally, for every eight
devices, a 4.7 µF electrolytic capacitor should be placed at the array's power supply connection
between VDD and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace
inductances.
TABLE OF OPERATING MODES
(VPP = 13V, VPE = 13V, VHH = 12V, VDP = 6.5V, VDE = 6.5V, VDD = 3.3V, VDI = 5.0V, X = VIH or VIL)
MODE
OE/VPP
PIN
OTHER ADDRESS
VDD
VIH
VIH
X
VDD
A[7:0]
Read
VIL
VIL
AIN
VDD
DOUT
Output Disable
VIL
VIH
X
VDD
High Z
Standby
VIH
VIH
AIN
VDD
A[7:0]
Program
VIH
VPP
AIN
VDP
DIN
Erase 1
VIH
VPE
A8&A11 = VIL, A9 = VPE,
A10 = VIH, Others = X
VDE
X
Erase 2
VIH
VPE
First command:
Addr. = 5555 (hex)
VDE
AA(hex)
Secon command:
Addr. = 2AAA (hex)
VDE
10(hex)
ALE
Address Latch Enable
AD[7:0]
Product Identifiermanufacturer
VIL
VIL
A8 = VIL, A9 = VHH, Others = X
VDI
DA(Hex)
Product Identifier-device
VIL
VIL
A8 = VIH, A9 = VHH, Others = X
VDI
1F(Hex)
-3-
Publication Release Date: 4/26/2000
Revision A2
Preliminary W27L520
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER
Ambient Temperature with Power Applied
Storage Temperature
Voltage on all Pins with Respect to Ground Except
OE/VPP, A9 and VDD Pins
Voltage on OE/VPP Pin with Respect to Ground
Voltage on A9 Pin with Respect to Ground
Voltage VDD Pin with Respect to Ground
RATING
-55 to +125
-65 to +150
-2.0 to +7.0
UNIT
°C
°C
V
-2.0 to +7.0
-2.0 to +7.0
-2.0 to +14.0
V
V
V
Note: 1. Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of
the device.
2. Minimum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20ns. Maximum output pin voltage is
VDD+0.75V DC which may overshoot to +7.0V for pulses of less than 20ns.
DC Erase Characteristics
(TA = 25° C ±5° C, VDD = 6.5V ±0.25V)
PARAMETER
SYM.
CONDITIONS
Input Load Current
VDD Erase Current
ILI
ICP
VPP Erase Current
IPP
Input Low Voltage
Input High Voltage
Output Low Voltage
(Verify)
Output High Voltage
(Verify)
A9 SID Voltage
A9 Erase Voltage
VPP Erase Voltage
VDD Supply Voltage (Erase
& Erase Verify)
VIL
VIH
VOL
VIN = VIL or VIH
ALE = VIH, OE/VPP = VPE
A8&A11 = VIL, A9 = VPE,
A10 = VIH, Others = X
ALE = VIH, OE/VPP = VPE
A8&A11 = VIL, A9 = VPE,
A10 = VIH, Others = X
IOL = 2.1 mA
VOH
IOH = -0.4 mA
VHH
VPE
VPE
VDE
VDD = 5V ± 10%
-
MIN.
-10
-
LIMITS
TYP.
MAX.
10
30
UNIT
µA
mA
-
-
30
mA
-0.3
2.4
-
-
0.8
VDD+0.3
0.45
V
V
V
2.4
-
-
-
11.5
12.75
12.75
6.25
12
13
13
6.5
12.5
13.25
13.25
6.75
V
V
V
V
Note: VDD must be applied simultaneously or before VPP and removed simultaneously or after VPP.
CAPACITANCE
(VDD = 3.0V to 3.6V, TA = 25° C, f = 1 MHz)
PARAMETER
Input Capacitance
Output Capacitance
SYMBOL
CIN
COUT
VIN = 0V
VOUT = 0V
-4-
MAX.
6
12
UNIT
pF
pF
Preliminary W27L520
AC CHARACTERISTICS
AC Test Conditions
PARAMETER
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Level
Output Load
CONDITIONS
0V/3V
10 nS
1.5V/1.5V
CL = 100 pF, IOH/IOL = -0.4 mA/2.1 mA
AC Test Load and Waveforms
+1.3V
(IN914)
3.3K ohm
DOUT
100 pF (Including Jig and Scope)
Input
Output
Test Points
Test Points
3V
1.5V
1.5V
0V
-5-
Publication Release Date: 4/26/2000
Revision A2
Preliminary W27L520
READ OPERATION DC CHARACTERISTICS
(VDD = 3.0V to 3.6V, TA = 0 to 70° C)
PARAMETER
SYM.
CONDITIONS
MIN.
Input Load Current
Output Leakage Current
Standby VDD Current
(CMOS input)
ILI
ILO
ISB
VIN = 0V to VDD
VOUT = 0V to VDD
VDD Operating Current
IDD
ALE = VIL, IOUT = 0 mA
f = 5 MHz
Input Low Voltage
Input High Voltage
VIL
VIH
Output Low Voltage
Output High Voltage
VOL
VOH
ALE = VDD ±0.3V, OE/VPP = VDD ±0.3V
All others inputs
= GND/ VDD ±0.3V
IOL = 2.1 mA
IOH = -0.4 mA
-5
-5
-
LIMITS
TYP. MAX
.
5
5
20
UNIT
µA
µA
µA
-
-
8
mA
-0.6
2.0
-
V
V
2.4
-
0.8
VDD
+0.3
0.4
-
V
V
READ OPERATION AC CHARACTERISTICS
(VDD = 3.0V to 3.6V, TA = 0 to 70° C)
PARAMETER
Address Latch Enable Access Time
Address Latch Enable Width
Address Access Time
Address Setup Time
Address Hold Time
Output Enable Access Time
OE /VPP High to High-Z Output
Output Hold from Address Change
SYM.
TCE
TALE
TACC
TAS
TAH
TOE
TDF
TOH
W27L520-70
MIN.
MAX.
45
15
15
0
70
70
35
25
-
W27L520-90
MIN.
MAX
.
90
45
90
15
15
35
25
0
-
Note: VDD must be applied simultaneously or before VPP and removed simultaneously or after VPP.
-6-
UNIT
nS
nS
nS
nS
nS
nS
nS
nS
Preliminary W27L520
DC PROGRAMMING CHARACTERISTICS
(VDD = 6.5V ±0.25V, TA = 25° C ±5° C)
PARAMETER
SYM.
CONDITIONS
LIMITS
UNIT
MIN.
-10
TYP.
-
MAX.
10
ALE = VIH,
-
-
30
µA
mA
OE /VPP = VPP
ALE = VIH,
-
-
30
mA
-0.3
2.4
2.4
11.5
12.0
0.8
VDD+0.5
0.45
12.5
V
V
V
V
V
12.75
6.25
13.0
6.5
13.25
6.75
V
V
MIN.
LIMITS
TYP.
MAX.
Input Load Current
ILI
VIN = VIL or VIH
VDD Program Current
ICP
VPP Program Current
IPP
Input Low Voltage
Input High Voltage
Output Low Voltage (Verify)
Output High Voltage (Verify)
A9 Silicon I.D. Voltage
VIL
VIH
VOL
VOH
VHH
VPP Program Voltage
VDD Supply Voltage (Program)
VPP
VDP
OE /VPP = VPP
IOL = 2.1 mA
IOH = -0.4 mA
VDD = 5V ± 10%
-
AC PROGRAMMING/ERASE CHARACTERISTICS
(VDD = 6.5V ±0.25V, TA = 25° C ±5° C)
PARAMETER
SYM.
UNIT
OE /VPP Pulse Rise Time
Address Latch Enable Width
ALE Program Pulse Width
TPRT
50
-
-
nS
TALE
TPPW
500
47.5
50
52.5
nS
ALE Erase Pulse Width
ALE Erase Pulse Width 1
TEPW
TEPW1
95
47.5
100
50
105
52.5
ALE Erase Pulse Width 2
Latched Address Setup Time
Latched Address Hold Time
Address Setup Time
TEPW2
TLAS
TLAH
TAS
95
100
100
2.0
100
-
105
-
Address Hold Time
TAH
0
-
-
µS
OE /VPP Setup Time
TOES
2.0
-
-
µS
OE /VPP Hold Time
Data Setup Time
Data Hold Time
TOEH
2.0
-
-
µS
Data Valid from OE /VPP Low during Erase Verify
TDS
TDH
TEOE
2.0
2.0
-
-
150
µS
µS
nS
Data Valid from OE /VPP Low during Program Verify
TPOE
-
-
150
nS
OE /VPP High to Output High Z
TDFP
0
-
130
nS
OE /VPP High Voltage Delay After ALE Low
TVS
2.0
-
-
µS
OE /VPP Recovery Time
TVR
2.0
-
-
µS
µS
mS
µS
mS
nS
nS
µS
Note: VDD must be applied simultaneously or before VPP and removed simultaneously or after VPP.
-7-
Publication Release Date: 4/26/2000
Revision A2
Preliminary W27L520
TIMING WAVEFORMS
AC Read Waveform
VIH
A8-A15
Address Valid
VIL
TALE
ALE
VIH
VIL
TCE
VIH
TOE
OE/Vpp
TDF
VIL
TAS
TOH
High Z
High Z
AD0-AD7
TAH
Data
Address
TACC
Programming Waveform
PROGRAM
A[15:8]
TAS
VIH
TAH
Address Stable
V IL
TRPT
13V
OE/Vpp
PROGRAM (VERIFY)
VIH
TOES TOEH
V IL
TVR
TVS
ALE
VIH
V IL
AD[7:0]
VIH
V IL
TALE
TPPW
TALE
TLAH
TLAS
Add
TDH
T DS
TPOE
Add
Data in
-8-
TDFP
Data out
Preliminary W27L520
Timing Waveforms, continued
Erase Waveform 1
Read
Device
SID
Read
Company
SID
Chip Erase
A9 = 13.0V
Others = VILor VIH
A8, A11 = VIL
A10 = VIH
Others = VIL or VIH
V IH
A8 = VIL
V IL
VDD = 6.5V
VDD = 6.5V
VDD =3.3V
A9 = 12.0V
A[15:8]
Erase (Verify)
A8 = VIH
Address Valid
V IH
AD[7:0]
DA
V IL
13.0V
1F
Add
TPRT
TVR
DOUT
TEOE
V IH
OE/Vpp
V IL
TOEH
TOES
V IH
ALE V
IL
TEPW
Erase Waveform 2
Read
Company
SID
A[15:8]
V IH
V IL
Read
Device
SID
Chip Erase
Command 1
VDD =6.5V
VDD =3.3V
A9=12.0
V
Others=VIL or VIH
A8=VIL
Erase Verify
VDD =6.5V
VDD =6.5V
TAS
A[15:8] = 55
A8=V IH
A[15:8] = 2A
Address Valid
TRPT
13.0V
OE/Vpp V IH
V IL
Command 2
DA
1F
Add
TOES
DOUT
TOEH
TVS
TPRT
TEOE
V IH
ALE V
IL
TALE
TOES
V IH
AD[7:0]
V IL
TEPW1
TLAH
TLAS
55
TDS
TEPW2
TDH
AA
AA
10
Note: First command Address = 5555(hex) with Data = AA(hex)
Second command Address = 2AAA(hex) with Data = 10(hex)
-9-
Publication Release Date: 4/26/2000
Revision A2
Preliminary W27L520
SMART PROGRAMMING ALGORITHM 1
Start
Address = First Location
VDD = 6.5V
OE/Vpp = 13V
Program One 50 µ S Pulse
Increment
Address
No
Last
Address ?
Yes
Address = First Location
Increment
Address
X=0
No
Last
Address ?
Pass
Fail
Verify
Byte
Increment X
Yes
Power
Down
No
Program One 50 µ S Pulse
X = 25 ?
VDD = 3.3V
OE/Vpp = VIL
Yes
Compare
All Bytes to
Original
Data
Pass
Device
Passed
- 10 -
Fail
Device
Failed
Preliminary W27L520
SMART PROGRAMMING ALGORITHM 2
Start
Address = First Location
VDD = 6.5V
X=0
Program One 50 µS Pulse
OE/Vpp = 13V
Increment X
X = 25?
Yes
No
Fail
Verify One Byte
OE/Vpp = V IL
Verify One Byte
OE/Vpp = V IL
Pass
Increment
Address
Fail
Pass
No
Last Address
?
Yes
Power
Down
VDD =3.3V
Compare
All Bytes to
Original Data
Fail
Pass
Device
Passed
- 11 -
Device
Failed
Publication Release Date: 4/26/2000
Revision A2
Preliminary W27L520
SMART ERASE ALGORITHM 1
Start
X=0
VDD= 6.5V
OE/Vpp = 13V
A9 = 13V; A8&A11 = V IL
A10 = V IH
Chip Erase 100 mS Pulse
Address = First Location
Increment X
V DD= 6.5V
OE/Vpp = V IL
No
Fail
Erase
Verify
X = 20?
Pass
Yes
Increment
Address
No
Last
Address?
Yes
Power
Down
VDD = 3.3V
OE/Vpp = V IL
Compare
All Bytes to
FFs (HEX)
Fail
Pass
Pass
Device
Fail
Device
- 12 -
Preliminary W27L520
SMART ERASE ALGORITHM 2
Start
X=0
VDD = 6.5V
OE/Vpp = 13V
Program One 50µ S Pulse
with Address = 5555(Hex) Data = AA(Hex)
Program One 100 mS Pulse
with Address = 2AAA(Hex) Data = 10(Hex)
Increment X
VDD = 6.5V
OE/Vpp = V IL
No
Fail
Erase
Verify
X = 20?
Pass
Yes
Increment
Address
No
Last
Address?
Yes
Power
Down
VDD = 3.3V
OE/Vpp = V IL
Compare
All Bytes to
FFs (HEX)
Fail
Pass
Fail
Device
Pass
Device
- 13 -
Publication Release Date: 4/26/2000
Revision A2
Preliminary W27L520
ORDERING INFORMATION
PART NO.
W27L520W-70*
W27L520W-90*
W27L520S-70*
W27L520S-90*
ACCESS
TIME
(nS)
70
90
70
90
OPERATING
CURRENT
MAX. (mA)
8
8
8
8
STANDBY
CURRENT
MAX. (µ
µ A)
20
20
20
20
PACKAGE
173mil TSSOP
173mil TSSOP
300mil SOP
300mil SOP
Notes:
1. The Part No is preliminary and might be changed after project is consoled.
2. Winbond reserves the right to make changes to its products without prior notice.
3. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications
where personal injury might occur as a consequence of product failure.
- 14 -
Preliminary W27L520
PACKAGE DIMENSIONS
20-pin TSSOP
c
L
b
Dimension in Inches
Symbol
E1
E
θ
e
A
Nom. Max.
Dimension in mm
Min.
Nom. Max.
0.043
1.10
A
A1
0.002
0.006 0.05
0.15
L
0.020
0.028 0.50
0.70
D
E
E1
0.252
0.260 6.40
6.60
0.246
0.256 6.25
6.50
0.169
0.176
4.30
4.48
0.007
0.012 0.18
0.30
0.003
0.007
0.09
0.18
8
0
b
c
e
θ
D
Min.
0.65 BSC
0
0.256 BSC
8
A1
20-pin SOP
c
L
b
Dimension in Inches
Symbol
E1
E
θ
e
D
A
Min.
Nom. Max.
0.092
Dimension in mm
Min.
Nom. Max.
0.105 2.34
2.67
A
A1
0.003
0.012 0.076
0.305
L
0.015
0.035 0.381
0.889
D
0.497
0.513 12.6
13.0
E
E1
b
c
e
θ
0.393
0.420 9.98
10.7
0.291
0.299
7.60
7.39
0.013
0.020 0.330
0.508
0.009
0.013 0.229
0.330
1.27 BSC
0.50 BSC
0
8
0
8
A1
- 15 -
Publication Release Date: 4/26/2000
Revision A2
Preliminary W27L520
VERSION HISTORY
VERSION
A1
A2
DATE
Sep. 1999
Feb. 2000
PAGE
3, 4, 9, 11
1
4
6, 7, 8, 9, 10
1,6,14
1,3,6
5
3/14/2000
3
4
4/26/2000
6
1,3,6
1
4
DESCRIPTION
Initial Issued
Specify VDD, VID, VCE, and VHH description
Change VCC as VDD
Change VCE as VDE
Change VCE as VDE, VCP as VDP, VID as VHH, ICC as IDD
Add 90nS bin
Add in power supply range: 4.5V to 5.5V
AC Test Condition: Change Input pulse level to 0V/3V;
Input and Output Timing Reference Level to 1.5V/1.5V
Delete Two-line Output Control section
Modify Storage Temperature Rating from -65 to
+125°C to -65 to +150°C
Modify Output Leakage Current from ±10µA to ±5µA
Delete power supply range: 4.5V to 5.5V
Add in ESD/Latchup information
Modify DC Characteristics
Headquarters
Winbond Electronics (H.K.) Ltd.
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5796096
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-7197006
Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-7190505
FAX: 886-2-7197502
Note: All data and specifications are subject to change without notice.
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Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: 408-9436666
FAX: 408-5441798