WINBOND W27L010-12

Preliminary W27L010
128K × 8 ELECTRICALLY ERASABLE EPROM
GENERAL DESCRIPTION
The W27L010 is a high speed, low power consumption Electrically Erasable and Programmable Read
Only Memory organized as 131072 × 8 bits. It requires only one supply in the range of 3.0V to 3.6V in
normal read mode. The W27L010 provides an electrical chip erase function.
FEATURES
•
•
•
•
•
High speed access time:
90/120 nS (max.)
Read operating current: 10 mA (max.)
Erase/Programming operating current:
30 mA (max.)
Standby current: 20 µA (max.)
Low voltage power supply range, 3.0V to 3.6V
PIN CONFIGURATIONS
•
•
•
•
•
+14V erase/+12V programming voltage
Fully static operation
All inputs and outputs directly TTL/CMOS
compatible
Three-state outputs
Available packages: 32-pin 600 mil DIP, 450
mil SOP and PLCC
BLOCK DIAGRAM
PGM
Vpp
1
32
Vcc
A16
2
31
PGM
A15
3
30
NC
A12
4
29
A14
A7
5
28
A13
A6
6
27
A8
A5
7
26
A4
8
25
A9
A11
A3
9
24
OE
A2
10
23
A10
A1
11
22
A0
12
21
CE
Q7
VCC
32-pin DIP
OUTPUT
BUFFER
DECODER
CORE
ARRAY
A0
.
.
Q0
.
.
Q7
A16
Q0
13
20
Q6
Q1
14
19
Q5
VPP
Q2
15
18
Q4
GND
16
17
Q3
4
5
6
7
8
9
10
11
12 1
13 4
CONTROL
OE
GND
PIN DESCRIPTION
A A A
1 1 1
2 5 6
A7
A6
A5
A4
A3
A2
A1
A0
Q0
CE
3 2
/
V V P
p c G N
p c M C
1
3 3
2 1
3
0 29
28
27
26
32-pin PLCC
25
24
23
1 1 1 1 1 2 22
5 6 7 8 9 0 21
SYMBOL
A0−A16
Q0−Q7
A14
A13
A8
A9
A11
OE
A10
CE
Q7
CE
OE
PGM
VPP
VCC
GND
NC
Q Q G Q Q Q Q
1 2 N 3 4 5 6
D
-1-
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Program Enable
Program/Erase Supply Voltage
Power Supply
Ground
No Connection
Publication Release Date: February 1999
Revision A1
Preliminary W27L010
FUNCTIONAL DESCRIPTION
Read Mode
Like conventional UVEPROMs, the W27L010 has two control functions, both of which produce data at
the outputs.
CE is for power control and chip select. OE controls the output buffer to gate data to the output pins.
When addresses are stable, the address access time (TACC) is equal to the delay from CE to output
(TCE), and data are available at the outputs TOE after the falling edge of OE, if TACC and TCE timings
are met.
Erase Mode
The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs,
which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half
an hour), the W27L010 uses electrical erasure. Generally, the chip can be erased within 100 mS by
using an EPROM writer with a special erase algorithm.
Erase mode is entered when VPP is raised to VPE (14V), VCC = VCE (5V), CE low, OE high, A9 =
VHH (14V), A0 low, and all other address pins low and data input pins high. Pulsing PGM low starts
the erase operation.
Erase Verify Mode
After an erase operation, all of the bytes in the chip must be verified to check whether they have been
successfully erased to "1" or not. The erase verify mode automatically ensures a substantial erase
margin. This mode will be entered after the erase operation if VPP = VPE (14V), CE low, and OE low,
PGM high.
Program Mode
Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only
way to change cell data from "1" to "0." The program mode is entered when VPP is raised to VPP
(12V), VCC = VCP (5V), CE low , OE hig, the address pins equal the desired addresses, and the input
pins equal the desired inputs. Pulsing PGM low starts the programming operation.
Program Verify Mode
All of the bytes in the chip must be verified to check whether they have been successfully
programmed with the desired data or not. Hence, after each byte is programmed, a program verify
operation should be performed. The program verify mode automatically ensures a substantial
program margin. This mode will be entered after the program operation if VPP = VPP (12V), CE low,
OE low, and PGM high.
Erase/Program Inhibit
Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different
data. When CE high , erasing or programming of non-target chips is inhibited, so that except for the
CE, the W27L010 may have common inputs.
-2-
Preliminary W27L010
Standby Mode
The standby mode significantly reduces VCC current. This mode is entered when CE high. In standby
mode, all outputs are in a high impedance state, independent of OE and PGM.
Two-line Output Control
Since EPROMs are often used in large memory arrays, the W27L010 provides two control inputs for
multiple memory connections. Two-line control provides for lowest possible memory power
dissipation and ensures that data bus contention will not occur.
System Considerations
EPROM power switching characteristics require careful device decoupling. System designers are
concerned with three supply current issues: standby current levels (Isb), active current levels (Icc),
and transient current peaks produced by the falling and rising edges of CE . Transient current
magnitudes depend on the device output's capacitive and inductive loading. Two-line control and
proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have
a 0.1 µF ceramic capacitor connected between its Vcc and GND. This high frequency, low inherentinductance capacitor should be placed as close as possible to the device. Additionally, for every eight
devices, a 4.7 µF electrolytic capacitor should be placed at the array's power supply connection
between Vcc and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace
inductances.
TABLE OF OPERATING MODES
VCC = 3.3V, VPP = 12V, VPE = 14V, VHH = 12V, VCP = 5V, X=VIH or VIL
MODE
PINS
A0
A9
VCC
VPP
OUTPUTS
VIL
PGM
X
X
X
VCC
VCC
DOUT
VIL
VIH
X
X
X
VCC
VCC
High Z
VIH
X
X
X
X
VCC
VCC
High Z
VCC ±0.3V
X
X
X
X
VCC
VCC
High Z
Program
VIL
VIH
VIL
X
X
VCP
VPP
DIN
Program Verify
VIL
VIL
VIH
X
X
VCP
VPP
DOUT
Program Inhibit
VIH
X
X
X
X
VCP
VPP
High Z
Erase
VIL
VIH
VIL
VIL
VPE
VCP
VPE
FF (Hex)
Erase Verify
VIL
VIL
VIH
X
X
VCP
VPE
DOUT
Erase Inhibit
VIH
X
X
X
X
VCP
VPE
High Z
Product IdentifierManufacturer
VIL
VIL
X
VIL
VHH
VCC
VCC
DA (Hex)
Product Identifier-device
VIL
VIL
X
VIH
VHH
VCC
VCC
01 (Hex)
CE
OE
Read
VIL
Output Disable
Standby (TTL)
Standby (CMOS)
-3-
Publication Release Date: February 1999
Revision A1
Preliminary W27L010
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER
RATING
UNIT
0 to +70
°C
-65 to +125
°C
-0.5 to VCC +0.5
V
Voltage on VCC Pin with Respect to Ground
-0.5 to +7
V
Voltage on VPP Pin with Respect to Ground
-0.5 to +14.5
V
Voltage on A9 Pin with Respect to Ground
-0.5 to +14.5
V
Operation Temperature
Storage Temperature
Voltage on all Pins with Respect to Ground Except VCC, VPP
and A9 Pins
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
DC Erase Characteristics
(TA = 25° C ±5° C, VCC = 5.0V ±10%, VHH = 14V)
PARAMETER
SYM.
CONDITIONS
Input Load Current
ILI
VIN = VIL or VIH
VCC Erase Current
ICP
CE = VIL, OE = VIH,
LIMITS
UNIT
MIN.
TYP.
MAX.
-10
-
10
µA
-
-
30
mA
-
-
30
mA
PGM = VIL, A9 = VHH
VPP Erase Current
IPP
CE = VIL, OE = VIH,
PGM = VIL, A9 = VHH
Input Low Voltage
VIL
-
-0.3
-
0.8
V
Input High Voltage
VIH
-
2.4
-
5.5
V
Output Low Voltage (Verify)
VOL
IOL = 2.1 mA
-
-
0.45
V
Output High Voltage (Verify)
VOH
IOH = -0.4 mA
2.4
-
-
V
A9 Erase Voltage
VID
-
13.25
14.0
14.25
V
VPP Erase Voltage
VPE
-
13.25
14.0
14.25
V
VCC Supply Voltage (Erase)
VCE
-
4.5
5.0
5.5
V
Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.
-4-
Preliminary W27L010
CAPACITANCE
(VCC = 3.0V to 3.6V , TA = 25° C, f = 1 MHz)
PARAMETER
SYMBOL
CONDITIONS
MAX.
UNIT
Input Capacitance
CIN
VIN = 0V
6
pF
Output Capacitance
COUT
VOUT = 0V
12
pF
AC CHARACTERISTICS
AC Test Conditions
PARAMETER
CONDITIONS
Input Pulse Levels
0.45V to 2.4V
Input Rise and Fall Times
10 nS
Input and Output Timing Reference Level
0.8V/2.0V
Output Load
CL = 100 pF,
IOH/IOL = -0.1 mA/1.6 mA
AC Test Load and Waveforms
+1.3V
(IN914)
3.3K ohm
D OUT
100 pF (Including Jig and Scope)
Output
Input
Test Points
2.4V
0.45V
Test Points
2.0V
2.0V
0.8V
0.8V
-5-
Publication Release Date: February 1999
Revision A1
Preliminary W27L010
READ OPERATION DC CHARACTERISTICS
(VCC = 3.0V to 3.6V, TA = 0 to 70° C)
PARAMETER
SYM.
CONDITIONS
LIMITS
UNIT
MIN.
TYP.
MAX.
Input Load Current
ILI
VIN = 0V to VCC
-5
-
5
µA
Output Leakage Current
ILO
VOUT = 0V to VCC
-10
-
10
µA
Standby VCC Current
(TTL input)
ISB
CE = VIH
-
-
200
µA
Standby VCC Current
(CMOS input)
ISB1
CE = VCC ±0.2V
-
-
20
µA
VCC Operating Current
ICC
CE = VIL
IOUT = 0 mA
f = 5 MHz
-
-
10
mA
VPP Operating Current
IPP
VPP = VCC
-
-
10
µA
Input Low Voltage
VIL
-
-0.3
-
0.6
V
Input High Voltage
VIH
-
2.0
-
VCC +0.5
V
Output Low Voltage
VOL
IOL = 1.6 mA
-
-
0.4
V
Output High Voltage
VOH
IOH = -0.1 mA
2.4
-
-
V
VPP Operating Voltage
VPP
VCC -0.7
-
VCC
V
-
READ OPERATION AC CHARACTERISTICS
(VCC = 3.0V to 3.6V, TA = 0 to 70° C)
PARAMETER
SYM.
W27L010-90
W27L010-12
MAX.
MIN.
MAX.
MIN.
UNIT
Read Cycle Time
TRC
90
-
120
-
nS
Chip Enable Access Time
TCE
-
90
-
120
nS
Address Access Time
TACC
-
90
-
120
nS
Output Enable Access Time
TOE
-
40
-
55
nS
OE High to High-Z Output
TDF
-
25
-
30
nS
Output Hold from Address Change
TOH
0
-
0
-
nS
Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.
-6-
Preliminary W27L010
DC PROGRAMMING CHARACTERISTICS
(VCC = 5.0V ±10%, TA = 25° C ±5° C)
PARAMETER
SYM.
CONDITIONS
LIMITS
UNIT
MIN.
TYP.
MAX.
Input Load Current
ILI
VIN = VIL or VIH
-
-
10
µA
VCC Program Current
ICP
CE = VIL, OE = VIH,
-
-
30
mA
-
-
30
mA
PGM = VIL
VPP Program Current
IPP
CE = VIL, OE = VIH,
PGM = VIL
Input Low Voltage
VIL
-
-0.3
-
0.8
V
Input High Voltage
VIH
-
2.4
-
5.5
V
Output Low Voltage (Verify)
VOL
IOL = 2.1 mA
-
-
0.45
V
Output High Voltage (Verify)
VOH
IOH = -0.4 mA
2.4
-
-
V
A9 Silicon I.D. Voltage
VID
-
11.5
12.0
12.5
V
VPP Program Voltage
VPP
-
11.75
12.0
12.25
V
VCC Supply Voltage (Program)
VCP
-
4.5
5.0
5.5
V
AC PROGRAMMING/ERASE CHARACTERISTICS
(VCC = 5.0V ±10%, TA = 25° C ±5° C)
PARAMETER
SYM.
LIMITS
UNIT
MIN.
TYP.
MAX.
VPP Setup Time
TVPS
2.0
-
-
µS
Address Setup Time
TAS
2.0
-
-
µS
Data Setup Time
TDS
2.0
-
-
µS
PGM Program Pulse Width
TPWP
95
100
105
µS
PGM Erase Pulse Width
TPWE
95
100
105
mS
Data Hold Time
TDH
2.0
-
-
µS
OE Setup Time
TOES
2.0
-
-
µS
Data Valid from OE
TOEV
-
-
150
nS
OE High to Output High Z
TDFP
0
-
130
nS
Address Hold Time after PGM High
TAH
0
-
-
µS
Address Hold Time (Erase)
TAHE
2.0
-
-
µS
CE Setup Time
TCES
2.0
-
-
µS
Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.
-7-
Publication Release Date: February 1999
Revision A1
Preliminary W27L010
TIMING WAVEFORMS
AC Read Waveform
VIH
Address
Address Valid
VIL
VIH
CE
VIL
TCE
VIH
TDF
OE
VIL
TOE
TOH
TACC
Outputs
High Z
Valid Output
High Z
Erase Waveform
Read
Manufacturer
Read
Device
SID
SID
A9 = 12.0V
VIL
Others = V IL
Others = VIL
VIH
Address
A0 = V IL
A0=V IH
Others=V IL
TAS
TAS
Data
DA
Blank Check
Read Verify
Erase Verify
Chip Erase
A9 = 14.0V
Address
Stable
Address
Stable
TAS
01
TAHC
Address
Stable
TACC
TDFP
DOUT
Data All One
TDS
DOUT
DOUT
T AH
TDH
14.0V
3.3V
5.0V
2.7V
TVPS
V PP
VIH
CE
TCE
VIL
TOE
TOES
TOE
TOE
VIH
OE
VIL
TCES
TPWE
PGM
-8-
TOEV
Preliminary W27L010
Timing Waveforms, Continued
Programming Waveform
Program
Verify
Program
Read
Verify
VIH
Address Stable
Address
Address Stable
Address Valid
VIL
TDFP
TAS
Data
Data In Stable
TDS
DOUT
TACC
DOUT
DOUT
TAH
TDH
12.0V
VPP
5.0V
VIH
5V
TVPS
TCES
CE
VIL
TOE
VIH
OE
VIL
VIH
PGM
TOES
TOEV
TPWP
VIL
-9-
Publication Release Date: February 1999
Revision A1
Preliminary W27L010
SMART PROGRAMMING ALGORITHM
Start
Address = First Location
Vcc = 5V
Vpp = 12V
X=0
Program One 100 µS Pulse
Increment X
Yes
X = 25?
No
Fail
Verify
One Byte
Verify
One Byte
Pass
Increment
Address
No
Fail
Pass
Last
Address?
Yes
Vcc = 3.3V
Vpp = 3.3V
Compare
All Bytes to
Original Data
Fail
Pass
Fail
Device
Pass
Device
- 10 -
Preliminary W27L010
SMART ERASE ALGORITHM
Start
X=0
Vcc = 5V
Vpp = 14V
A9 = 14V; A0 = V IL
Chip Erase 100 mS Pulse
Address = First Location
Increment X
Vcc = 2.7V
Vpp = 2.7V
No
Erase
Verify
Fail
X = 20?
Pass
Yes
Increment
Address
No
Last
Address?
Yes
Vcc = 3.3V
Vpp = 3.3V
Compare
All Bytes to
FFs (HEX)
Fail
Pass
Pass
Device
Fail
Device
- 11 -
Publication Release Date: February 1999
Revision A1
Preliminary W27L010
ORDERING INFORMATION
PART NO.
ACCESS
TIME
(nS)
POWER SUPPLY
CURRENT MAX.
(mA)
STANDBY VCC
CURRENT MAX.
(µA)
PACKAGE
W27L010-90
90
8
20
600 mil DIP
W27L010-12
120
8
20
600 mil DIP
W27L010S-90
90
8
20
450 mil SOP
W27L010S-12
120
8
20
450 mil SOP
W27L010P-90
90
8
20
32-pin PLCC
W27L010P-12
120
8
20
32-pin PLCC
Notes:
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in
applications where personal injury might occur as a consequence of product failure.
PACKAGE DIMENSIONS
32-pin P-DIP
Dimension in Inches
Symbol
A
A1
A2
B
B1
c
D
E
E1
e1
L
D
17
32
E1
a
eA
S
16
1
c
A A2
A1
L
Base Plane
Seating Plane
B
e1
a
B1
- 12 -
eA
0.210
0.010
5.33
0.25
0.150
0.155
0.160
3.81
3.94
4.06
0.016
0.018
0.022
0.41
0.46
0.56
0.048
0.050
0.054
1.22
1.27
1.37
0.008
0.010
0.014
0.20
0.25
0.36
0.590
1.650
1.660
41.91
42.16
0.600
0.610
14.99
15.24
15.49
0.545
0.550
0.555
13.84
13.97
14.10
0.090
0.100
0.110
2.29
2.54
2.79
0.120
0.130
0.140
3.05
3.30
3.56
15
0
0.670
16.00
16.51
17.02
0
0.630 0.650
0.085
15
2.16
Notes:
E
S
Dimension in mm
Min. Nom. Max. Min. Nom. Max.
1. Dimensions D Max. & S include mold flash or tie bar burrs.
2. Dimension E1 does not include interlead flash.
3. Dimensions D & E1 include mold mismatch and are
determined at the mold parting line.
4. Dimension B1 does not include dambar protrusion/intrusion.
5. Controlling dimension: Inches.
6. General appearance spec. should be based on final visual
inspection spec.
Preliminary W27L010
Package Dimensions, Continued
32-pin SO Wide Body
Dimension in Inches
Symbol
A
A1
A2
b
c
D
E
e
HE
L
LE
S
y
θ
17
32
e1
E HE
θ
L
Detail F
1
16
b
Min.
Nom.
Max.
Dimension in mm
Min.
Nom.
0.118
0.004
Max.
3.00
0.10
0.101
0.106
0.111
2.57
2.69
0.014
0.016
0.020
0.36
0.41
0.51
0.006
0.008
0.012
0.15
0.20
0.31
0.805
0.817
20.45
20.75
0.440
0.445
0.450
11.18
11.30
11.43
0.044
0.050
2.82
0.056
1.12
1.27
1.42
0.546
0.556
0.556
13.87
14.12
14.38
0.023
0.031
0.039
0.58
0.79
0.99
0.047
0.055
0.063
1.19
1.40
1.60
0.036
0.91
0.004
0.10
10
0
10
0
Notes:
1. Dimensions D Max. & S include mold flash
or tie bar burrs.
2. Dimension b does not include dambar
protrusion/intrusion.
3. Dimensions D & E include mold mismatch
. mold parting line.
and determined at the
4. Controlling dimension: Inches.
5. General appearance spec should be based
on final visual inspection spec.
e1
D
c
A
A2
S
e
y
LE
A1
See Detail F
Seating Plane
32-Lead PLCC
HE
E
4
1
32
30
Symbol
5
29
GD
D HD
21
13
14
c
20
A
A1
A2
b1
b
c
D
E
e
GD
GE
HD
HE
L
y
θ
Dimension in Inches
Min.
Nom.
Max.
Dimension in mm
Min.
Nom.
Max.
3.56
0.140
0.50
0.020
0.105
0.110
0.115
2.67
2.80
2.93
0.026
0.028
0.032
0.66
0.71
0.81
0.016
0.018
0.022
0.41
0.46
0.56
0.008
0.010
0.014
0.20
0.25
0.35
0.547
0.550
0.553
13.89
13.97
14.05
0.447
0.450
0.453
11.35
11.43
11.51
0.044
0.050
0.056
1.12
1.27
1.42
0.490
0.510
0.530
12.45
12.95
13.46
0.390
0.410
0.430
9.91
10.41
10.92
0.585
0.590
0.595
14.86
14.99
15.11
0.485
0.490
0.495
12.32
12.45
12.57
0.075
0.090
0.095
1.91
2.29
2.41
0.004
0°
10°
0.10
0°
10°
Notes:
L
A2
θ
e
b
b1
Seating Plane
A
1. Dimensions D & E do not include interlead flash.
2. Dimension b1 does not include dambar protrusion/intrusion.
3. Controlling dimension: Inches.
4. General appearance spec. should be based on final
visual inspection sepc.
A1
y
GE
- 13 -
Publication Release Date: February 1999
Revision A1
Preliminary W27L010
VERSION HISTORY
VERSION
DATE
A1
Feb. 1999
PAGE
DESCRIPTION
Initial Issued
Headquarters
Winbond Electronics (H.K.) Ltd.
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5792647
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-7197006
Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-7190505
FAX: 886-2-7197502
Note: All data and specifications are subject to change without notice.
- 14 -
Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
2730 Orchard Parkway, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-9436668