SN74AHC1G126 SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT SCLS379D – AUGUST 1997 – REVISED JANUARY 2000 D D D D EPIC (Enhanced-Performance Implanted CMOS) Process Operating Range 2-V to 5.5-V VCC Latch-Up Performance Exceeds 250 mA Per JESD 17 Package Options Include Plastic Small-Outline Transistor (DBV, DCK) Packages DBV OR DCK PACKAGE (TOP VIEW) OE A GND 1 5 VCC 4 Y 2 3 description The SN74AHC1G126 is a single bus buffer gate/line driver with 3-state output. The output is disabled when the output-enable (OE) input is low. When OE is high, true data is passed from the A input to the Y output. To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. The SN74AHC1G126 is characterized for operation from –40°C to 85°C. FUNCTION TABLE INPUTS OE A OUTPUT Y H H H H L L L X Z logic symbol† 1 OE EN 2 A 4 Y † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) OE A 1 2 4 Y Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74AHC1G126 SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT SCLS379D – AUGUST 1997 – REVISED JANUARY 2000 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347°C/W DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 3) VCC VIH Supply voltage VCC = 2 V VCC = 3 V High-level input voltage VCC = 5.5 V VCC = 2 V MIN MAX 2 5.5 UNIT V 1.5 V 2.1 3.85 0.5 VIL Low-level input voltage VI VO Input voltage 0 5.5 V Output voltage 0 VCC –50 V IOH High-level output current VCC = 3 V VCC = 5.5 V VCC = 2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V VCC = 2 V IOL ∆t/∆v Low-level output current Input transition rise or fall rate 0.9 V 1.65 –4 –8 50 VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V 4 VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V 100 8 20 mA mA mA mA ns/V TA Operating free-air temperature –40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74AHC1G126 SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT SCLS379D – AUGUST 1997 – REVISED JANUARY 2000 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –50 mA VOH IOH = –4 mA IOH = –8 mA IOL = 50 mA VOL IOL = 4 mA IOL = 8 mA II IOZ VI = VCC or GND VI = VCC or GND ICC Ci VI = VCC or GND, VI = VCC or GND Co VO = VCC or GND MIN TA = 25°C TYP MAX MIN 2V 1.9 2 1.9 3V 2.9 3 2.9 4.5 V 4.4 4.5 4.4 3V 2.58 4.5 V 3.94 VCC IO = 0 MAX UNIT V 2.48 3.8 2V 0.1 0.1 0.1 3V 0.1 4.5 V 0.1 0.1 3V 0.36 0.44 V 4.5 V 0.36 0.44 0 V to 5.5 V ±0.1 ±1 mA 5.5 V ±0.25 ±2.5 mA 5.5 V 1 10 mA 10 10 pF 5V 4 5V 10 pF switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE tPLH tPHL A Y CL = 15 pF tPZH tPZL OE Y CL = 15 pF tPHZ tPLZ OE Y CL = 15 pF tPLH tPHL A Y CL = 50 pF tPZH tPZL OE Y CL = 50 pF tPHZ tPLZ OE Y CL = 50 pF POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MIN TA = 25°C TYP MAX MIN MAX 5.6 8 1 9.5 5.6 8 1 9.5 5.4 8 1 9.5 5.4 8 1 9.5 7 9.7 1 11.5 7 9.7 1 11.5 8.1 11.5 1 13 8.1 11.5 1 13 7.9 11.5 1 13 7.9 11.5 1 13 9.5 13.2 1 15 9.5 13.2 1 15 UNIT ns ns ns ns ns ns 3 SN74AHC1G126 SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT SCLS379D – AUGUST 1997 – REVISED JANUARY 2000 switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE tPLH tPHL A Y CL = 15 pF tPZH tPZL OE Y CL = 15 pF tPHZ tPLZ OE Y CL = 15 pF tPLH tPHL A Y CL = 50 pF tPZH tPZL OE Y CL = 50 pF tPHZ tPLZ OE Y CL = 50 pF MIN TA = 25°C TYP MAX MIN MAX 3.8 5.5 1 6.5 3.8 5.5 1 6.5 3.6 5.1 1 6 3.6 5.1 1 6 4.6 6.8 1 8 4.6 6.8 1 8 5.3 7.5 1 8.5 5.3 7.5 1 8.5 5.1 7.1 1 8 5.1 7.1 1 8 6.1 8.8 1 10 6.1 8.8 1 10 UNIT ns ns ns ns ns ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd 4 TEST CONDITIONS Power dissipation capacitance No load, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 1 MHz TYP 14 UNIT pF SN74AHC1G126 SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT SCLS379D – AUGUST 1997 – REVISED JANUARY 2000 PARAMETER MEASUREMENT INFORMATION RL = 1 kΩ From Output Under Test Test Point From Output Under Test VCC Open S1 TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input tw tsu VCC Input 50% VCC 50% VCC 0V th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VCC 50% VCC Input 50% VCC 0V tPLH In-Phase Output tPHL 50% VCC tPHL Out-of-Phase Output VOH 50% VCC VOL Output Waveform 1 S1 at VCC (see Note B) VOH 50% VCC VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 50% VCC 50% VCC 0V tPZL tPLZ ≈VCC 50% VCC tPZH tPLH 50% VCC VCC Output Control Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 50% VCC VOH – 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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