SN54AHC540, SN74AHC540 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS260H – DECEMBER 1995 – REVISED JANUARY 2000 D D D D EPIC (Enhanced-Performance Implanted CMOS) Process Operating Range 2-V to 5.5-V VCC Latch-Up Performance Exceeds 250 mA Per JESD 17 Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Very Small-Outline (DGV), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) DIPs SN54AHC540 . . . J OR W PACKAGE SN74AHC540 . . . DB, DGV, DW, N, OR PW PACKAGE (TOP VIEW) OE1 A1 A2 A3 A4 A5 A6 A7 A8 GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC OE2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 description The ’AHC540 octal buffers/drivers are ideal for driving bus lines or buffer memory address registers. These devices feature inputs and outputs on opposite sides of the package to facilitate printed circuit board layout. A3 A4 A5 A6 A7 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 Y1 Y2 Y3 Y4 Y5 A8 GND Y8 Y7 Y6 The 3-state control gate is a two-input AND gate with active-low inputs so that if either output-enable (OE1 or OE2) input is high, all corresponding outputs are in the high-impedance state. The outputs provide inverted data when they are not in the high-impedance state. OE2 A2 A1 OE1 VCC SN54AHC540 . . . FK PACKAGE (TOP VIEW) To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54AHC540 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74AHC540 is characterized for operation from –40°C to 85°C. FUNCTION TABLE (each buffer/driver) INPUTS OE1 OE2 A OUTPUT Y L L L H L L H L H X X Z X H X Z Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54AHC540, SN74AHC540 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS260H – DECEMBER 1995 – REVISED JANUARY 2000 logic symbol† OE1 OE2 A1 A2 A3 A4 A5 A6 A7 A8 1 & 19 EN 2 18 1 3 17 4 16 5 15 6 14 7 13 8 12 9 11 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) OE1 OE2 A1 1 19 2 18 Y1 To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±75 mA Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54AHC540, SN74AHC540 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS260H – DECEMBER 1995 – REVISED JANUARY 2000 recommended operating conditions (see Note 3) SN54AHC540 VCC Supply voltage VIH VCC = 2 V VCC = 3 V High-level input voltage Low-level input voltage VI VO 2 5.5 Output voltage ∆t/∆v 5.5 2.1 V V 0.5 0.9 0.9 1.65 1.65 V 0 5.5 0 5.5 V 0 VCC –50 0 VCC –50 mA VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V VCC = 3.3 V ± 0.3 V Input transition rise or fall rate 2 UNIT 1.5 3.85 VCC = 2 V VCC = 3.3 V ± 0.3 V Low-level output current MAX 2.1 VCC = 5 V ± 0.5 V VCC = 2 V IOL MIN 3.85 VCC = 3 V VCC = 5.5 V High-level output current SN74AHC540 0.5 Input voltage IOH MAX 1.5 VCC = 5.5 V VCC = 2 V VIL MIN VCC = 5 V ± 0.5 V –4 –4 –8 –8 50 50 4 4 8 8 100 100 20 20 V mA mA mA ns/V TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER MIN TA = 25°C TYP MAX 2V 1.9 2 1.9 1.9 3V 2.9 3 2.9 2.9 4.5 V 4.4 4.5 4.4 4.4 IOH = –4 mA 3V 2.58 2.48 2.48 IOH = –8 mA 4.5 V 3.94 3.8 3.8 TEST CONDITIONS VCC IOH = –50 mA VOH IOL = 50 mA VOL IOL = 4 mA II IOL = 8 mA VI = VCC or GND IOZ† VO = VCC or GND, VI (OE) = VIL or VIH ICC Ci VI = VCC or GND, VI = VCC or GND IO = 0 SN54AHC540 MIN MAX SN74AHC540 MIN MAX UNIT V 2V 0.1 0.1 0.1 3V 0.1 0.1 0.1 4.5 V 0.1 0.1 0.1 3V 0.36 0.5 0.44 V 4.5 V 0.36 0.5 0.44 0 V to 5.5 V ±0.1 ±1* ±1 mA 5.5 V ±0.25 ±2.5 ±2.5 mA 4 40 40 mA 10 pF 5.5 V 5V 2 Co 10 VO = VCC or GND 5V 4 * On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V. † For I/O pins, the parameter IOZ includes the input leakage current. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 pF 3 SN54AHC540, SN74AHC540 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS260H – DECEMBER 1995 – REVISED JANUARY 2000 switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE tPLH tPHL A Y CL = 15 pF tPZH tPZL OE Y CL = 15 pF tPHZ tPLZ OE Y CL = 15 pF tPLH tPHL A Y CL = 50 pF tPZH tPZL OE Y CL = 50 pF tPHZ tPLZ OE Y CL = 50 pF MIN TA = 25°C TYP MAX SN54AHC540 SN74AHC540 MIN MAX MIN MAX 4.8* 7* 1* 8.5* 1 8.5 4.8* 7* 1* 8.5* 1 8.5 6.8* 10.5* 1* 12.5* 1 12.5 6.8* 10.5* 1* 12.5* 1 12.5 6.8* 10.5* 1* 12.5* 1 12.5 6.8* 10.5* 1* 12.5* 1 12.5 7.3 10.5 1 12 1 12 7.3 10.5 1 12 1 12 8 14 1 16 1 16 8 14 1 16 1 16 8 15.4 1 17.5 1 17.5 8 15.4 1 17.5 1 17.5 tsk(o) CL = 50 pF ∗ On products compliant to MIL-PRF-38535, this parameter is not production tested. ∗∗ On products compliant to MIL-PRF-38535, this parameter does not apply. 1.5** 1.5 UNIT ns ns ns ns ns ns ns switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE tPLH tPHL A Y CL = 15 pF tPZH tPZL OE Y CL = 15 pF tPHZ tPLZ OE Y CL = 15 pF tPLH tPHL A Y CL = 50 pF tPZH tPZL OE Y CL = 50 pF tPHZ tPLZ OE Y CL = 50 pF MIN TA = 25°C TYP MAX POST OFFICE BOX 655303 SN74AHC540 MIN MAX MIN MAX 3.7* 5* 1* 6* 1 6 3.7* 5* 1* 6* 1 6 4.7* 7.2* 1* 8.5* 1 8.5 4.7* 7.2* 1* 8.5* 1 8.5 4.5* 6.8* 1* 8* 1 8 4.5* 6.8* 1* 8* 1 8 5.2 7 1 8 1 8 5.2 7 1 8 1 8 6.2 9.2 1 10.5 1 10.5 6.2 9.2 1 10.5 1 10.5 6 8.8 1 10 1 10 6 8.8 1 10 1 10 tsk(o) CL = 50 pF ∗ On products compliant to MIL-PRF-38535, this parameter is not production tested. ∗∗ On products compliant to MIL-PRF-38535, this parameter does not apply. 4 SN54AHC540 • DALLAS, TEXAS 75265 1** 1 UNIT ns ns ns ns ns ns ns SN54AHC540, SN74AHC540 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS260H – DECEMBER 1995 – REVISED JANUARY 2000 noise characteristics, VCC = 5 V, CL = 50 pF, TA = 25°C (see Note 4) SN74AHC540 PARAMETER MIN MAX UNIT VOL(P) VOL(V) Quiet output, maximum dynamic VOL 0.8 V Quiet output, minimum dynamic VOL –0.8 V VOH(V) VIH(D) Quiet output, minimum dynamic VOH 4.7 High-level dynamic input voltage 3.5 VIL(D) Low-level dynamic input voltage NOTE 4: Characteristics are for surface-mount packages only. V V 1.5 V TYP UNIT operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance No load, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 1 MHz 12 pF 5 SN54AHC540, SN74AHC540 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS260H – DECEMBER 1995 – REVISED JANUARY 2000 PARAMETER MEASUREMENT INFORMATION RL = 1 kΩ From Output Under Test Test Point From Output Under Test VCC Open S1 TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input tw tsu VCC Input 50% VCC 50% VCC 0V th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VCC 50% VCC Input 50% VCC 0V tPLH In-Phase Output tPHL 50% VCC tPHL Out-of-Phase Output VOH 50% VCC VOL VCC Output Control Output Waveform 1 S1 at VCC (see Note B) 50% VCC 0V tPZL VOH 50% VCC VOL tPLZ ≈VCC 50% VCC tPZH tPLH 50% VCC 50% VCC Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOL + 0.3 V VOL tPHZ 50% VCC VOH – 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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