Recommended System Management Alternative: X4283 X24128 128K 16K x 8 Bit 400kHz 2-Wire Serial EEPROM with Block Lock™ FEATURES DESCRIPTION • Save critical data with programmable block lock protection —Block lock (0, 1/4, 1/2, or all of EEPROM array) —Software write protection —Programmable hardware write protect • In circuit programmable ROM mode • 400kHz 2-wire serial interface —Schmitt trigger input noise suppression —Output slope control for ground bounce noise elimination • Longer battery life with lower power —Active read current less than 1mA —Active write current less than 3mA —Standby current less than 1µA • 2.5V to 5.5V power supply version • 32 word page write mode —Minimizes total write time per word • Internally organized 16K x 8 • Bidirectional data transfer protocol • Self-timed write cycle —Typical write cycle time of 5ms • High reliability —Endurance: 100,000 cycles —Data retention: 100 years • 8-lead XBGA • 14-lead SOIC The X24128 is a CMOS Serial EEPROM, internally organized 16K x 8. The device features a serial interface and software protocol allowing operation on a simple two wire bus. Three device select inputs (S0–S2) allow up to eight devices to share a common two wire bus. A Write Protect Register at the highest address location, FFFFh, provides three write protection features: Software Write Protect, Block Lock Protect, and Programmable Hardware Write Protect. The software write protect feature prevents any nonvolatile writes to the device until the WEL bit in the write protect register is set. The Block Lock protection feature gives the user four array block protect options, set by programming two bits in the write protect register. The programmable hardware write protect feature allows the user to install the device with WP tied to VCC, write to and Block Lock the desired portions of the memory array in circuit, and then enable the In Circuit Programmable ROM Mode by programming the WPEN bit HIGH in the Write Protect Register. After this, the Block Locked portions of the array, including the Write Protect Register itself, are permanently protected from being erased. Xicor EEPROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years. BLOCK DIAGRAM Data Register Serial EEPROM Data and Address (SDA) SCL Y Decode Logic Command Decode and Control Logic Page Decode Logic 4k X 8 Block Lock and Write Protect Control Logic S2 S1 S0 4k X 8 Write Protect Register Device Select Logic 8k X 8 Write Voltage Control WP REV 1.1 9/8/00 Serial Eeprom Array 16k X 8 www.xicor.com Characteristics subject to change without notice. 1 of 16 X24128 PIN DESCRIPTIONS PIN CONFIGURATION Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. 8-Lead XBGA: Top View Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. S1 NC NC NC S2 VSS Device Select (S0, S1, S2) Write Protect (WP) The Write Protect input controls the Hardware Write Protect feature. When held LOW, Hardware Write Protection is disabled. When this input is held HIGH, and the WPEN bit in the Write Protect Register is set HIGH, the Write Protect Register is protected, preventing changes to the Block Lock protection and WPEN bits. PIN NAMES Symbol Description S0, S1, S2 Device Select Inputs SDA Serial Data SCL Serial Clock WP Write Protect VSS Ground VCC Supply Voltage NC No Connect REV 1.1 9/8/00 8 S1 VCC 2 7 S0 SDA 3 6 VSS SCL 4 5 S2 14 Lead SOIC S0 An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the Pullup resistor selection graph at the end of this data sheet. The device select inputs (S0, S1, S2) are used to set the first three bits of the 8-bit slave address. This allows up to eight devices to share a common bus. These inputs can be static or actively driven. If used statically they must be tied to VSS or VCC as appropriate. If actively driven, they must be driven with CMOS levels (driven to VCC or VSS). WP 1 1 2 3 4 5 6 7 14 13 12 X24128 11 10 9 8 VCC WP NC NC NC SCL SDA DEVICE OPERATION The device supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers, and provide the clock for both transmit and receive operations. Therefore, the device will be considered a slave in all applications. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figures 1 and 2. Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. www.xicor.com Characteristics subject to change without notice. 2 of 16 X24128 Figure 1. Data Validity SCL SDA Data Stable Data Change Figure 2. Definition of Start and Stop SCL SDA START Bit STOP Bit Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the device into the standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus. Acknowledge Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 3. REV 1.1 9/8/00 The device will respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write operation have been selected, the device will respond with an acknowledge after the receipt of each subsequent 8-bit word. In the read mode the device will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the device will continue to transmit data. If an acknowledge is not detected, the device will terminate further data transmissions. The master must then issue a stop condition to return the device to the standby power mode and place the device into a known state. www.xicor.com Characteristics subject to change without notice. 3 of 16 X24128 Figure 3. Acknowledge Response From Receiver SCL from Master 1 8 9 Data Output from Transmitter Data Output from Receiver START Acknowledge DEVICE ADDRESSING Figure 4. Device Addressing Following a start condition, the master must output the address of the slave it is accessing. The first four bits of the Slave Address Byte are the device type identifier bits. These must equal “1010”. The next 3 bits are the device select bits S0, S1, and S2. This allows up to 8 devices to share a single bus. These bits are compared to the S0, S1, and S2 device select input pins. The last bit of the Slave Address Byte defines the operation to be performed. When the R/W bit is a one, then a read operation is selected. When it is zero then a write operation is selected. Refer to Figure 4. After loading the Slave Address Byte from the SDA bus, the device compares the device type bits with the value “1010” and the device select bits with the status of the device select input pins. If the compare is not successful, no acknowledge is output during the ninth clock cycle and the device returns to the standby mode. The word address is either supplied by the master or obtained from an internal counter, depending on the operation. The master must supply the two Word Address Bytes as shown in Figure 4. The internal organization of the E2 array is 512 pages by 32 bytes per page. The page address is partially contained in the Word Address Byte 1 and partially in bits 7 through 5 of the Word Address Byte 0. The byte address is contained in bits 4 through 0 of the Word Address Byte 0. See Figure 4. REV 1.1 9/8/00 www.xicor.com Device Type Identifier 1 0 1 Device Select 0 S2 S1 S0 R/W Slave Address Byte High Order Word Address 0 0 A13 A12 A11 A10 A9 A8 X24128 Word Address Byte 1 Low Order Word Address A7 A6 A5 A4 A3 A2 A1 A0 D1 D0 Word Address Byte 0 D7 D6 D5 D4 D3 D2 Data Byte Characteristics subject to change without notice. 4 of 16 X24128 WRITE OPERATIONS Byte Write For a write operation, the device requires the Slave Address Byte, the Word Address Byte 1, and the Word Address Byte 0, which gives the master access to any one of the words in the array. Upon receipt of the Word Address Byte 0, the device responds with an acknowledge, and waits for the first eight bits of data. After receiving the 8 bits of the data byte, the device again responds with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the device begins the internal write cycle to the nonvolatile memory. While the internal write cycle is in progress the device inputs are disabled and the device will not respond to any requests from the master. The SDA pin is at high impedance. See Figure 5. Page Write The device is capable of a thirty-two byte page write operation. It is initiated in the same manner as the byte write operation; but instead of terminating the write operation after the first data word is transferred, the master can transmit up to thirty-one more words. The device will respond with an acknowledge after the receipt of each word, and then the byte address is internally incremented by one. The page address remains constant. When the counter reaches the end of the page, it “rolls over” and goes back to the first byte of the current page. This means that the master can write 32 words to the page beginning at any byte. If the master begins writing at byte 16, and loads 32 words, then the first 16 words are written to bytes 16 through 31, and the last 16 words are written to bytes 0 through 15. Afterwards, the address counter would point to byte 16. If the master writes more than 32 words, then the previously loaded data is overwritten by the new data, one byte at a time. The master terminates the data byte loading by issuing a stop condition, which causes the device to begin the nonvolatile write cycle. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. Refer to Figure 6 for the address, acknowledge, and data transfer sequence. Figure 5. Byte Write Sequence Signals from the Master SDA Bus S T A R T Word Address Byte 1 Slave Address S1010 S T O P Data 0 P A C K Signals from the Slave Word Address Byte 0 A C K A C K A C K Figure 6. Page Write Sequence (0 ≤ n ≤ 31) Signals from the Master SDA Bus Signals from the Slave REV 1.1 9/8/00 S T A R T Word Address Byte 1 Slave Address S 1010 Word Address Byte 0 Data (0) Data (n) S T O P P 0 A C K A C K www.xicor.com A C K A C K A C K Characteristics subject to change without notice. 5 of 16 X24128 Acknowledge Polling The maximum write cycle time can be significantly reduced using Acknowledge Polling. To initiate Acknowledge Polling, the master issues a start condition followed by the Slave Address Byte for a write or read operation. If the device is still busy with the internal write cycle, then no ACK will be returned. If the device has completed the internal write operation, an ACK will be returned, and the host can then proceed with the read or write operation. Refer to Figure 7. Figure 7. Acknowledge Polling Sequence Byte LoAd Completed By Issuing Stop. Enter ACK Polling Issue Slave Address Byte (Read or Write) Issue STOP No Yes High Voltage Cycle Complete. Continue Sequence? Current Address Read Internally, the device contains an address counter that maintains the address of the last word read or written incremented by one. After a read operation from the last address in the array, the counter will “roll over” to the first address in the array. After a write operation to the last address in a given page, the counter will “roll over” to the first address on the same page. It should be noted that the ninth clock cycle of the read operation is not a “don’t care.” To terminate a read operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during the ninth clock cycle and then issue a stop condition. Figure 8. Current Address Read Sequence Signals from the Master No SDA Bus Yes Continue Normal Read or Write Command Sequence Read operations are initiated in the same manner as write operations with the exception that the R/W bit of the Slave Address Byte is set to one. There are three basic read operations: Current Address Reads, Random Reads, and Sequential Reads. Upon receipt of the Slave Address Byte with the R/W bit set to one, the device issues an acknowledge and then transmits the eight bits of the Data Byte. The master terminates the read operation when it does not respond with an acknowledge during the ninth clock, and then issues a stop condition. Refer to Figure 8 for the address, acknowledge, and data transfer sequence. Issue START ACK Returned? READ OPERATIONS Signals from the Slave S T A R T S T O P Slave Address S 1 0 1 0 1 P A C K Data Issue STOP PROCEED REV 1.1 9/8/00 www.xicor.com Characteristics subject to change without notice. 6 of 16 X24128 Random Read Random read operation allows the master to access any memory location in the array. Prior to issuing the Slave Address Byte with the R/W bit set to one, the master must first perform a “Dummy” write operation. The master issues the start condition and the Slave Address Byte with the R/W bit low, receives an acknowledge, then issues the Word Address Byte 1, receives another acknowledge, then issues the Word Address Byte 0. After the device acknowledges receipt of the Word Address Byte 0, the master issues another start condition and the Slave Address Byte with the R/ W bit set to one. This is followed by an acknowledge and then eight bits of data from the device. The master terminates the read operation by not responding with an acknowledge, and then issuing a stop condition. Refer to Figure 9 for the address, acknowledge, and data transfer sequence. The device will perform a similar operation called “Set Current Address” if a stop is issued instead of the second start shown in Figure 9. The device will go into standby mode after the stop and all bus activity will be ignored until a start is detected. The effect of this operation is that the new address is loaded into the address counter, but no data is output by the device. The next Current Address Read operation will read from the newly loaded address. Sequential Read Sequential reads can be initiated as either a current address read or random read. The first Data Byte is transmitted as with the other modes; however, the master now responds with an acknowledge, indicating it requires additional data. The device continues to output data for each acknowledge received. The master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. The data output is sequential, with the data from address n followed by the data from address n + 1. The address counter for read operations increments through all byte addresses, allowing the entire memory contents to be read during one operation. At the end of the address space the counter “rolls over” to address 0000h, and the device continues to output data for each acknowledge received. Refer to Figure 10 for the acknowledge and data transfer sequence. Figure 9. Random Read Sequence Signals from the Master SDA Bus S T A R T Word Address Byte 1 Slave Address S 1 0 1 0 S T A R T Word Address Byte 0 0 S T O P 1 S A C K Signals from the Slave Slave Address A C K A C K P A C K Data Figure 10. Sequential Read Sequence Signals from the Master SDA Bus Signals from the Slave Slave Address S A C K A C K S T O P A C K 1 P A C K Data (1) Data (2) Data (n–1) Data (n) (n is any integer greater than 1) REV 1.1 9/8/00 www.xicor.com Characteristics subject to change without notice. 7 of 16 X24128 WRITE PROTECT REGISTER (WPR) Writing to the Write Protect Register The Write Protect Register can only be modified by performing a “Byte Write” operation directly to the address FFFFh as described below. The Data Byte must contain zeroes where indicated in the procedural descriptions below; otherwise the operation will not be performed. Only one Data Byte is allowed for each register write operation. The part will not acknowledge any data bytes after the first byte is entered. The user then has to issue a stop to initiate the nonvolatile write cycle that writes BL0, BL1, and WPEN to the nonvolatile bits. A stop must also be issued after volatile register write operations to put the device into Standby. The state of the Write Protect Register can be read by performing a random byte read at FFFFh at any time. The part will reset itself after the first byte is read. The master should supply a stop condition to be consistent with the protocol, but a stop is not required to end this operation. After the read, the address counter contains 0000h. BL0, BL1: Block Lock Protect Bits (Nonvolatile) The Block Lock Protect Bits, BL0 and BL1, determine which blocks of the array are protected. A write to a protected block of memory is ignored, but will receive an acknowledge. The master must issue a stop to put the part into standby, just as it would for a valid write; but the stop will not initiate an internal nonvolatile write cycle. See Table 1. WPEN: Write Protect Enable Bit (Nonvolatile) The Write Protect (WP) pin and the Write Protect Enable (WPEN) bit in the Write Protect Register control the Programmable Hardware Write Protection feature. Hardware Write Protection is enabled when the WP pin is HIGH and the WPEN bit is HIGH, and disabled when either the WP pin is LOW or the WPEN bit is LOW. Figure 12 defines the write protect status for each combination of WPEN and WP. When the chip is Hardware Write Protected, nonvolatile writes are disabled to the Write Protect Register, including the Block Lock protect bits and the WPEN bit itself, as well as to the Block Lock protected sections in the memory array. Only the sections of the memory array that are not Block Lock protected, and the volatile bits WEL and RWEL, can be written. Write Protect Register: WPR (ADDR = FFFFh) 7 6 5 4 WPEN 0 0 BL1 3 2 1 BL0 RWEL WEL 0 0 WEL: Write Enable Latch (Volatile) 0 = Write Enable Latch reset, writes disabled. 1 = Write Enable Latch set, writes enabled. RWEL: Register Write Enable Latch (Volatile) 0 = Register Write Enable Latch reset, writes to the Write Protect Register disabled. 1 = Register Write Enable Latch set, writes to the Write Protect Register enabled. REV 1.1 9/8/00 In Circuit Programmable ROM Mode Note that when the WPEN bit is write protected, it cannot be changed back to a LOW state; so write protection is enabled as long as the WP pin is held HIGH. Thus an In Circuit Programmable ROM function can be implemented by hardwiring the WP pin to VCC, writing to and Block Locking the desired portion of the array to be ROM, and then programming the WPEN bit HIGH. Unused Bit Positions Bits 0, 5 & 6 are not used. All writes to the WPR must have zeros in these bit positions. The data byte output during a WPR read will contain zeros in these bits. www.xicor.com Characteristics subject to change without notice. 8 of 16 X24128 Table 1. Block Lock Protect Bits and Protected Addresses BL1 BL0 Protected Addresses Array Location 0 0 None No Protect 0 1 3000h–3FFFh Upper 1/4 1 0 2000h–3FFFh Upper 1/2 1 1 0000h–3FFFh Full Array Table 2. WP Pin and WPEN Bit Functionality WP WPEN Memory Array Not Lock Block Protected Memory Array Block Lock Protected Block Lock Bits WPEN Bit 0 X Unprotected Protected Unprotected Unprotected X 0 Unprotected Protected Unprotected Unprotected 1 1 Unprotected Protected Protected Protected Writing to the WEL and RWEL bits WEL and RWEL are volatile latches that power up in the LOW (disabled) state. While the WEL bit is LOW, writes to any address other than FFFFh will be ignored (no acknowledge will be issued after the Data Byte). The WEL bit is set by writing 00000010 to address FFFFh. Once set, WEL remains HIGH until either it is reset to 0 (by writing 00000000 to FFFFh) or until the part powers up again. Writes to WEL and RWEL do not cause a nonvolatile write cycle, so the device is ready for the next operation immediately after the stop condition. The RWEL bit controls writes to the Block Lock protect bits, BL0 and BL1, and the WPEN bit. If RWEL is 0 then no writes can be performed on BL0, BL1, or WPEN. RWEL is reset when the device powers up or after any nonvolatile write, including writes to the Block Lock protect bits, WPEN bit, or any bytes in the memory array. When RWEL is set, WEL cannot be reset, nor can RWEL and WEL be reset in one write operation. RWEL can be reset by writing 00000010 to FFFFh; but this is the same operation as in step 3 described below, and will result in programing BL0, BL1, and WPEN. Writing to the BL and WPEN Bits A 3 step sequence is required to change the nonvolatile Block Lock protect or Write Protect Enable bits: 3) Set BL1, BL0, and/or WPEN bits, Write u00xy010 to address FFFFh, where u = WPEN, x = BL1, and y = BL0. (Nonvolatile Write Cycle.) The three step sequence was created to make it difficult to change the contents of the Write Protect Register accidentally. If WEL was set to one by a previous register write operation, the user may start at step 2. RWEL is reset to zero in step 3 so that user is required to perform steps 2 and 3 to make another change. RWEL must be 0 in step 3. If the RWEL bit in the data byte for step 3 is a one, then no changes are made to the Write Protect Register and the device remains at step 2. The WP pin must be LOW or the WPEN bit must be LOW before a nonvolatile register write operation is initiated. Otherwise, the write operation will abort and the device will go into standby mode after the master issues the stop condition in step 3. Step 3 is a nonvolatile write operation, requiring tWC to complete (acknowledge polling may be used to reduce this time requirement). It should be noted that step 3 MUST end with a stop condition. If a start condition is issued during or at the end of step 3 (instead of a stop condition) the device will abort the nonvolatile register write and remain at step 2. If the operation is aborted with a start condition, the master must issue a stop to put the device into standby mode. 1) Set WEL = 1, Write 00000010 to address FFFFh (Volatile Write Cycle.) 2) Set RWEL = 1, Write 00000110 to address FFFFh (Volatile Write Cycle.) REV 1.1 9/8/00 www.xicor.com Characteristics subject to change without notice. 9 of 16 X24128 ABSOLUTE MAXIMUM RATINGS COMMENT Temperature under bias ....................–65°C to +135°C Storage temperature .........................–65°C to +150°C Voltage on any pin with respect to VSS ....... –1V to +7V D.C. output current ............................................... 5mA Lead temperature (soldering, 10 seconds).........300°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those indicated in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Supply Voltage Limits Commercial 0°C +70°C X24128–2.5 2.5V to 5.5V Industrial –40°C +85°C D.C. OPERATING CHARACTERISTICS Limits Symbol Parameter ICC1 ICC2 Max. Unit VCC supply current (Read) 1 mA VCC supply current (Write) 3 mA ISB1(1) VCC standby current 5 µA SCL = SDA = VCC, All Other Inputs = VSS or VCC – 0.3V, VCC = 5V ± 10% ISB2(1) VCC standby current 1 µA SCL = SDA = VCC, All Other Inputs = VSS or VCC – 0.3V, VCC = 2.5V ILI Input leakage current 10 µA VIN = VSS to VCC ILO Output leakage current 10 µA VOUT = VSS to VCC (2) Min. VlL Input LOW voltage –0.5 VCC x 0.3 V VIH(2) Input HIGH voltage VCC x 0.7 VCC + 0.5 V VOL Output LOW voltage 0.4 V (3) Vhys Hysteresis of Schmitt trigger inputs VCC x 0.05 Test Conditions SCL = VCC X 0.1/VCC X 0.9 Levels @ 400kHz, SDA = Open, All Other Inputs = VSS or VCC – 0.3V IOL = 3mA V CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V Symbol (3) (3) CI/O CIN Parameter Max. Unit Test Conditions Input/output capacitance (SDA) 8 pF VI/O = 0V Input capacitance (S0, S1, S2, SCL, WP) 6 pF VIN = 0V Notes: (1) Must perform a stop command prior to measurement. (2) VIL min. and VIH max. are for reference only and are not 100% tested. (3) This parameter is periodically sampled and not 100% tested. REV 1.1 9/8/00 www.xicor.com Characteristics subject to change without notice. 10 of 16 X24128 A.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.) Read & Write Cycle Limits Symbol Min. Max. Unit SCL clock frequency 0 400 kHz Noise suppression time constant at SCL, SDA inputs 50 tAA SCL LOW to SDA Data out valid 0.1 tBUF Time the bus must be free before a new transmission can start 1.2 µs Start condition hold time 0.6 µs tLOW Clock LOW period 1.2 µs tHIGH Clock HIGH period 0.6 µs tSU:STA Start condition setup time (for a repeated start condition) 0.6 µs tHD:DAT Data In hold time 0 µs tSU:DAT Data In setup time 100 ns fSCL tI tHD:STA ns 0.9 µs tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU:STO tDH tOF Note: Parameter Stop Condition setup time 0.6 Data out hold time 50 µs (4) Output fall time 20+0.1Cb 300 ns 250 µs (4) Cb = Total capacitance of one bus line in pF POWER-UP TIMING(5) Symbol Parameter Max. Unit tPUR Power-up to read operation 1 ms tPUW Power-up to write operation 5 ms Notes: (5) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested. (6) Typical values are for TA = 25°C and nominal supply voltage (5V). A.C. CONDITIONS OF TEST EQUIVALENT A.C. LOAD CIRCUIT Input pulse levels VCC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing levels VCC X 0.5 5V 1.53KΩ Output 100pF REV 1.1 9/8/00 www.xicor.com Characteristics subject to change without notice. 11 of 16 X24128 Bus Timing tF tHIGH tLOW tHD:STA tHD:DAT tR SCL tSU:STA tSU:DAT tSU:STO SDA IN tDH tAA tBUF SDA OUT Write Cycle Limits Symbol (8) TWC Parameter Min. Write Cycle Time Typ.(7) Max. Unit 5 10 ms Notes: (7) Typical values are for TA = 25°C and nominal supply voltage (5V). (8) tWR is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to automatically complete the internal write operation. The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/write cycle. During the write cycle, the X24128 bus interface circuits are disabled, SDA is allowed to remain HIGH, and the device does not respond to its slave address. Bus Timing SCL SDA 8th Bit ACK Word n tWR STOP Condition REV 1.1 9/8/00 www.xicor.com START Condition Characteristics subject to change without notice. 12 of 16 X24128 Guidelines for Calculating Typical Values of Bus Pull-Up Resistors SYMBOL TABLE WAVEFORM 120 V RMin. = CC Max. =1.8KΩ IOL Min. Resistance (KΩ) 100 tR CBUS 80 RMAX.= 60 Max. Resistance 40 20 Min. Resistance 0 0 20 40 60 80 100 120 Bus Capacitance (pF) REV 1.1 9/8/00 www.xicor.com INPUTS OUTPUTS Must be steady Will be steady May change from Low to High Will change from Low to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed N/A Changing: State Not Known Center Line is High Impedance Characteristics subject to change without notice. 13 of 16 X24128 PACKAGING INFORMATION 8-Lead XBGA 8-Lead XBGA Complete Part Number Top Mark X24128Z-2.5 X24128ZI-2.5 XAAB XAAE 8-Lead XBGA: Top View .084” VCC 2 7 SO SDA 3 6 VSS SCL 4 5 S2 .259” WP S1 Pin 1 1000 ± 30 S0 VCC VSS SDA S2 SCL 6588 ± 30 S1 6588 ± 30 8 350 ± 20 1 500 ± 20 WP 215 ± 30 X24128: Bottom View 1200 ± 30 430 ± 50 2143 ± 30 2029 ± 30 215 ± 30 350 ± 20 NOTES: ALL DIMENSIONS IN µM (to convert to inches, 1µm = 3.94 x 10-5 inch) ALL DIMENSIONS ARE TYPICAL VALUES REV 1.1 9/8/00 www.xicor.com Characteristics subject to change without notice. 14 of 16 X24128 PACKAGING INFORMATION 14-Lead Plastic Small Outline Gullwing Package Type S 0.150 (3.80) 0.228 (5.80) 0.158 (4.00) 0.244 (6.20) Pin 1 Index Pin 1 0.014 (0.35) 0.020 (0.51) 0.336 (8.55) 0.345 (8.75) (4X) 7° 0.053 (1.35) 0.069 (1.75) 0.004 (0.10) 0.010 (0.25) 0.050 (1.27) 0.050"Typical 0.010 (0.25) 0.020 (0.50) X 45° 0.050"Typical 0° – 8° 0.0075 (0.19) 0.010 (0.25) 0.250" 0.016 (0.410) 0.037 (0.937) 0.030"Typical 14 Places FOOTPRINT NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) REV 1.1 9/8/00 www.xicor.com Characteristics subject to change without notice. 15 of 16 X24128 Ordering Information X24128 X X -X VCC Range 2.5 = 2.5V to 5.5V Device Temperature Range Blank = 0°C to +70°C I = –40°C to +85°C Package X24128 Z = 8-Lead XBGA S14 = 14-Lead SOIC Part Mark Convention 8-Lead XBGA Package 8 and 14-Lead PDIP/SOIC Complete Part Number Top Mark X24128 X24128Z - 2.5 XAAE XAAB X24128ZI - 2.5 X S14 = 14-Lead SOIC X AE = 2.5V to 5.5V, 0 to +70°C AF = 2.5V to 5.5V, –40 to +85°C LIMITED WARRANTY ©Xicor, Inc. 2000 Patents Pending Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. TRADEMARK DISCLAIMER: Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All others belong to their respective owners. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor’s products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. REV 1.1 9/8/00 www.xicor.com Characteristics subject to change without notice. 16 of 16