APPLICATION NOTES AND DEVELOPMENT SYSTEM
A V A I L A B L E
AN99 • AN115 • AN124 •AN133 • AN134 • AN135
Single Supply / Low Power / 256-tap / 2-Wire Bus
X9279
Single Digitally-Controlled (XDCPTM) Potentiometer
FEATURES
DESCRIPTION
• 256 Resistor Taps
• 2-Wire Serial Interface for write, read, and
transfer operations of the potentiometer
• Wiper Resistance, 100Ω typical @ 5V
• 16 Nonvolatile Data Registers for Each
Potentiometer
• Nonvolatile Storage of Multiple Wiper Positions
• Power On Recall. Loads Saved Wiper Position on
Power Up.
• Standby Current < 5µA Max
• VCC: 2.7V to 5.5V Operation
• 50KΩ, 100KΩ versions of End to End Resistance
• Endurance: 100,000 Data Changes per Bit per
Register
• 100 yr. Data Retention
• 14-Lead TSSOP, 16-Lead CSP (Chip Scale
Package)
• Low Power CMOS
The X9279 integrates a single digitally controlled
potentiometer (XDCP) on a monolithic CMOS
integrated circuit.
The digital controlled potentiometer is implemented
using 255 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the 2-Wire
bus interface. The potentiometer has associated with it
a volatile Wiper Counter Register (WCR) and a four
nonvolatile Data Registers that can be directly written
to and read by the user. The contents of the WCR
controls the position of the wiper on the resistor array
though the switches. Powerup recalls the contents of
the default data register (DR0) to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
FUNCTIONAL DIAGRAM
VCC
2-Wire
Bus
Interface
Address
Data
Status
RH
Write
Read
Transfer
Inc/Dec
Power On Recall
Wiper Counter
Register (WCR)
Bus
Interface
and Control
Control
50KΩ and 100KΩ
256-taps
POT
Data Registers
16 Bytes
RW
VSS
REV 1.1.7 2/6/03
wiper
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RL
Characteristics subject to change without notice.
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X9279
DETAILED FUNCTIONAL DIAGRAM
VCC
Bank 0
DR0 DR1
SCL
SDA
A2
A1
DR2 DR3
INTERFACE
AND
CONTROL
CIRCUITRY
A0
Power On Recall
RH
WIPER
50KΩ and 100KΩ
256-taps
COUNTER
REGISTER
(WCR)
RL
RW
DATA
WP
Bank 1
Bank 2
Bank 3
DR0 DR1
DR0 DR1
DR0 DR1
DR2 DR3
DR2 DR3
DR2 DR3
Control
12 additional nonvolatile registers
3 Banks of 4 registers x 8-bits
VSS
CIRCUIT LEVEL APPLICATIONS
SYSTEM LEVEL APPLICATIONS
• Vary the gain of a voltage amplifier
• Adjust the contrast in LCD displays
• Provide programmable dc reference voltages for
comparators and detectors
• Control the power level of LED transmitters in
communication systems
• Control the volume in audio circuits
• Set and regulate the DC biasing point in an RF power
amplifier in wireless systems
• Trim out the offset voltage error in a voltage amplifier
circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and
Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the dc biasing of a pin diode attenuator in RF
circuits
• Control the gain in audio and home entertainment
systems
• Provide the variable DC bias for tuners in RF wireless
systems
• Set the operating points in temperature control
systems
• Control the operating point for sensors in industrial
systems
• Trim offset and gain errors in artificial intelligent
systems
• Provide a control variable (I, V, or R) in feedback
circuits
REV 1.1.7 2/6/03
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Characteristics subject to change without notice.
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X9279
PIN CONFIGURATION
CSP
TSSOP
NC
A0
NC
A2
SCL
SDA
VSS
14
1
X9279
13
2
3
12
4
11
5
10
6
9
8
7
VCC
RL
RH
RW
A3
A1
WP
4
3
2
1
A
A0
VCC
RL
RH
B
A2
NC
NC
RW
C
SCL
NC
NC
A3
D
SDA VSS
WP
A1
PIN ASSIGNMENTS
Pin
TSSOP
Pin
CSP
Symbol
1
B2, B3
NC
No Connect
2
A4
A0
Device Address for 2-Wire bus.
3
C2, C3
NC
No Connect
Function
4
B4
A2
5
C4
SCL
Serial Clock for 2-Wire bus.
6
D4
SDA
Serial Data Input/Output for 2-Wire bus.
7
D3
VSS
System Ground.
8
D2
WP
Hardware Write Protect
9
D1
A1
Device Address for 2-Wire bus.
10
C1
A3
Device Address for 2 wire-bus.
11
B1
RW
Wiper Terminal of the Potentiometer.
12
A1
RH
High Terminal of the Potentiometer.
13
A2
RL
Low Terminal of the Potentiometer.
14
A3
VCC
REV 1.1.7 2/6/03
Device Address for 2-Wire bus.
System Supply Voltage.
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Characteristics subject to change without notice.
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X9279
PIN DESCRIPTIONS
Potentiometer Pins
Bus Interface Pins
RH, RL
SERIAL DATA INPUT/OUTPUT (SDA)
The RH and RL pins are equivalent to the terminal
connections on a mechanical potentiometer.
The SDA is a bidirectional serial data input/output pin
for a 2-Wire slave device and is used to transfer data
into and out of the device. It receives device address,
opcode, wiper register address and data sent from an
2-Wire master at the rising edge of the serial clock
SCL, and it shifts out data after each falling edge of the
serial clock SCL.
It is an open drain output and may be wire-ORed with
any number of open drain or open collector outputs. An
open drain output requires the use of a pull-up resistor.
For selecting typical values, refer to the guidelines for
calculating typical values on the bus pull-up resistors
graph.
The wiper pin is equivalent to the wiper terminal of a
mechanical potentiometer.
Bias Supply Pins
SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY GROUND (VSS)
The VCC pin is the system supply voltage. The VSS pin
is the system ground.
Other Pins
NO CONNECT
SERIAL CLOCK (SCL)
This input is used by 2-Wire master to supply 2-Wire
serial clock to the X9279.
No connect pins should be left open. This pins are used
for Xicor manufacturing and testing purposes.
HARDWARE WRITE PROTECT INPUT (WP)
DEVICE ADDRESS (A2 - A0)
The Address inputs are used to set the least significant
3 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
Address input in order to initiate communication with
the X9279. A maximum of 8 devices may occupy the 2Wire serial bus.
REV 1.1.7 2/6/03
RW
The WP pin when LOW prevents nonvolatile writes to
the Data Registers.
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Characteristics subject to change without notice.
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X9279
PRINCIPLES OF OPERATION
The X9279 is a integrated microcircuit incorporating a
resistor array and associated registers and counter
and the serial interface logic providing direct
communication between the host and the digitally
controlled potentiometers. This section provides detail
description of the following:
– Resistor Array Description.
– Serial Interface Description.
– Instruction and Register Description.
Array Description
The X9279 is comprised of a resistor array (see Figure
1). The array contains, in effect, 255 discrete resistive
segments that are connected in series. The physical
ends of each array are equivalent to the fixed terminals
of a mechanical potentiometer (RH and RL inputs).
These switches are controlled by a Wiper Counter
Register (WCR). The 8-bits of the WCR (WCR[7:0])
are decoded to select, and enable, one of 256 switches
(see Table 1).
The WCR may be written directly. These Data
Registers can the WCR can be read and written by the
host system.
Power Up and Down Recommendations.
There are no restrictions on the power-up or powerdown conditions of VCC and the voltages applied to the
potentiometer pins provided that VCC is always more
positive than or equal to VH, VL, and VW, i.e., VCC ≥ VH,
VL, VW. The VCC ramp rate specification is always in
effect.
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(RW) output. Within each individual array only one
switch may be turned on at a time.
Figure 1. Detailed Potentiometer Block Diagram
SERIAL
BUS
INPUT
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY
REGISTER 0
(DR0)
8
BANK_0 Only
IF WCR = 00[H] THEN RW = RL
IF WCR = FF[H] THEN RW = RH
C
O
U
N
T
E
R
REGISTER 1
(DR1)
8
REGISTER 2
(DR2)
RH
REGISTER 3
(DR3)
PARALLEL
BUS
INPUT
WIPER
COUNTER
REGISTER
(WCR)
D
E
C
O
D
E
INC/DEC
LOGIC
UP/DN
MODIFIED SCK
UP/DN
CLK
RL
RW
REV 1.1.7 2/6/03
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Characteristics subject to change without notice.
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X9279
SERIAL INTERFACE DESCRIPTION
Serial Interface
The X9279 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9279 will be considered a
slave device in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW periods. SDA state changes during SCL
HIGH are reserved for indicating start and stop
conditions. See Figure 2.
Start Condition
All commands to the X9279 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH. The X9279 continuously monitors
the SDA and SCL lines for the start condition and will
not respond to any command until this condition is
met. See Figure 2.
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH. See Figure 2.
Acknowledge
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.
The X9279 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9279 will respond with a final acknowledge.
See Figure 2.
Figure 2. Acknowledge Response from Receiver
SCL FROM
MASTER
1
8
9
DATA
OUTPUT
FROM
TRANSMITTER
DATA
OUTPUT
FROM
RECEIVER
START
REV 1.1.7 2/6/03
ACKNOWLEDGE
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Characteristics subject to change without notice.
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X9279
Acknowledge Polling
The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical 5ms EEPROM write cycle
time. Once the stop condition is issued to indicate the
end of the nonvolatile write command the X9279
initiates the internal write cycle. ACK polling, Flow 1,
can be initiated immediately. This involves issuing the
start condition followed by the device slave address. If
the X9279 is still busy with the write operation no ACK
will be returned. If the X9279 has completed the write
operation an ACK will be returned and the master can
then proceed with the next operation.
FLOW 1: ACK Polling Sequence
Nonvolatile Write
Command Completed
EnterACK Polling
Issue
START
Issue Slave
Address
ACK
Returned?
Issue STOP
No
INSTRUCTION AND REGISTER DESCRIPTION
Device Addressing: Identification Byte ( ID and A)
The first byte sent to the X9279 from the host, following
a CS going HIGH to LOW, is called the Identification
byte. The most significant four bits of the slave address
are a device type identifier. The ID[3:0] bits is the
device ID for the X9279; this is fixed as 0101[B] (refer
to Table 1).
The A[2:0] bits in the ID byte is the internal slave
address. The physical device address is defined by the
state of the A2-A0 input pins. The slave address is
externally specified by the user. The X9279 compares
the serial data stream with the address input state; a
successful compare of both address bits is required for
the X9279 to successfully continue the command
sequence. Only the device which slave address
matches the incoming device address sent by the
master executes the instruction. The A2-A0 inputs can
be actively driven by CMOS input signals or tied to VCC
or VSS.
Instruction Byte (I)
The next byte sent to the X9279 contains the
instruction and register pointer information. The three
most significant bits are used provide the instruction
opcode I [2:0]. The RB and RA bits point to one of the
four Data Registers. P0 is the POT selection; since the
X9279 is single POT, the P0=0. The format is shown in
Table 2.
Yes
Further
Operation?
Register Bank Selection (RB, RA, P1, P0)
There are 16 registers organized into four banks. Bank
0 is the default bank of registers. Only Bank 0 registers
can be used for Data Register to Wiper Counter
Register operations.
No
Yes
Issue
Instruction
Issue STOP
Proceed
Proceed
REV 1.1.7 2/6/03
Banks 1, 2, and 3 are additional banks of registers (12
total) that can be used for 2-Wire write and read
operations. The Data Registers in Banks 1, 2, and 3
cannot be used for direct read/write operations
between the Wiper Counter Register.
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X9279
Register Selection (R0 to R3) Table
Register
RB RA Selection
0
0
0
0
1
1
1
0
2
1
1
3
Register Bank Selection (Bank 0 to Bank 3) Table
Bank
P0 Selection
Operations
P1
Data Register Read and Write;
Wiper Counter Register
Operations
Data Register Read and Write;
Wiper Counter Register
Operations
Data Register Read and Write;
Wiper Counter Register
Operations
Data Register Read and Write;
Wiper Counter Register
Operations
0
0
0
0
1
1
1
0
2
1
1
3
Operations
Data Register Read and Write;
Wiper Counter Register
Operations
Data Register Read and Write
Only
Data Register Read and Write
Only
Data Register Read and Write
Only
Table 1. Identification Byte Format
Device Type
Identifier
Set to 0
for proper operation
ID3
ID2
ID1
ID0
0
1
0
1
0
A2
Internal Slave
Address
A1
(MSB)
A0
(LSB)
Table 2. Instruction Byte Format
P1 and P0 are used also for register Bank Selection
for 2-Wire Register Write and Read operations
Register
Selection
Instruction Opcode
Register Selection
Register Selected
I3
I2
(MSB)
I1
I0
RB
RA
P1
P0
(LSB)
Pot Selection (Bank Selection)
Set to P0=0 for potentiometer operations
REV 1.1.7 2/6/03
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RB
RA
DR0
0
0
DR1
0
1
DR2
1
0
DR3
1
1
Characteristics subject to change without notice.
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X9279
Table 3. Instruction Set
Instruction
I3
I2
Instruction Set
I1 I0 RB RA
Read Wiper Counter
Register
Write Wiper Counter
Register
Read Data Register
1
0
0
1
0
1
0
1
0
1
0
1
Write Data Register
1
1
XFR Data Register to
Wiper Counter Register
1
XFR Wiper Counter
Register to Data Register
Increment/Decrement
Wiper Counter Register
Note:
P1
P0
Operation
0
0
0
0
0
0
0
1
1/0
1/0
1/0
1/0
0
0
1/0
1/0
1/0
1/0
1
0
1
1/0
1/0
0
0
1
1
1
0
1/0
1/0
0
0
0
0
1
0
0
0
0
0
Read the contents of the Wiper Counter
Register
Write new value to the Wiper Counter
Register
Read the contents of the Data Register pointed
to by P1-P0 and RB-RA
Write new value to the Data Register
pointed to by P1-P0 and RB-RA
Transfer the contents of the Data Register
pointed to by RB-RA (Bank 0 only) to the Wiper
Counter Register
Transfer the contents of the Wiper Counter
Register to the Register pointed to by RB-RA
(Bank 0 only)
Enable Increment/decrement of the Wiper
Counter Register
1/0 = data is one or zero
DEVICE DESCRIPTION
Wiper Counter Register (WCR)
The X9279 contains contains a Wiper Counter
Register, for the DCP potentiometer. The Wiper
Counter Register can be envisioned as a 8-bit parallel
and serial load counter with its outputs decoded to
select one of 256 switches along its resistor array. The
contents of the WCR can be altered in four ways: it
may be written directly by the host via the Write Wiper
Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of
four associated data registers via the XFR Data
Register instruction (parallel load); it can be modified
one step at a time by the Increment/Decrement
instruction (see Instruction section for more details).
Finally, it is loaded with the contents of its Data
Register zero (DR0) upon power-up.
The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9279 is powereddown. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
REV 1.1.7 2/6/03
different from the value present at power-down. Powerup guidelines are recommended to ensure proper
loadings of the DR0 value into the WCR. The DR0
value of Bank 0 is the default value.
Data Registers (DR)
The potentiometer has four 8-bit nonvolatile Data
Registers (DR3-DR0). These can be read or written
directly by the host. Data can also be transferred
between any of the four Data Registers and the
associated Wiper Counter Register. All operations
changing data in one of the Data Registers is a
nonvolatile operation and will take a maximum of
10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.
Bit [7:0] are used to store one of the 256 wiper
positions (0~255).
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X9279
Table 4. Wiper counter Register, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile, V).
WCR7
WCR6
WCR5
WCR4
WCR3
WCR2
WCR1
WCR0
V
V
V
V
V
V
V
V
(MSB)
(LSB)
Table 5. Data Register, DR (8-bit), Bit [7:0]: Used to store wiper positions or data (Nonvolatile, NV).
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NV
NV
NV
NV
NV
NV
NV
NV
MSB
LSB
Instructions
Four of the seven instructions are three bytes in length.
These instructions are:
– Read Wiper Counter Register – read the current
wiper position of the potentiometer,
Two instructions require a two-byte sequence to
complete. These instructions transfer data between the
host and the X9279; either between the host and one
of the data registers or directly between the host and
the Wiper Counter Register. These instructions are:
– XFR Data Register to Wiper Counter Register –
This transfers the contents of one specified Data
Register to the Wiper Counter Register.
– Write Wiper Counter Register – change current
wiper position of the potentiometer,
– Read Data Register – read the contents of the
selected Data Register;
– XFR Wiper Counter Register to Data Register –
This transfers the contents of the Wiper Counter
Register to the specified Data Register.
– Write Data Register – write a new value to the
selected Data Register.
The basic sequence of the three byte instructions is
illustrated in Figure 4. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
wiper to this action will be delayed by tWRL. A transfer
from the WCR (current wiper position), to a Data
Register is a write to nonvolatile memory and takes a
minimum of tWR to complete. The transfer can occur
between the potentiometer and one of its four
associated registers (Bank 0).
The final command is Increment/Decrement (Figure 5
and 6). The Increment/Decrement command is
different from the other commands. Once the
command is issued and the X9279 has responded with
an acknowledge, the master can clock the selected
wiper up and/or down in one segment steps; thereby,
providing a fine tuning capability to the host. For each
SCL clock pulse (tHIGH) while SDA is HIGH, the
selected wiper will move one resistor segment towards
the RH terminal. Similarly, for each SCL clock pulse
while SDA is LOW, the selected wiper will move one
resistor segment towards the RL terminal.
See Instruction format for more details.
Figure 3. Two-Byte Instruction Sequence
SCL
SDA
0
1
0
1
S ID3 ID2 ID1 ID0 0 A2 A1 A0
T
A
Internal
R
Device ID
T
Address
0
A
C
K
0
RB RA P1 P0 A
I3
I2 I1 I0
C
K
Instruction
Register
Pot/Bank
Opcode
Address
Address
S
T
O
P
These commands only valid when P1=P0=0
REV 1.1.7 2/6/03
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Characteristics subject to change without notice.
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X9279
Figure 4. Three-Byte Instruction Sequence
SCL
1
0
S ID3 ID2 ID1 ID0
T
A
R
Device ID
T
0
0
SDA
1
0
A2 A1 A0
External
Address
A
C
K
I0 RB RA P1 P0 A D7 D6 D5 D4 D3 D2 D1 D0 A S
C
C T
K
K O
Pot/Bank
WCR[7:0]
valid
only
when
P1=P0=0;
Instruction
P
Register
Address
or
Opcode
Address
Data Register D[7:0] for all values of P1 and P0
I3 I2
I1
Figure 5. Increment/Decrement Instruction Squence
SCL
0
SDA
S
T
A
R
T
1
0
1
0
ID3 ID2 ID1 ID0 0 A2
Device ID
A1 A0
External
Address
A
C
K
I3
I2
I1 I0
Instruction
Opcode
RB RA P1 P0
A
C
Register Pot/Bank K
Address
Address
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
S
T
O
P
Figure 6. Increment/Decrement Timing Limits
INC/DEC
CMD
Issued
tWRID
SCL
SDA
VW/RW
REV 1.1.7 2/6/03
Voltage Out
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X9279
INSTRUCTION FORMAT
Read Wiper Counter Register (WCR)
S
T
A
R
T
Device Type
Identifier
0
1
0
1
Device
Addresses
Instruction
DR/Bank
S
Opcode
Addresses
A
C
0 A2 A1 A0 K 1 0 0 1 0 0 0 0
S
A
C
K
Wiper Position
(Sent by X9279 on SDA) M
W W W W W W W W A
C C C C C C C C C
R R R R R R R R K
7 6 5 4 3 2 1 0
S
T
O
P
S
A
C
K
Wiper Position
(Sent by Master on SDA) S
W W W W W W W W A
C C C C C C C C C
R R R R R R R R K
7 6 5 4 3 2 1 0
S
T
O
P
Write Wiper Counter Register (WCR)
S
T
A
R
T
Device Type
Identifier
0
1
0
1
Device
Addresses
Instruction
DR/Bank
S
Opcode
Addresses
A
C
0 A2 A1 A0 K 1 0 1 0 0 0 0 0
Read Data Register (DR)
S
T
A
R
T
Device Type
Identifier
0
1
0
1
Device
Addresses
Instruction
DR/Bank
S
Opcode
Addresses
A
C
0 A 2 A 1 A 0 K 1 0 1 1 RB RA P1 P0
S
A
C
K
Wiper Position
(Sent by X9279 on SDA) M
W W W W W W W W A
C C C C C C C C C
R R R R R R R R K
7 6 5 4 3 2 1 0
S
A
C
K
Wiper Position
(Sent by Master on SDA) S
W W W W W W W W A
C C C C C C C C C
R R R R R R R R K
7 6 5 4 3 2 1 0
S
T
O
P
S
T
A
R
T
Device Type
Identifier
0
1
0
1
Device
Addresses
Instruction
DR/Bank
S
Opcode
Addresses
A
C
0 A2 A1 A0
1 1 0 0 RB RA P1 P0
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
Write Data Register (DR)
Transfer Wiper Counter Register (WCR) to Data Register (DR)
S
T
A
R
T
Device Type
Identifier
0
1
0
REV 1.1.7 2/6/03
1
Instruction
DR/Bank
S
S
Opcode
Addresses
A
A
C
C
0 A2 A1 A0
1 1 1 0 RB RA 0 0
K
K
Device
Addresses
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S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
Characteristics subject to change without notice.
12 of 24
X9279
Transfer Data Register (DR) to Wiper Counter Register (WCR)
S Device Type
T
Identifier
A
R 0 1 0 1
T
Device
Addresses
Instruction
DR/Bank
S
S
Opcode
Addresses
A
A
C
C
0 A 2 A 1 A 0 K 1 1 0 1 RB RA 0 0 K
S
T
O
P
Increment/Decrement Wiper Counter Register (WCR)
S Device Type
T
Identifier
A
R 0 1 0 1
T
Notes: (1)
(2)
(3)
(4)
(5)
Instruction
DR/Bank
S
Opcode
Addresses
A
C
0 A2 A1 A0 K 0 0 1 0 0 0 0 0
Device
Addresses
Increment/Decrement
S
(Sent by Master on SDA)
A
C
K I/D I/D . . . . I/D I/D
S
T
O
P
“MACK”/”SACK”: stands for the acknowledge sent by the master/slave.
“A3 ~ A0”: stands for the device addresses sent by the master.
“X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.
“I”: stands for the increment operation, SDA held high during active SCL phase (high).
“D”: stands for the decrement operation, SDA held low during active SCL phase (high).
REV 1.1.7 2/6/03
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Characteristics subject to change without notice.
13 of 24
X9279
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias ....................–65°C to +135°C
Storage temperature .........................–65°C to +150°C
Voltage on SCL, SDA any address input
with respect to VSS ..................................–1V to +7V
∆V = | (VH–VL) |.................................................... 5.5V
Lead temperature (soldering, 10 seconds)........ 300°C
IW (10 seconds).................................................. ±6mA
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this
specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temp
Min.
Max.
Device
Supply Voltage (VCC)(4) Limits
Commercial
0°C
+70°C
X9279
5V ±10%
–40°C
+85°C
X9279-2.7
2.7V to 5.5V
Industrial
ANALOG CHARACTERISTICS (Over recommended industrial (2.7V) operating conditions unless otherwise stated.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
RTOTAL
End to End Resistance
100
kΩ
T version
RTOTAL
End to End Resistance
50
kΩ
U version
End to End Resistance Tolerance
±20
%
Power Rating
50
mW
IW
Wiper Current
±3
mA
RW
Wiper Resistance
300
Ω
IW = ± 3mA @ VCC = 3V
RW
Wiper Resistance
150
Ω
IW = ± 3mA @ VCC = 5V
VTERM
Voltage on any RH or RL Pin
V
VSS = 0V
Noise
Resolution
Absolute Linearity
VSS
VCC
-120
dBV/ Hz
0.4
%
(1)
Relative Linearity (2)
Temperature Coefficient of
RTOTAL
CH/CL/CW
Potentiometer Capacitances
MI(3)
Rw(n)(actual) – Rw(n)(expected)(5)
±0.2
MI(3)
Rw(n + 1) – [Rw(n) + MI](5)
ppm/°C
20
10/10/25
Ref: 1V
±1
±300
Ratiometric Temp. Coefficient
25°C, each pot
ppm/°C
pF
See Macro model
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used
as a potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(3) MI = RTOT / 255 or (RH – RL) / 255, single pot
(4) During power up VCC > VH, VL, and VW.
(5) n = 0, 1, 2, ....,255; m =0, 1, 2, ...., 254.
REV 1.1.7 2/6/03
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Characteristics subject to change without notice.
14 of 24
X9279
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
ICC1
VCC supply current
(active)
3
mA
fSCL = 400KHz; VCC = +6V;
SDA = Open; (for 2-Wire, Active, Read
and
ICC2
VCC supply current
(nonvolatile write)
5
mA
fSCL = 400KHz; VCC = +6V;
SDA = Open; (for 2-Wire, Active,
Nonvolatile Write State only)
ISB
VCC current (standby)
5
µA
ILI
Input leakage current
10
µA
VCC = +6V; VIN = VSS or VCC;
SDA = VCC; (for 2-Wire, Standby State
only)
VIN = VSS to VCC
ILO
Output leakage current
10
µA
VOUT = VSS to VCC
VIH
Input HIGH voltage
VCC x 0.7
VCC + 1
V
VIL
Input LOW voltage
–1
VCC x 0.3
V
VOL
Output LOW voltage
0.4
V
VOH
Output HIGH voltage
IOL = 3mA
ENDURANCE AND DATA RETENTION
Parameter
Min.
Units
Minimum endurance
100,000
Data changes per bit per register
Data retention
100
years
CAPACITANCE
Symbol
(6)
CIN/OUT
(6)
CIN
Test
Max.
Units
Test Conditions
Input / Output capacitance (SDA)
8
pF
VOUT = 0V
Input capacitance (SCL, WP, A2, A1 and A0)
6
pF
VIN = 0V
POWER-UP TIMING
Symbol
(6)
tr VCC
Parameter
VCC Power-up rate
Min.
Max.
Units
0.2
50
V/ms
(7)
Power-up to initiation of read operation
1
ms
(7)
Power-up to initiation of write operation
50
ms
tPUR
tPUW
A.C. TEST CONDITIONS
Input Pulse Levels
Input rise and fall times
Input and output timing level
VCC x 0.1 to VCC x 0.9
10ns
VCC x 0.5
Notes: (6) This parameter is not 100% tested
(7) tPUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be
issued. These parameters are periodically sampled and not 100% tested.
REV 1.1.7 2/6/03
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Characteristics subject to change without notice.
15 of 24
X9279
EQUIVALENT A.C. LOAD CIRCUIT
5V
SPICE Macromodel
3V
867 Ω
1533Ω
SDA pin
RTOTAL
RH
SDA pin
RL
CW
CL
100pF
100pF
CL
10pF
25pF
10pF
RW
AC TIMING
Symbol
Parameter
Min.
Max.
Units
400
kHz
fSCL
Clock Frequency
tCYC
Clock Cycle Time
2500
ns
tHIGH
Clock High Time
600
ns
tLOW
Clock Low Time
1300
ns
tSU:STA
Start Setup Time
600
ns
tHD:STA
Start Hold Time
600
ns
tSU:STO
Stop Setup Time
600
ns
tSU:DAT
SDA Data Input Setup Time
100
ns
tHD:DAT
SDA Data Input Hold Time
30
ns
tR
SCL and SDA Rise Time
300
ns
tF
SCL and SDA Fall Time
300
ns
tAA
SCL Low to SDA Data Output Valid Time
0.9
µs
tDH
SDA Data Output Hold Time
0
ns
TI
Noise Suppression Time Constant at SCL and SDA inputs
50
ns
tBUF
Bus Free Time (Prior to Any Transmission)
1200
ns
tSU:WPA
A0, A1 Setup Time
0
ns
tHD:WPA
A0, A1 Hold Time
0
ns
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
tWR
REV 1.1.7 2/6/03
Parameter
High-voltage write cycle time (store instructions)
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Typ.
Max.
Units
5
10
ms
Characteristics subject to change without notice.
16 of 24
X9279
XDCP TIMING
Symbol
Parameter
Min.
Max.
Units
tWRPO
Wiper response time after the third (last) power supply is stable
5
10
µs
tWRL
Wiper response time after instruction issued (all load instructions)
5
10
µs
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
N/A
Changing:
State Not
Known
Center Line
is High
Impedance
.
REV 1.1.7 2/6/03
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Characteristics subject to change without notice.
17 of 24
X9279
TIMING DIAGRAMS
Start and Stop Timing
(START)
(STOP)
tR
tF
SCL
tSU:STA
tHD:STA
tSU:STO
tR
tF
SDA
Input Timing
tCYC
tHIGH
SCL
tLOW
SDA
tSU:DAT
tHD:DAT
tBUF
Output Timing
SCL
SDA
tAA
REV 1.1.7 2/6/03
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tDH
Characteristics subject to change without notice.
18 of 24
X9279
XDCP Timing (for All Load Instructions)
(STOP)
SCL
LSB
SDA
tWRL
VWx
Write Protect and Device Address Pins Timing
(START)
SCL
(STOP)
...
(Any Instruction)
...
SDA
...
tSU:WPA
tHD:WPA
WP
A0, A1
REV 1.1.7 2/6/03
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Characteristics subject to change without notice.
19 of 24
X9279
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
+VR
VR
RW
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
Application Circuits
Noninverting Amplifier
VS
Voltage Regulator
+
VO
–
VIN
VO (REG)
317
R1
R2
Iadj
R1
R2
VO = (1+R2/R1)VS
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
Offset Voltage Adjustment
R1
Comparator with Hysterisis
R2
VS
VS
–
+
VO
100KΩ
–
VO
+
}
}
TL072
R1
R2
10KΩ
10KΩ
+12V
REV 1.1.7 2/6/03
VUL = {R1/(R1+R2)} VO(max)
RLL = {R1/(R1+R2)} VO(min)
10KΩ
-12V
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Characteristics subject to change without notice.
20 of 24
X9279
Application Circuits (continued)
Attenuator
Filter
C
VS
+
R2
R1
VS
VO
–
–
R
VO
+
R3
R4
R2
R1 = R2 = R3 = R4 = 10kΩ
R1
GO = 1 + R2/R1
fc = 1/(2πRC)
VO = G VS
-1/2 ≤ G ≤ +1/2
R1
R2
}
}
Inverting Amplifier
Equivalent L-R Circuit
VS
R2
C1
–
VS
VO
+
+
–
R1
ZIN
VO = G VS
G = - R2/R1
R3
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R1 + R3) >> R2
Function Generator
C
R2
–
+
R1
–
} RA
+
} RB
frequency ∝ R1, R2, C
amplitude ∝ RA, RB
REV 1.1.7 2/6/03
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Characteristics subject to change without notice.
21 of 24
X9279
PACKAGING INFORMATION
14-LEAD PLASTIC, TSSOP, PACKAGE TYPE V
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.193 (4.9)
.200 (5.1)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0∞– 8∞
Seating Plane
.019 (.50)
.029 (.75)
DetailA (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
REV 1.1.7 2/6/03
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Characteristics subject to change without notice.
22 of 24
X9279
16-Bump Chip Scale Package (CSP B16)
Package Outline Drawing
a
9279TRB
YWW I
LOT #
f
d
A4
A3
A2
A1
B4
B3
B2
B1
j
C4
C3
C2
C1
m
D4
D3
D2
D1
l
Top View (Marking Side)
b
k
e
Bottom View (Bumped Side)
Side View
e
c
Side View
Package Dimensions
Package Width
Package Length
Package Height
Body Thickness
Ball Height
Ball Diameter
Ball Pitch – Width
Ball Pitch – Length
Ball to Edge Spacing – Width
Ball to Edge Spacing – Length
REV 1.1.7 2/6/03
Ball Matrix:
Symbol
a
b
c
d
e
f
j
k
l
m
Min
2.593
2.771
0.644
0.444
0.200
0.300
0.537
0.626
Millimeters
Nominal
2.623
2.801
0.677
0.457
0.220
0.320
0.5
0.5
0.562
0.651
Max
2.653
2.831
0.710
0.470
0.240
0.340
4
3
2
RL
1
RH
A
A0
Vcc
B
A2
C
D
SCL
SDA
NC
NC
RW
NC
Vss
NC
WP
A3
A1
0.587
0.676
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Characteristics subject to change without notice.
23 of 24
X9279
ORDERING INFORMATION
X9279
Y
P
T
V
VCC Limits
Blank = 5V ±10%
–2.7 = 2.7 to 5.5V
Device
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
Package
V14 = 14-Lead TSSOP
B = 16-Lead CSP
Potentiometer Organization
Pot
T = 100KΩ
U = 50KΩ
LIMITED WARRANTY
©Xicor, Inc. 2003 Patents Pending
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
REV 1.1.7 2/6/03
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Characteristics subject to change without notice.
24 of 24