XM20C64 XM20C64 64K 8K x 8 High Speed AUTOSTORE™ NOVRAM FEATURES DESCRIPTION • • • • The XM20C64 is a high speed nonvolatile RAM Module. It is comprised of four Xicor X20C16 high speed NOVRAMs, a high speed decoder and decoupling capacitors mounted on a co-fired multilayered Ceramic substrate. The XM20C64 is configured 8K x 8 and is fully decoded. The module is a 28-lead DIP conforming to the industry standard pinout for SRAMs. • • • • • • • High Speed: tAA = 55ns NO Batteries!! Low Power CMOS AUTOSTORE™ NOVRAM —Automatically Stores RAM data to E2PROM upon Power-fail Detection Open Drain AUTOSTORE Output Pin —Provides Interrupt or Status Information —Linkable to System Reset Circuitry Auto Recall —Automatically Recalls E2PROM Data During Power-on Fully Decoded Module Full Military Temperature Range — –55°C to +125°C High Reliability —Endurance: 1,000,000 Nonvolatile Store Cycles —Data Retention: 100 Years ESD Protection —≥2KV All Pins Also Available in 66 Pin PUMA Package The XM20C64 fully supports the AUTOSTORE feature, providing hands-off automatic storing of RAM data into E2PROM when VCC falls below the AUTOSTORE threshold. The XM20C64 is a highly reliable memory component, supporting unlimited writes to RAM, a minimum 1,000,000 store cycles and a minimum 100 year data retention. FUNCTIONAL DIAGRAM PIN CONFIGURATION 2 NE 25 OE 31 WE 23 NE 1 28 VCC OE A12 2 27 WE WE A7 3 26 AS A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 OE A3 7 22 OE WE A2 8 21 A10 A1 9 20 CE A0 10 19 I/O0 I/O1 11 18 A0–A10 I/O7 I/O6 12 17 13 16 I/O5 I/04 I/O I/O2 VSS 14 15 I/O3 NE A0–A10 I/O CE 30 2 A11 A12 2 3 Y0 A0 Y1 A1 Y2 Y3 CE 4 5 6 25 31 23 7 1 NE A0–A10 I/O CE 30 2 25 31 23 NE OE WE CE 30 2 25 31 23 3874 FHD F02.1 NE A0–A10 A0–A10 OE WE I/O CE I/O0–I/O7 30 AUTOSTORE 3874 FHD F01 AUTOSTORE™ NOVRAM is a trademark of Xicor, Inc. ©Xicor, Inc. 1991, 1995, 1996 Patents Pending 3874-1.6 6/20/96 T0/C2/D0 NS 1 Characteristics subject to change without notice XM20C64 PIN DESCRIPTIONS DEVICE OPERATION Addresses (A0-A12) NOVRAM operations are identical to those of a standard SRAM. When OE and CE are asserted data is presented at the I/Os from the address location pointed to by the A0–A12 inputs. The address inputs select an 8-bit memory location during read and write operations. Chip Enable (CE) RAM write operations are initiated and the address input is latched by the HIGH to LOW transition of CE or WE, whichever occurs last. Data is latched on the rising edge of either CE or WE, whichever occurs first. The chip enable input must be LOW to enable all read, write and user requested nonvolatile operations. Output Enable (OE) During normal RAM operations OE controls the data output buffers. If a hardware nonvolatile operation is selected (NE = CE = LOW) and OE strobes LOW, a recall operation will be initiated. An array recall, E2PROM data transferred to RAM, is initiated whenever OE = NE = CE = LOW. A recall is also performed automatically upon power-up. Command Sequence Operations OE LOW will always disable a STORE operation regardless of the state of NE, WE, and CE so long as the internal transfer has not commenced. The X20C64 employs a version of the industry standard Software Data Protection (SDP). The end user can select various options for transferring data from RAM into the E2PROM array. Write Enable (WE) During normal RAM operations WE = CE = LOW will cause data to be written to the RAM address pointed to by the A0-A12 inputs. All command sequences are comprised of three specific data/address write operations performed with NE LOW. A Store operation can be directly selected by issuing a Store command. The user may also enable and disable the AUTOSTORE function through the software data protection sequence. Refer to Table 1 below for a complete description of the command sequence. Nonvolatile Enable (NE) The nonvolatile input controls the transfer of data from the E2PROM array to the RAM array, when strobed LOW in conjunction with CE = OE = LOW. Operational Notes Data In/Data Out (I/O0-I/O7) The X20C64 should be viewed as a subsystem when writing software for the various store operations. The module contains four discrete components each needing to be set to the required state individually. The two high order address bits (A11 and A12) select only one of the four components. Data is written to or read from the X20C64 through the I/O pins. The I/O pins are placed in the high impedance state when either CE or OE is HIGH or when NE is LOW. AUTOSTORE Output (AS) AS is an open-drain output. When it is asserted (driving LOW) it indicates VCC has fallen below the AUTOSTORE threshold and an internal store operation has been initiated. Because AS is an open drain output it may be wire-ORed with multiple open drain outputs and used as an interrupt input to a microprocessor. 2 XM20C64 TABLE 1 TABLE 2 Step Operation A0–A10* Data Pattern Command Function 1 2 3 Write Write Write 555 2AA 555 AA 55 Command CC[H] CD[H] 33[H] Enable Autostore Disable Autostore Store Operation 3874 PGM T11 3874 PGM T12.2 * It should be noted, the high order addresses should remain stable during the operations. It should also be noted that these commands are not global, that is only one device on the module will be affected by each command operation. Command Sequence Timing Limits Limits Symbol Parameter Min. tSTO tSP tSPH Store Time Command Write Pulse Width Inter Command Delay 50 55 Note: Max. Units 5 ms ns ns 3874 PGM T01.1 All Write Command Sequence timings must conform to the standard write timing requirements. Command Sequence tSTO ADDRESS 555 555 2AAA OE tSP CE WE NE tDS DATA IN tDH AA 55 CMD 3874 FHD F03.1 3 XM20C64 ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias .................. –65°C to +125°C Storage Temperature ....................... –65°C to +125°C Voltage on any Pin with Respect to VSS ............................................ –1V to +7V Lead Temperature (Soldering, 10 seconds) .............................. 300°C *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the module. This is a stress rating only and the functional operation of the module at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect module reliability. RECOMMENDED OPERATING CONDITIONS Temperature Max. Supply Voltage Limits +125°C XM20C64 5V ±10% Min. Military –55°C 3874 PGM T07 3874 PGM T06 D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.) Limits Symbol Parameter Min. Max. Units Test Conditions NE = WE + VIH, CE = OE = VIL, Address Inputs = TTL Inputs @ f = 20MHz All I/Os = Open All Inputs = VIH, All I/Os = Open lCC1 VCC Active Current 100 mA ICC2 VCC Active Current (AUTOSTORE) VCC Standby Current Input Leakage Current Output Leakage Current Input LOW Voltage Input HIGH Voltage Output LOW Voltage AUTOSTORE Output Voltage Output HIGH Voltage 10 mA 1.5 10 10 0.8 VCC + 0.5 0.4 0.4 mA µA µA V V V V ISB ILI ILO VIL(1) VIH(1) VOL VOLAS VOH –0.5 2 2.4 V All Inputs = VCC–0.3V All I/Os = Open VIN = VSS to VCC VIN = VSS to VCC, CE = VIH IOL = 5mA IOLAS = 1mA IOH = –4mA 3874 PGM T08.2 POWER-UP TIMING Symbol tPUR tPUST Parameter Power-Up (VCC Min.) to RAM Operation Power-Up (VCC Min.) to Store Operation Max. Units 500 5 µs ms 3874 PGM T09 CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V. Symbol (2) CI/O CIN(2) Test Max. Units Conditions Input/Output Capacitance Input Capacitance 40 24 pF pF VI/O = 0V VIN = 0V 3874 PGM T10.1 Notes: (1) VIL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested. 4 XM20C64 A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified) Read Cycle Limits Limits Symbol Parameter Min. tRC tCE tAA tOE tLZ(3) tOLZ(3) tHZ(3) tOHZ(3) tOH Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE Low to Output in Low Z OE Low to Output in Low Z CE High to Output in Low Z OE High to Output in Low Z Output Hold 55 Max. Units ns ns ns ns ns ns ns ns ns 55 55 30 0 0 0 0 0 25 25 3874 PGM T03 Read Cycle Timing Diagram tRC ADDRESS tCE CE tOE OE tOLZ tHZ tLZ tOH tOHZ I/O tAA Note: 3874 FHD F05 (3) tLZ min., tHZ min., tOLZ min., and tOHZ min. are periodically sampled and not 100% tested. tHZ max. and tOHZ max. are measured from the point when CE or OE return high (whichever occurs first) to the time when the outputs are no longer driven. MODE SELECTION CE WE NE OE Mode I/O State Power H L L L L L L L X H L L H H H L X H H L H L L L X L X H H L H L Module Not Selected Read RAM Active Write RAM Issue Software Command Output Disabled Hardware Array Recall No Operation Not Allowed High Z Data Output Data Input Data Input High Z High Z High Z High Z Standby Active Active Active Active Active Active Active 3874 PGM T04.1 5 XM20C64 Write Cycle Limits Limits Symbol tWC tWP tCW tAS tDS tDH tOW tWR Parameter Min. Write Cycle time WE Pulse Width CE Pulse Width Address Setup Data Setup Data Hold Output Active from End of Write End of Write to Read Max. 55 40 40 0 25 0 5 0 Units ns ns ns ns ns ns ns ns 3874 PGM T02 Write Cycle Timing Diagram tWC ADDRESS OE tWR tCW CE tAS tWP WE tOW DATA OUT tDS tDH DATA VALID DATA IN 3874 FHD F04 6 XM20C64 Array Recall Timing Limits Symbol Parameter tRCC tRCP tRWE Min. Array Recall Time Recall Strobe Pulse Width Delay From WE HIGH to Recall Max. Units 10 µs ns ns 50 0 3874 PGM T05.1 Note: The recall sequence must be repeated for each memory component individually. This is accomplished by sequencing through the Array Recall Cycle with all four combinations of A11, and A12. Array Recall Cycle tRCC ADDRESS tRCP NE OE tRWE WE CE DATA I/O 3874 FHD F06.1 EQUIVALENT TEST LOAD CIRCUIT SYMBOL TABLE WAVEFORM 5V 735Ω OUTPUT 318Ω 30pF 3874 FHD F07.2 7 INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed N/A Changing: State Not Known Center Line is High Impedance XM20C64P XM20C64 PIN CONFIGURATION 1 12 23 34 45 56 I/O8 WE2 I/O15 I/O24 VCC I/O31 I/O9 CE2 I/O14 I/O25 CE4 I/O30 I/O10 GND I/O13 I/O26 WE4 I/O29 AS I/O11 I/O12 A6 I/O27 I/O28 NE A10 OE A7 A3 A0 NC NC NC A15 A4 A1 NC NC WE1 A8 A5 A2 NC VCC I/O7 A9 I/O0 CE1 I/O6 I/O16 CE3 I/O22 I/O1 NC I/O5 I/O17 GND I/O21 I/O2 I/O3 I/O4 I/O18 I/O19 I/O20 11 22 33 44 WE3 I/O23 55 66 3874 ILL F10 PACKAGING INFORMATION 1.09+/-.010 SQ .149+/-.015 .180 .050 TYP .100 TYP PIN #1 IDENTIFIER (NOT CHAMFERED) .320 MAX .050 .600 TYP .018 .100 TYP 0.15 .040 ALL MEASUREMENTS IN INCHES .164 .410 8 .130 3874 ILL F11 XM20C64 PACKAGING INFORMATION 28-PIN DUAL-IN-LINE PACKAGE CERAMIC LEADLESS CHIP CARRIERS ON CERAMIC SIDEBRAZED CERAMIC SUBSTRATE .600 (15.24) .580 (14.73) PIN 1 1.600 MAX. (40.64) .295 MAX. (6.00) .010 MIN. (.25) .018 ± .002 (.46 ± .05) .140 MIN. (3.56) .100 ± .005 TYP. (2.54 ± .13) 1.300 ± .005 (33.02 ± 0.13) TOL. NON. ACCUM. + .002 – .001 + .05 (.25 ) – .03 .010 .600 ± .010 (15.24 ± .25) NOTES: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY 3926 FHD F40 9 XM20C64P XM20C64 NOTES 10 XM20C64 ORDERING INFORMATION XM20C64: 2K X 8 CMOS NOVRAM Memory Module XM20C64 X X -X Access Time –55 = 55ns Device Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C M = Military = –55°C to +125°C MHR = Military High Rel Blank = 28 Lead Ceramic DIP Module P = 66 Pin PUMA Module LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 11