XILINX XC3195A

XC3100A
Logic Cell Array Families

Product Specifications
Features
Description
• Ultra-high-speed FPGA family with six members
– 50-85 MHz system clock rates
– 190 to 325 MHz guaranteed flip-flop toggle rates
The XC3100A is a performance-optimized relative of the
XC3000 and XC3000A families. While all families are
footprint compatible, XC3100A familiy extends the system
performance beyond 80 MHz.
– 1.75 to 4.1 ns logic delays
The XC3100A familiy follows the XC4000 speed-grade
nomenclature, indicating device performance with a number that is based on the internal logic-block delay, in ns.
• High-end additional family member in the 22 X 22
CLB array-size XC3195A device
• 8 mA output sink current and 8 mA source current
The XC3100A family offers the following enhancements
over the popular XC3100 family.
• Maximum power-down and quiescent current is 5 mA
The XC3100A family has additional interconnect resources
to drive the I-inputs of TBUFs driving horizontal Longlines.
The CLB Clock Enable input can be driven from a second
vertical Longline. These two additions result in more
efficient and faster designs when horizontal Longlines are
used for data bussing.
• Both families are 100% architecture and pin-out
compatible with other XC3000 families
• Beyond this, XC3100A is also software and bitstream
compatible with the XC3000, XC3000A, and XC3000L
families
• 100% PCI complaint (A-2 speed grade in plastic quad
flat pack (PQFP) packaging).
During configuration, the XC3100A devices check the
bitstream format for stop bits in the appropriate positions.
Any error terminates the configuration and pulls INIT Low.
XC3100A combines the features of the XC3000A and
XC3100 families.
When the configuration process is finished and the device
starts up in user mode, the first activation of the outputs is
automatically slew-rate limited. This feature, called Soft
Startup, avoids the potential ground bounce when all
outputs are turned on simultaneously. After start-up, the
slew rate of the individual outputs is, as in all XC3000
families, determined by the individual configuration option.
• Additional interconnect resources for TBUFs and CE
inputs
• Error checking of the configuration bitstream
• Soft startup holds all outputs slew-rate limited during
initial power-up
The XC3100A family is a superset of the XC3000 families.
Any bitstream used to configure an XC3000, XC3000A,
XC3000L or XC3100 device, will configure the same-size
XC3100A device exactly the same way.
• More advanced CMOS process
Device
CLBs
Array
User I/O
Max
XC3120A
XC3130A
XC3142A
XC3164A
XC3190A
XC3195A
64
100
144
224
320
484
8x8
10 x 10
12 x 12
16 x 14
16 x 20
22 x 22
64
80
96
120
144
176
2-177
Flip-Flops
256
360
480
688
928
1,320
Horizontal
Longlines
16
20
24
28
40
44
Configuration
Data Bits
14,779
22,176
30,784
46,064
64,160
94,944
XC3100, XC3100A Logic Cell Array Family
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently
released device performance parameters, please request a copy of the current test-specification revision.
Absolute Maximum Ratings
Symbol Description
Units
VCC
Supply voltage relative to GND
–0.5 to +7.0
V
VIN
Input voltage with respect to GND
–0.5 to VCC +0.5
V
VTS
Voltage applied to 3-state output
–0.5 to VCC +0.5
V
TSTG
Storage temperature (ambient)
–65 to +150
°C
TSOL
Maximum soldering temperature (10 s @ 1/16 in.)
+260
°C
Junction temperature plastic
+125
°C
Junction temperature ceramic
+150
°C
TJ
Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed
under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for
extended periods of time may affect device reliability.
Operating Conditions
Symbol
VCC
Description
Min
Max
Units
Supply voltage relative to GND Commercial 0°C to +85°C junction
4.75
5.25
V
Supply voltage relative to GND Industrial -40°C to +100°C junction
4.5
5.5
V
VIHT
High-level input voltage — TTL configuration
2.0
VCC
V
VILT
Low-level input voltage — TTL configuration
0
0.8
V
VIHC
High-level input voltage — CMOS configuration
70%
100%
VCC
VILC
Low-level input voltage — CMOS configuration
0
20%
VCC
TIN
Input signal transition time
250
ns
At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.3% per °C.
2-178
DC Characteristics Over Operating Conditions
Symbol
VOH
Description
Min
High-level output voltage (@ IOH = –8.0 mA, VCC min)
Max
3.86
Units
V
Commercial
VOL
Low-level output voltage (@ IOL = 8.0 mA, VCC min)
VOH
High-level output voltage (@ IOH = –8.0 mA, VCC min)
0.40
3.76
V
V
Industrial
VOL
Low-level output voltage (@ IOL = 8.0 mA, VCC min)
VCCPD
Power-down supply voltage (PWRDWN must be Low)
ICCO
Quiescent LCA supply current
Chip thresholds programmed as CMOS levels1
0.40
2.30
Chip thresholds programmed as TTL levels
–10
V
V
8
mA
14
mA
+10
µA
IIL
Input Leakage Current
CIN
Input capacitance, all packages except PGA175
(sample tested)
All Pins except XTL1 and XTL2
XTL1 and XTL2
10
15
pF
pF
Input capacitance, PGA 175
(sample tested)
All Pins except XTL1 and XTL2
XTL1 and XTL2
15
20
pF
pF
IRIN
Pad pull-up (when selected) @ VIN = 0V (sample tested)
0.02
0.17
mA
IRLL
Horizontal long line pull-up (when selected) @ logic Low
0.20
2.80
mA
Note: 1. With no output current loads, no active input or long line pull-up resistors, all package pins at VCC or GND,
and the LCA configured with a MakeBits tie option.
2. Total continuous output sink current may not exceed 100 mA per ground pin. The number of ground pins varies
from two for the XC3120A in the PC84 package, to eight for the XC3195A in the PQ208 or PG223 package.
2-179
XC3100, XC3100A Logic Cell Array Family
CLB Switching Characteristic Guidelines
CLB Output (X, Y)
(Combinatorial)
T ILO
1
CLB Input (A,B,C,D,E)
T ICK
2
3
T CKI
CLB Clock
12 TCL
11 T CH
4
TDICK
5
TCKDI
6
T ECCK
7
TCKEC
CLB Input
(Direct In)
CLB Input
(Enable Clock)
8
TCKO
CLB Output
(Flip-Flop)
CLB Input
(Reset Direct)
13 TRPW
9 T RIO
T
CLB Output
(Flip-Flop)
X5424
Buffer (Internal) Switching Characteristic Guidelines
-5
-4
-3
-2
-1
Symbol
Max
Max
Max
Max
Max
Units
TPID
6.8
6.5
5.6
5.2
4.8
ns
TPIDC
5.4
5.1
4.3
4.0
3.8
ns
TBUF driving a Horizontal Long line (L.L.)*
I to L.L. while T is Low (buffer active) (XC3100)
(XC3100A)
T↓ to L.L. active and valid with single pull-up resistor
T↓ to L.L. active and valid with pair of pull-up resistors
T↑ to L.L. High with single pull-up resistor
T↑ to L.L. High with pair of pull-up resistors
TIO
TIO
TON
TON
TPUS
TPUF
4.1
3.6
5.6
7.1
15.6
12.0
3.7
3.6
5.0
6.5
13.5
10.5
3.1
3.1
4.2
5.7
11.4
8.8
3.1
4.2
5.7
11.4
8.1
2.9
4.0
5.5
10.4
7.1
ns
ns
ns
ns
ns
ns
BIDI
Bidirectional buffer delay
TBIDI
1.4
1.2
1.0
0.9
0.85
ns
Description
Global and Alternate Clock Distribution*
Either: Normal IOB input pad through clock buffer
to any CLB or IOB clock input
Or:
Fast (CMOS only) input pad through clock
buffer to any CLB or IOB clock input
* Timing is based on the XC3142A, for other devices see XACT timing calculator.
2-180
ADVANCE INFORMATION
Speed Grade
CLB Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Description
Symbol
Combinatorial Delay
Logic Variables A, B, C, D, E,
to outputs X or Y
Sequential delay
Clock K to outputs X or Y
Clock K to outputs X or Y when Q is returned
through function generators F or G
to drive X or Y
-5
Min
-4
-3
-2
-1
Max Min
Max
Min Max
Min Max Min Max
1 TILO
4.1
3.3
2.7
2.2
8 TCKO
3.1
2.5
2.1
1.7
TQLO
6.3
5.2
4.3
3.5
ADVANCE INFORMATION
Speed Grade
Units
1.75
ns
1.4
ns
3.2
ns
Set-up time before clock K
Logic Variables
Data In
Enable Clock
Reset Direct inactive
A, B, C, D, E
DI
EC
RD
2 TICK
3.1
4 TDICK 2.0
6 TECCK 3.8
1.0
2.5
1.6
3.2
1.0
2.1
1.4
2.7
1.0
1.8
1.3
2.5
1.0
1.7
1.2
2.3
1.0
ns
ns
ns
ns
Hold Time after clock k
Logic Variables
Data In
Enable Clock
A, B, C, D, E
DI
EC
3 TCKI
0
5 TCKDI 1.0
7 TCKEC 1.0
0
1.0
0.8
0
0.9
0.7
0
0.9
0.7
0
0.8
0.6
ns
ns
ns
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
11 TCH
12 TCL
FCLK
2.4
2.4
190
2.0
2.0
230
1.6
1.6
270
1.3
1.3
325
1.3
1.3
325
ns
ns
MHz
Reset Direct (RD)
RD width
delay from RD to outputs X or Y
13 TRPW
9 TRIO
3.8
3.2
2.7
2.3
2.3
2.4
ns
ns
12.0
ns
ns
4.4
3.7
3.1
2.7
Global Reset, from RESET Pad,
RESET width (Low)
(XC3142A)
delay from RESET pad to outputs X or Y
Notes:
TMRW 14.0
TMRQ
17.0
14.0
12.0
14.0
12.0
12.0
12.0
12.0
The CLB K to Q output delay (TCKO, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than
the Data In hold time requirement (TCKDI, #5) of any CLB on the same die.
TILO, TQLO and TICK are specified for 4-input functions. For 5-input functions or base FGM functions, each of these
specifications for the XC3100A family increses by 0.50 ns (-5), 0.42 ns (-4) and 0.35 ns (-3).
2-181
XC3100, XC3100A Logic Cell Array Family
IOB Switching Characteristic Guidelines
I/O Block (I)
3
T PID
I/O Pad Input
T PICK
1
I/O Clock (IK/OK)
12 TIOL
11 TIOH
I/O Block (RI)
4
13 TRRI
TIKRI
RESET
TOOK
5
6
TOKO
15 TRPO
I/O Block (O)
10 TOP
I/O Pad Output
(Direct)
TOKPO
7
I/O Pad Output
(Registered)
I/O Pad TS
8
T TSHZ
9
TTSON
I/O Pad Output
X5425
Vcc
PROGRAM-CONTROLLED MEMORY CELLS
OUT
INVERT
3- STATE
(OUTPUT ENABLE)
OUT
OUTPUT
SELECT
3-STATE
INVERT
SLEW
RATE
PASSIVE
PULL UP
T
O
D
Q
FLIP
FLOP
OUTPUT
BUFFER
I/O PAD
R
DIRECT IN
REGISTERED IN
I
Q
Q D
FLIP
FLOP
or
LATCH
TTL or
CMOS
INPUT
THRESHOLD
R
OK
(GLOBAL RESET)
IK
CK1
CK2
PROGRAM
CONTROLLED
MULTIPLEXER
= PROGRAMMABLE INTERCONNECTION POINT or PIP
2-182
X3029
IOB Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Description
Propagation Delays (Input)
Pad to Direct In (I)
Pad to Registered In (q) with
latch transparent
(XC3100A)
(XC3100)
Clock (IK) to Registered In (Q)
Set-up Time (Input)
Pad to Clock (IK) set-up time
XC3100 Family
XC3120A,XC3130A
XC3142A
XC3164A
XC3190A
XC3195A
Propagation Delays (Output)
Clock (OK) to Pad
(fast)
same
(slew-rate limited)
Output (O) to Pad
(fast)
same
(slew-rate limited) (XC3100A)
(XC3100)
3-state to Pad begin hi-Z (fast)
same
(slew-rate limited)
3-state to Pad active and valid (fast) (XC3100A)
same
(slew-rate limited)
3-state to Pad active and valid (fast) (XC3100)
same
(slew-rate limited)
Set-up and Hold Times (Output)
Output (O) to clock (OK) set-up time,(XC3100A)
(XC3100)
Output (O) to clock (OK) hold time
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
Global Reset Delays
RESET Pad to Registered In (Q),
(XC3120/XC3120A)
(XC3195/XC3195A)
RESET Pad to output pad (fast)
(slew-rate limited)
-4
-3
-2
-1
Max
Min Max
Min Max
Min Max
Min-Max
3 TPID
2.8
2.5
2.2
2.0
1.8
TPTG
TPTG
4 TIKRI
14.0
16.0
2.8
12.0
15.0
2.5
11.0
13.0
2.2
11.0
Symbol
1 TPICK
7
7
10
10
10
9
9
8
8
8
8
-5
Min
15.0
10.9
11.0
11.2
11.5
12.0
TOKPO
TOKPO
TOPF
TOPS
TOPF
TTSHZ
TTSHZ
TTSON
TTSON
TTSON
TTSON
14.0
10.6
10.7
11.0
11.2
11.6
5.5
14.0
4.1
12.1
13.0
6.9
6.9
10.0
18.0
12.0
20.0
12.0
9.4
9.5
9.7
9.9
10.3
5.0
12.0
3.7
11.0
11.0
6.2
6.2
10.0
17.0
10.0
17.0
5.0
6.2
0
4.5
5.6
0
4.0
5.0
0
11 TIOH
12 TIOL
FCLK
2.4
2.4
190.0
2.0
2.0
230.0
1.6
1.6
270.0
15 TRPO
15 TRPO
18.0
29.5
24.0
32.0
15.0
25.0
20.0
27.0
8.9
9.0
9.2
9.4
9.8
4.4
10.0
3.3
9.0
9.0
5.5
5.5
9.0
15.0
9.0
15.0
5 TOOK
5 TOOK
6 TOKO
13 TRRI
1.9
11.0
1.8
8.5
8.6
8.8
9.0
9.4
4.0
9.7
3.0
8.7
5.0
5.0
8.5
14.2
3.6
13.0
21.0
17.0
23.0
ADVANCE INFORMATION
Speed Grade
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3.6
8.9
2.7
8.0
4.5
4.5
6.5
11.8
3.2
0
0
ns
ns
ns
1.3
1.3
325.0
1.3
1.3
325.0
ns
ns
MHz
13.0
21.0
17.0
23.0
13.0
21.0
17.0
22.0
ns
ns
ns
ns
Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). For larger capacitive loads,
see XAPP 024. Typical slew rate limited output rise/fall times are approximately four times longer.
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the
internal pull-up resistor or alternatively configured as a driven output or driven from an external source.
3. Input pad set-up time is specified with respect to the internal clock (IK). In order to calculate system set-up time, subtract
clock delay (pad to ik) from the input pad set-up time value. Input pad holdtime with respect to the internal clock (IK) is
negative. This means that pad level changes immediately before the internal clock edge (IK) will not be recognized.
4. TPID, TPTG, and TPICK are 3 ns higher for XTAL2 when the pin is configured as a user input.
2-183
XC3100, XC3100A Logic Cell Array Family
For a detailed description of the device architecture, see pages 2-105 through 2-123.
For a detailed description of the configuration modes and their timing, see pages 2-124 through 2-132.
For detailed lists of package pin-outs, see pages 2-140 through 2-150.
For package physical dimensions and thermal data, see Section 4.
XC3130A-70PC44C
Example:
Ordering Information
Device Type
Temperature Range
Toggle Rate
Number of Pins
Package Type
Component Availability
44
PINS
TYPE
CODE
XC3120A
XC3130A
XC3142A
XC3164A
XC3190A
XC3195A
-5
-4
-3
-2
-1
-5
-4
-3
-2
-1
-5
-4
-3
-2
-1
-5
-4
-3
-2
-1
-5
-4
-3
-2
-1
-5
-4
-3
-2
-1
64
68
84
100
CERAM PLAST.
PLAST.
PLAST.
PLAST.
PLAST.
PLCC
VQFP
PLCC
PLCC
PC44
VQ64
PC68
PC84
CI
CI
CI
CI
CI
CI
CI
CI
CI
CI
CI
CI
C
C
C
C
C
C
C
C
CI
CI
CI
CI
CI
C
CI
CI
CI
CI
CI
C
CI
CI
CI
CI
CI
C
C
C
C
C
C
C
C
C
C
PGA
PQFP
PLAST.
132
TQFP
144
TOPPLAST. BRAZED PLAST. CERAM. PLAST.
VQFP
CQFP
PGA
PGA
TQFP
160
164
175
176
TOPPLAST. BRAZED PLAST. CERAM. PLAST.
PQFP
CQFP
PGA
PGA
TQFP
208
223
PLAST. CERAM.
PQFP
PGA
PG84 PQ100 TQ100 VQ100 CB100 PP132 PG132 TQ144 PQ160 CB164 PP175 PG175 TQ176 PQ208 PG223
C
C
C
CI
CIMB
CI
C
C
CIMB
CI
CI
CI
CI
C
C
CI
CI
CI
CI
CI
C
C
CI
CI
C
C
C
C
C
C
C
C
C
C
C
C
C
C
CI
CI
CI
CI
CI
CI
CI
CI
CI
CI
CI
CI
CI
CI
CI
C
C
C
C
C
C
C
C
C
MB
C
CI
CI
CI
CIMB
CI
CI
CI
CI
CI
CI
CI
CI
CI
CI
CI
CI
CI
CI
C
C
C
C
C
C
C
C
C
C
C
CI
CI
CI
CIMB
CI
CIMB
CI
CI
CI
CI
CI
CI
CI
CI
CI
CI
CI
CI
C
C
C
C
C
C
C
C
C
C
C
C
C = Commercial = 0° to +85° C
I = Industrial = -40° to +100° C
Parentheses indicate future product plans
2-184
MB
MB
M = Mil Temp = -55° to +125° C
C
B = MIL-STD-883C Class B