XC3000A Logic Cell Array Family Product Specifications Features Description • Enhanced, high performance FPGA family with five The XC3000A family offers the following enhancements over the popular XC3000 family: device types – Improved redesign of the basic XC3000 LCA Family – Logic densities from 1,000 to 6,000 gates – Up to 144 user-definable I/Os The XC3000A family has additional interconnect resources to drive the I-inputs of TBUFs driving horizontal Longlines. The CLB Clock Enable input can be driven from a second vertical Longline. These two additions result in more efficient and faster designs when horizontal Longlines are used for data bussing. • Superset of the industry-leading XC3000 family – Identical to the basic XC3000 in structure, pin out, design methodology, and software tools – 100% compatible with all XC3000, XC3000L, and XC3100 bitstreams – Improved routing and additional features During configuration, the XC3000A devices check the bitstream format for stop bits in the appropriate positions. Any error terminates the configuration and pulls INIT Low. When the configuration process is finished and the device starts up in user mode, the first activation of the outputs is automatically slew-rate limited . This feature, called Soft Startup, avoids the potential ground bounce when all outputs are turned on simultaneously. After start-up, the slew rate of the individual outputs is, as in the XC3000 family, determined by the individual configuration option. • Additional programmable interconnection points (PIPs) – Improved access to longlines and CLB clock enable inputs – Most efficient XC3000-class solution to bus-oriented designs • Advanced 0.8 µ CMOS static memory technology The XC3000A family is a superset of the XC3000 family. Any bitstream used to configure an XC3000 or XC3100 device configures an XC3000A device exactly the same way. – Low quiescent and active power consumption • Performance specified by logic delays, faster than corresponding XC3000 versions • XC3000A-specific features – 4 mA output sink and source current – Error checking of the configuration bitstream – Soft startup starts all outputs in slew-limited mode upon power-up – Easy migration to the XC3400 series of HardWire mask programmed devices for high-volume production. Device XC3020A XC3030A XC3042A XC3064A XC3090A CLBs 64 100 144 224 320 Array 8x8 10 x 10 12 x 12 16 x 14 16 x 20 User I/Os Max 64 80 96 120 144 2-161 Flip-Flops Horizontal Longlines Configurable Data Bits 256 360 480 688 928 16 20 24 32 40 14,779 22,176 30,784 46,064 64,160 XC3000A Logic Cell Array Family Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released device performance parameters, please request a copy of the current test-specification revision. Absolute Maximum Ratings Symbol Description Units VCC Supply voltage relative to GND –0.5 to +7.0 V VIN Input voltage with respect to GND –0.5 to VCC +0.5 V VTS Voltage applied to 3-state output –0.5 to VCC +0.5 V TSTG Storage temperature (ambient) –65 to +150 °C TSOL Maximum soldering temperature (10 s @ 1/16 in.) +260 °C Junction temperature plastic +125 °C Junction temperature ceramic +150 °C TJ Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Operating Conditions Symbol VCC Description Min Max Units Supply voltage relative to GND Commercial 0°C to +85°C junction 4.75 5.25 V Supply voltage relative to GND Industrial -40°C to +100°C junction 4.5 5.5 V VIHT High-level input voltage — TTL configuration 2.0 VCC V VILT Low-level input voltage — TTL configuration 0 0.8 V VIHC High-level input voltage — CMOS configuration 70% 100% VCC VILC Low-level input voltage — CMOS configuration 0 20% VCC TIN Input signal transition time 250 ns At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.3% per °C. 2-162 DC Characteristics Over Operating Conditions Symbol VOH Description Min High-level output voltage (@ IOH = –4.0 mA, VCC min) Max 3.86 Units V Commercial VOL Low-level output voltage (@ IOL = 4.0 mA, VCC min) VOH High-level output voltage (@ IOH = –4.0 mA, VCC min) 0.40 3.76 V V Industrial VOL Low-level output voltage (@ IOL = 4.0 mA, VCC min) VCCPD Power-down supply voltage (PWRDWN must be Low) ICCPD Power-down supply current (VCC(MAX) @ TMAX) ICCO Quiescent LCA supply current in addition to ICCPD* Chip thresholds programmed as CMOS levels 0.40 2.30 Chip thresholds programmed as TTL levels –10 V V 50 µA 500 µA 10 mA +10 µA IIL Input Leakage Current CIN Input capacitance, all packages except PGA175 (sample tested) All Pins except XTL1 and XTL2 XTL1 and XTL2 10 15 pF pF Input capacitance, PGA 175 (sample tested) All Pins except XTL1 and XTL2 XTL1 and XTL2 15 20 pF pF IRIN Pad pull-up (when selected) @ VIN = 0 V (sample tested) IRLL Horizontal Longline pull-up (when selected) @ logic Low 0.02 0.17 mA 3.4 mA * With no output current loads, no active input or Longline pull-up resistors, all package pins at Vcc or GND, and the LCA device configured with a MakeBits tie option. 2-163 XC3000A Logic Cell Array Family CLB Switching Characteristic Guidelines CLB Output (X, Y) (Combinatorial) T ILO 1 CLB Input (A,B,C,D,E) 2 T ICK 3 T CKI CLB Clock 12 TCL 11 T CH 4 TDICK 5 TCKDI 6 T ECCK 7 TCKEC CLB Input (Direct In) CLB Input (Enable Clock) 8 TCKO CLB Output (Flip-Flop) CLB Input (Reset Direct) 13 TRPW 9 T RIO T CLB Output (Flip-Flop) X5424 Buffer (Internal) Switching Characteristic Guidelines Description Speed Grade -7 -6 Symbol Max Max Units Global and Alternate Clock Distribution* Either: Normal IOB input pad through clock buffer to any CLB or IOB clock input Or: Fast (CMOS only) input pad through clock buffer to any CLB or IOB clock input TPID 7.5 7.0 ns TPIDC 6.0 5.7 ns TBUF driving a Horizontal Longline (L.L.)* I to L.L. while T is Low (buffer active) T↓ to L.L. active and valid with single pull-up resistor T↓ to L.L. active and valid with pair of pull-up resistors T↑ to L.L. High with single pull-up resistor T↑ to L.L. High with pair of pull-up resistors TIO TON TON TPUS TPUF 4.5 9.0 11.0 16.0 10.0 4.0 8.0 10.0 14.0 8.0 ns ns ns ns ns BIDI Bidirectional buffer delay TBIDI 1.7 1.5 ns * Timing is based on the XC3042A, for other devices see XACT timing calculator. 2-164 CLB Switching Characteristic Guidelines (continued) Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator. Description Combinatorial Delay Logic Variables A, B, C, D, E, to outputs X or Y FG Mode F and FGM Mode Sequential delay Clock k to outputs X or Y Clock k to outputs X or Y when Q is returned through function generators F or G to drive X or Y FG Mode F and FGM Mode Speed Grade -7 Symbol Min Max Units 5.1 5.6 4.1 4.6 ns ns 8 TCKO 4.5 4.0 ns TQLO 9.5 10.0 8.0 8.5 ns ns TICK 4 6 Hold Time after clock K Logic Variables Data In Enable Clock Reset Direct (RD) RD width delay from RD to outputs X or Y Max TILO 2 Clock Clock High time Clock Low time Max. flip-flop toggle rate Min 1 Set-up time before clock K Logic Variables A, B, C, D, E FG Mode F and FGM Mode Data In DI Enable Clock EC A, B, C, D, E DI EC -6 TDICK TECCK 4.5 5.0 4.0 4.5 3.5 4.0 3.0 4.0 ns ns ns ns 3 5 7 TCKI TCKDI TCKEC 0 1.0 2.0 0 1.0 2.0 ns ns ns 11 12 TCH TCL FCLK 4.0 4.0 113.0 3.5 3.5 135.0 13 9 TRPW TRIO 6.0 TMRW TMRQ 16.0 Global Reset (RESET Pad)* RESET width (Low) delay from RESET pad to outputs X or Y ns ns MHz 5.0 6.0 5.0 ns ns 17.0 ns ns 14.0 19.0 *Timing is based on the XC3042A, for other devices see XACT timing calculator. Notes: The CLB K to Q output delay (TCKO, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than the Data In hold time requirement (TCKDI, #5) of any CLB on the same die. 2-165 XC3000A Logic Cell Array Family IOB Switching Characteristic Guidelines I/O Block (I) T PID 3 I/O Pad Input T PICK 1 I/O Clock (IK/OK) 12 TIOL 11 TIOH I/O Block (RI) 4 13 TRRI TIKRI RESET 5 TOOK 6 TOKO 15 TRPO I/O Block (O) 10 TOP I/O Pad Output (Direct) 7 TOKPO I/O Pad Output (Registered) I/O Pad TS 8 9 TTSON T TSHZ I/O Pad Output X5425 Vcc PROGRAM-CONTROLLED MEMORY CELLS OUT INVERT 3- STATE (OUTPUT ENABLE) OUT OUTPUT SELECT 3-STATE INVERT SLEW RATE PASSIVE PULL UP T O D Q FLIP FLOP OUTPUT BUFFER I/O PAD R DIRECT IN REGISTERED IN I Q Q D FLIP FLOP or LATCH TTL or CMOS INPUT THRESHOLD R OK (GLOBAL RESET) IK CK1 CK2 PROGRAM CONTROLLED MULTIPLEXER = PROGRAMMABLE INTERCONNECTION POINT or PIP 2-166 X3029 IOB Switching Characteristic Guidelines (continued) Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator. Speed Grade Description Symbol -7 Min -6 Max Min Propagation Delays (Input) Pad to Direct In (I) Pad to Registered In (Q) with latch transparent Clock (IK) to Registered In (Q) 4 TPID TPTG TIKRI Set-up Time (Input) Pad to Clock (IK) set-up time 1 TPICK Propagation Delays (Output) Clock (OK) to Pad (fast) same (slew rate limited) Output (O) to Pad (fast) same (slew-rate limited) 3-state to Pad begin hi-Z (fast) same (slew-rate limited) 3-state to Pad active and valid (fast) same (slew -rate limited) 7 7 10 10 9 9 8 8 TOKPO TOKPO TOPF TOPS TTSHZ TTSHZ TTSON TTSON Set-up and Hold Times (Output) Output (O) to clock (OK) set-up time Output (O) to clock (OK) hold time 5 6 TOOK TOKO 8.0 0 7.0 0 11 12 TIOH TIOL FCLK 4.0 4.0 113.0 3.5 3.5 135.0 13 15 15 TRRI TRPO TRPO Clock Clock High time Clock Low time Max. flip-flop toggle rate Global Reset Delays (based on XC3042A) RESET Pad to Registered In (Q) RESET Pad to output pad (fast) (slew-rate limited) 3 4.0 15.0 3.0 14.0 Max Units 3.0 14.0 2.5 ns ns ns 12.0 8.0 18.0 6.0 16.0 10.0 20.0 11.0 21.0 ns 7.0 15.0 5.0 13.0 9.0 12.0 10.0 18.0 24.0 33.0 43.0 ns ns ns ns ns ns ns ns ns ns ns ns MHz 23.0 29.0 37.0 ns ns ns Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). For larger capacitive loads, see page XAPP024. Typical slew rate limited output rise/fall times are approximately four times longer. 2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the internal pull-up resistor or alternatively configured as a driven output or driven from an external source. 3. Input pad set-up time is specified with respect to the internal clock (IK). In order to calculate system set-up time, subtract clock delay (pad to IK) from the input pad set-up time value. Input pad holdtime with respect to the internal clock (IK) is negative. This means that pad level changes immediately before the internal clock edge (IK) will not be recognized. 4. TPID, TPTG, and TPICK are 3 ns higher for XTL2 when the pin is configured as a user input. 2-167 XC3000A Logic Cell Array Family For a detailed description of the device architecture, see pages 2-105 through 2-123. For a detailed description of the configuration modes and their timing, see pages 2-124 through 2-132. For detailed lists of package pin-outs, see pages 2-140 through 2-150. For package physical dimensions and thermal data, see Section 4. Ordering Information XC3020A-6PC84C Example: Device Type Temperature Range Block Delay Number of Pins Package Type Component Availability 44 PINS TYPE CODE XC3020A XC3030A XC3042A XC3064A XC3090A -7 -6 -7 -6 -7 -6 -7 -6 -7 -6 64 68 84 100 PLAST. PLCC PLAST. VQFP PLAST. PLCC PLAST. PLCC CERAM PLAST. PGA PQFP PC44 VQ64 PC68 PC84 PG84 CI CI CI C C C C PLAST. TQFP 132 144 TOPPLAST. BRAZED PLAST. CERAM. PLAST. VQFP CQFP PGA PGA TQFP 160 164 175 176 TOPPLAST. BRAZED PLAST. CERAM. PLAST. PQFP CQFP PGA PGA TQFP 208 PLAST. CERAM. PQFP PGA PQ100 TQ100 VQ100 CB100 PP132 PG132 TQ144 PQ160 CB164 PP175 PG175 TQ176 PQ208 PG223 CI CI CI CI CI CI CI C C C C C C C CI CI CI CI CI CI C C C C C C C CI CI CI CI C C C C CI CI CI C CI CI CI CI CI CI C C C C C C Commercial == 0° 0° to to +85° +70° C C CC==Commercial 223 Industrial = -40° to +100° +85° CC II == Industrial 2-168 M= Temp = -55° to +125° C C MMil = Mil Temp = -55° to +125° B =BMIL-STD-883C Class B B = MIL-STD-883C Class