Obsolescence Notice This product is obsolete. This information is available for your convenience only. For more information on Zarlink’s obsolete products and replacement product lists, please visit http://products.zarlink.com/obsolete_products/ MGCT04 Transmit Circuit for TDMA/AMPS and CDMA/AMPS Preliminary Information Features • • • • • • DS5424 Dual RF Ports for 900MHz and 1900MHz AGC Amplifier with 90dB of Variable Gain, Fully Compensated for Temperature On-chip Active Filter. Removes the Requirement for External IF SAW Filter High Power 900MHz and 1900MHz Output Stages Quadrature Modulator Small Scale MLF Package Applications • • Transmit Modulator and Up-converter in TDMA/ AMPS Mobile Phones Transmit Up-converter in CDMA/AMPS Mobile Phones The MGCT04 circuit is designed for use in dual band, dual mode cellular 900MHz/PCS1900MHz CP2 CP1 CP0 23 5 8 ISSUE 1.1 March 2001 Ordering Information MGCT04/KG/LH1S MGCT04/KG/LH1T mobile phones. It can be used for both TDMA/AMPS or CDMA/AMPS systems. The MGCT04 is compatible with baseband and mixed signal interface circuits from Zarlink Semiconductor and other manufacturers. System costs have been kept to a minimum by removing the requirement for an additional SAW filter in the transmit IF path. The AGC has been split between RF and IF sections to reduce noise and a low pass filter has been included before the IF variable gain amplifier to remove spurious products produced in the modulator. LO 2GHz LO 1GHz 19 21 UHF OSCILLATOR INPUT SELECT CONTROL LOGIC Q IN Q IN I IN I IN 13 1900 MHz OUTPUT DRIVER POWER CONTROL 14 26 PHASE SHIFT 15 RF VGA ALL PASS PHASE SHIFT NETWORK IF VGA ÷2/4 AND 27 28 1 3 16 2 SSB MIXER DIV 7 OUT ÷8 VCO BUFFER RF190 RF190 RFDEG1 RFDEG2 RF900 RF900 900 MHz OUTPUT DRIVER VGA CONTROL OSC BUFFER VREF BIAS BUFFER 9 VHF OSC IN 10 VHF OSC BIAS 22 AGC Figure 1 - MGCT04 Block Diagram 1 MGCT04 Preliminary Information 21 15 22 14 28 8 1 Note: Corner Pads are connected to ground 7 Figure 2 - Pin Connections - top view Pin Signal Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 RF DEG2 RF 900B RF 900 RF GND CP0 VCO GND DIV OUT CP2 VHF OSC IN VHF OSC BIAS VCO VCC GND Q IN Q INB I IN I INB VCC UHF VCC LO 2GHZ GND UHF LO 1GHZ AGC CP1 RF VCC RF GND RF 1900B RF 1900 RF DEG1 Function Connection to external inductor to control gain of power amplifiers Inverse output from 900MHz differential output driver Output from 900MHz differential output driver Ground to RF circuits Control pin 0. See tables 2 & 3 for function Ground for VHF oscillator Output from VHF oscillator divided by 8 Control pin 2. See tables 2 & 3 for function Input from external VHF oscillator Switched bias voltage for external VHF oscillator Positive supply to VHF oscillator Ground Q +input Q -input I +input I -input Positive supply Positive supply to UHF LO input buffers 2GHz local oscillator input Ground to UHF oscillator input buffers 1GHz local oscillator input Control voltage for IF and RF variable gain amplifiers Control pin 1. See tables 2 & 3 for function Positive supply to RF circuits Ground to RF circuits Inverse output from 1900MHz differential output driver Output from 1900MHz differential output driver Connection to external inductor to control gain of power amplifiers Table 1 - Pin Assignments 2 Preliminary Information MGCT04 Absolute Maximum Ratings Supply voltage (VCC) Control input voltage Storage temperature, TSTG 4V -0.6V to VCC + 0.6V -55˚C to +125˚C Operating temperature -40˚C to 100˚C Max Junction Temperature (TJ) 150˚C Electrical Characteristics Test conditions (unless otherwise stated): Tamb = -30°C to +70°C, VCC = 2·7V to 3·6V. UHF LO level = -15dBm (both bands), I, Q input = 1.4 volts p.p, test frequency = 849MHz (900 output) and 1910MHz (1900 output).These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. Value Characteristics Units Min. Supply current Sleep current Standby mode Standby Mode - Prescaler disabled Total supply current Standby to operating mode switching time Logic inputs Logic high voltage Logic low voltage Typ. 75 10 µA mA mA All circuits off See Tables 4 and 5 Pin 7 connected to VCC 160 10 mA µs Maximum power PCS mode VCC 0·8 V V 8 4 118 VCC -0.6 0 Conditions Max. Table 2 - DC Characteristics Value Characteristics Units Min. Typ. Max. 1.0 1.4 2.0 Conditions I and Q modulator I and Q input voltage level I and Q common mode voltage 1.2 Vpp Differential V I and Q differential input resistance 13.5 kΩ I and Q input bandwidth 2.5 MHz IF Vector offset 25 dB Pout = +8dBm SSB rejection 30 dB Pout = + 8dBm VHF oscillator input and divider Input drive level 22 VHF oscillator bias voltage Output level from prescaler Prescaler divide ratio 40 1.2 400 70 mVrms From external VHF osc. via matching network V mVpp 8 6pF load Drive output for synthesiser Table 3 - AC Characteristics 3 MGCT04 Preliminary Information Value Characteristics Units Min. Typ. Conditions Max. Variable gain amplifiers IF amp. operating frequency range 50 200 MHz RF amp. operating frequency range 750 2000 MHz Overall gain control range 84 Control voltage for minimum gain 0.1 90 Voltage gain V Control voltage for maximum gain AGC control voltage slope dB 33 2.6 V 60 dB/V SSB mixer and UHF oscillator inputs Cellular band LO input level -15 -10 -5 dBm From external UHF osc. via matching network PCS band LO input level -15 -10 -5 dBm From external UHF osc. via matching network Cellular band local oscillator input frequency. (LO 1GHz) 850 1100 MHz PCS band local oscillator input frequency (LO 2GHz) 1500 2150 MHz 900MHz RF output stage Specifications assume 50 ohm load driven via a matching network (Fig. 6) RF amplifier operating frequency range 824 849 MHz Output power +8 +19 dBm Note 1 ACPR (CDMA) -66 -52 dBc Pout = +3dBm Vcc = 3V ACPR (TDMA) -45 -30 dBc Pout = +8dBm, Offset = 30kHz Vcc = 3V -90 -60 dBc Pout = +8dBm, Offset = 60kHz Vcc = 3V +19 dBm Note 2 dBm/ Hz At duplex frequency, offset 45MHz Pout = +3dBm ftx = 849 MHz Pout = +8dBm Output power AMPS +10 +14 Receive band noise -128 Receive band noise (869 - 894MHz) -123 121 dBm/ Hz LO Leakage -30 -20 dBc Pout = +8dBm Image Rejection -30 -20 dBc Pout = +8dBm -20 dBm Note 3 Spurious Outputs Other Spurii Table 3 - AC Characteristics (continued) 4 Preliminary Information MGCT04 Value Units Characteristics Min. Typ. 1900MHz RF output stage (PCS) RF amplifier operating frequency range Conditions Max. Specifications assume 50 ohm load driven via a matching network (Fig. 5) 1850 1910 MHz Output power +8 +18 dBm Note 1 ACPR (CDMA) -66 -52 dBc Pout = +3dBm Vcc = 3V ACPR (TDMA) -45 -30 dBc Pout = +8dBm, Offset = 30kHz Vcc = 3V -90 -60 dBc Pout = +8dBm, Offset = 60kHz Vcc = 3V Receive band noise -128 dBm/ Hz At duplex frequency, offset 80MHz Pout = +3dBm Receive band noise (1930 - 1990 MHz) -123 -121 dBm/ Hz ftx = 1910MHz, Pout = +8dBm LO Leakage -30 -20 dBc Pout = +8dBm Image Rejection -30 -20 dBc Pout = +8dBm -20 dBm Note 3 Spurious Outputs Other Spurii Table 3 - AC Characteristics (continued) Notes: 1. V (I/Q) = 1.4V differential, VHF LO = 22mV rms, UHF LO = -15dBm, VGA = 2.6volts 2. V (I/Q) = 1.4 V dc differential, VHF LO = 22mV rms, UHF LO = -15dBm, VGA = 2.6 volts 3. Frequency range 10MHz to 10*ftx except Rx and Tx bands Circuit Description General The MGCT04 circuit is designed to provide the transmit function in dual band dual mode CDMA/ AMPS IS136/AMPS mobile phones. The circuit contains the following blocks: 1. Quadrature modulator 2. VHF voltage controlled oscillator buffer and divide by 8 prescaler 3. Active IF low pass filter 4. IF variable gain amplifier 5. Single sideband mixer with external UHF oscillator inputs 6. RF variable gain amplifier 7. 900MHz and 1900MHz high power output driver stages 8. Power and mode control logic Quadrature Modulator I and Q data from a baseband circuit such as the Zarlink Semiconductor MGCM02 or MGCM03 circuit is applied to the I and Q inputs of the quadrature modulator to produce the intermediate frequency by mixing with the local oscillator frequency from the VHF VCO. The control inputs can select either a divide by two or divide by four function between the VHF VCO and the quadrature modulator giving a choice of possible intermediate frequencies. VHF Oscillator Input Oscillator Bias and Divider An external VHF oscillator circuit is AC coupled to the VHF oscillator input. The oscillator drives the quadrature modulator and an internal divide by eight circuit to reduce the frequency of the output signal to be sent off chip to the frequency synthesiser. This reduces the power required in the output buffer circuit and also allows a low frequency low power CMOS synthesiser to be used. The divider can be disabled if not required by connecting the output pin (DIV OUT - pin 7) to the positive power supply. This reduces the total supply current by typically 4mA. An oscillator bias circuit is included on the chip so that the external VHF oscillator transistor can be switched off using the control inputs. The bias voltage is 5 MGCT04 Preliminary Information switched off in either of the sleep conditions shown in Tables 4 and 5. filter to be used for both 900MHz and 1900MHz bands. Active Low Pass Filter RF Variable Gain Amplifier The output from the quadrature modulator is passed to the active low pass filter which attenuates wide band noise and spurious outputs. The SSB mixer is followed by the RF variable gain amplifier stage which provides about 23dB of the total gain variation. An additional SAW filter in the transmit path is avoided by providing the gain variation after the mixer. IF Variable Gain Amplifier The filtered IF signal is passed to the IF variable gain amplifier which in turn drives the single sideband mixer. An externally applied AGC control voltage allows the total circuit gain to be varied over a minimum 84dB range. The AGC action is split between the IF and RF portions of the circuit and an internal AGC control circuit processes the external AGC control voltage to drive both IF and RF variable gain amplifiers and provides a near linear control characteristic over the entire AGC range. Single Sideband Mixer The modulated IF signal is fed to the single sideband mixer which up-converts the IF to the RF frequency to be transmitted by mixing with an RF signal from one of two external UHF oscillator input pins, seiected by an on chip multiplexer. When 1900MHz mode is programmed with the VHF oscillator in divide by four mode (Tables 4 and 5), the polarity of the quadrature oscillator drive signals to the single sideband mixer are reversed, thus selecting a low side LO for 1900MHz PCS and high side for 900MHz. This technique allows a common IF and The variable gain amplifier control circuit ensures that the attenuation from maximum power is initially controlled by the RF variable gain stage thus reducing the noise contribution from the RF mixer. Output Drivers Separate output drive stages are provided for 900MHz and 1900MHz operation. A differential design is used for both amplifiers to improve power efficiency and to ease power supply decoupling problems. The 900MHz output stage provides a linear output of 3 to 5 dBm for CDMA and 8 dBm for TDMA operation, but is over-driven in AMPS mode to obtain a typical output of 11dBm. In both power driver stages the DC current is backed off as the RF and IF gain is reduced, improving efficiency when less than maximum output power is required. Control Inputs Three control inputs are provided to select different operating modes for the chip; the various modes selected by the control pins are shown in Tables 4 and 5. CP2 CP1 CP0 Function 0 0 0 Sleep mode. All circuits powered down 0 0 1 Quadrature modulator on. 1900MHz mode. Low side UHF LO. IF = VHF VCO ÷ 4 0 1 0 Quadrature modulator on. 900MHz mode. high side UHF LO. IF = VHF VCO ÷ 4 0 1 1 Standby mode. VHF oscillator input buffer, oscillator bias and divider on. All other circuits powered down Table 4 - Control pin functions; VHF LO in divide-by-four mode CP2 CP1 CP0 Function 1 0 0 Sleep mode. All circuits powered down 1 0 1 Quadrature modulator on. 1900MHz mode. High side UHF LO. IF = VHF VCO ÷ 2 1 1 0 Quadrature modulator on. 900MHz mode. high side UHF LO. IF = VHF VCO ÷ 2 1 1 1 Standby mode. VHF oscillator input buffer, oscillator bias and divider on. All other circuits powered down Table 5 - Control pin functions; VHF LO in divide-by-two mode 6 MGCT04 Preliminary Information VCC VCC VCC INPUT 1.85k 400k 600 OSC BIAS 800k DIV OUT VREF 1.2V Figure 3a - Control inputs CP0, CP1 and CP2 1.85k 2.5mA 0.5mA Figure 3b - Oscillator bias buffer Figure 3c - Divider ouput circuit VCC VCC 550 2.7k 550 2.7k VOUT− VOUT+ VBIAS VBIAS 10k 10k VHF OSC INPUT 4k5 4k5 LO2GHz LO1GHz 100 100 4p 540µA 1.6mA Figure 3d - VHF oscillator input buffer RF900 V CC RF900 VBIAS Figure 3e - LO2GHz and LO1GHz oscillator inputs RF1900 RF1900 VCC VBIAS RFDEG2 RFDEG1 Figure 3f - 900MHz and 1900MHz outputs 10k I IN/Q IN VCC 80k VCC TO QUAD MOD 27k VBIAS 1 AGC IN 27k 80k I IN/Q IN TO QUAD MOD 44k VBIAS 2 2.0p 10k Figure 3g - I and Q inputs Figure 3h - AGC input 7 MGCT04 Preliminary Information 1GHz LO 1900MHz power amplifier 1900MHz SAW filter 2GHz LO Vcc CONTROL MICROPROCESSOR 1900MHz matching network 1900MHz diplexer AGC 900MHz matching network 900MHz diplexer 1 900MHz power amplifier 900MHz SAW filter 28 External VHF oscillator 22 21 MGCT04 Oscillator control 7 VHF SYNTHESISER 8 15 14 MIXED SIGNAL INTERFACE CIRCUIT Oscillator out Oscillator bias Vee Figure 4 - Typical application circuit VCC 50Ω SAW FILTER C3 1.2p C1 1.2p L1 15n VCC 50Ω SAW FILTER L2 15n C3 1.5p C1 100p L1 68n PIN 27 L5 5.6n L4 5.6n L3 3.9n PIN 3 L5 22n L4 22n PIN 26 C4 1.2p 8 C2 1.2p L2 68n L3 22n PIN 2 C4 1.5p C2 100p NOTE L1 and L2 are required to provide a DC feed to the output pins and do not form part of the matching network NOTE L1 and L2 are required to provide a DC feed to the output pins and do not form part of the matching network Figure 5 - Typical 1900MHz output matching network Figure 6 - Typical 900MHz output matching network Preliminary Information MGCT04 MGCT04 VCO control voltage VHF OSC IN (9) Frequency Synthesizer VHF OSC BIAS (10) DIV OUT (7) Vee Figure 7 - Typical circuit showing connection of external VHF oscillator 10n 3n3 68p 2n2 Pin 21 2p 5p6 Pin 19 b) UHF LO 2GHz a) UHF LO 1GHz 4n7 39n Pin 9 8P Note: Test signal generator impedance is 50 ohms in each case c) VHF LO Figure 8 - LO Input Test Circuits 9 For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. 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