HD155101BF RF Single-chip Linear IC for GSM and EGSM Systems ADE-207-256A (Z) 2nd Edition September 1998 Description The HD155101BF was developed for GSM and EGSM cellular systems, and integrates most of the functions of a transceiver. The HD155101BF incorporates the bias circuit for a RF LNA, a 1st mixer, 1stIF amplifier, 2nd mixer, AGC amplifier and an IQ quadrature demodulator for the receiver, and an IQ quadrature modulator and offset PLL for the transmitter. Also, on chip are the dividers for the 1st & 2nd local oscillator signals and 90˚ phase splitter. Moreover the HD155101BF includes control circuits to implement power saving modes. These functions can operate down to 2.7 V and are housed in a 48-pin LQFP SMD package. Hence the HD155101BF can form a small size transceiver handset for GSM and EGSM by adding a PLL frequency synthesizer IC, a power amplifier and some external components. See page 7 “Configuration”. The HD155101BF is fabricated using a 0.6 µm double-polysilicon Bi-CMOS process. Functions Receiver (RX) • • • • • • Low Noise Amplifier (LNA) bias circuit 1st mixer IF amplifier 2nd mixer Automatic gain control amplifier (AGC) IQ demodulator with 90° phase splitter Transmitter (TX) • IQ modulator with 90° phase splitter • Offset PLL Down converter Phase comparator TX VCO driver HD155101BF Others • IF dividers • Power saving circuit • IFVCO Features • Highly integrated RF processing for hand-portables • Wide operating frequency RX: RF: 925 to 960 MHz 1st IF: 130 to 300 MHz 2nd IF: 26 to 60 MHz TX: RF: 880 to 915 MHz IF: 156 to 360 MHz • Offset PLL architecture reduces TX spurious • Low current consumption (Vcc = 3 V) RX mode: 42.5 mA Typ (including IFVCO current (2.5 mA Typ)) + LNA transistor current (5.6 mA Typ) TX mode: 38.0 mA Typ (including IFVCO current (2.5 mA Typ)) Idle mode: 1 µA Typ • Operating supply voltage: Phase comparator and TX VCO driver circuits: 2.7 to 5.25 V Other blocks: 2.7 to 3.6 V • Operating temperature range: –20 to +85°C • 48 pin SMD Low Profile Quad Flat Package (LQFP): FP-48 2 HD155101BF Pin Arrangement MIX1IN MIX1INB GNDMIX1 VCCMIX1 RFLOIN MIX1OUTB MIX1OUT VCCIF GNDIF IFIN IFINB MIX2O The HD155101BF is housed in a 48-pin LQFP SMD package to which is suitable for applications where space is limited. “Pin Functions” shows the arrangement and roles assigned for each pin of the HD155101BF. 48 47 46 45 44 43 42 41 40 39 38 37 VCCLNA 4 33 AGCOUT GNDLNA 5 32 AGCOUTB RFIN 6 31 VCCDIV POONTX 7 30 GNDDIV VCCPLL 8 29 VCONT GNDPLL 9 28 IOUT VCOIN 10 27 IOUTB VCCCOMP 11 26 QOUT PLLOUT 12 13 14 15 16 17 18 19 20 21 22 23 25 24 IFVCOI VCCAGC IFVCOO 34 GNDIQ 3 IFLO RFOUT VCCIQ GNDAGC MOD 35 MODB 2 IIN POONRX2 IINB MIX2OB QIN 36 QINB 1 ICURAD POONRX1 QOUTB (Top View) 3 HD155101BF Pin Functions Pin No. Symbol Input/ Output Meaning of symbol Function 1 POONRX1 Input POwer ON for RX1 If ‘H’, LNA and MIX1 are active. Other receiver blocks don’t care. 2 POONRX2 Input POwer ON for RX2 LNA and MIX1 don’t care. If ‘H’, Other receiver blocks are active. 3 RFOUT Output RF signal OUTput Open collector type output of LNA. The collector of LNA transistor. 4 VCCLNA Vcc VCC of LNA block Power supply of LNA 5 GNDLNA Gnd GND of LNA block Ground of LNA 6 RFIN Input RF signal INput Input of LNA. The base of LNA transistor 7 POONTX Input POwer ON for TX If ‘H’, the blocks for transmitter are active. The reciver blocks don’t care. 8 VCCPLL Vcc VCC of O PLL block Power supply for offset PLL except phase comparator 9 GNDPLL Gnd GND of O PLL block Ground of offset PLL 10 VCOIN Input VCO signal INput Input of Tx. VCO signal 11 VCCCOMP Vcc VCC of phase COMParator Power supply for just phase comparator of offset PLL 12 PLLOUT Output OPLL OUTput Current output to control and modulate Tx. VCO This pin should be connected external loop filter. 13 ICURAD Input I CURrent AD just This pin should be connected an external R to determine charge pump current of phase comparator 14 QINB Input Q signal INput Bar Q negative signal input of IQ quadrature modulator 15 QIN Input Q signal INput Q positive signal input of IQ quadrature modulator 16 IINB Input I signal INput Bar I negative signal input of IQ quadrature modulator 17 IIN Input I signal INput I positive signal input of IQ quadrature modulator 18 MODB Output MODulator output Bar Negative output of IQ quadrature modulator 19 MOD Output MODulator output Positive output of IQ quadrature modulator 20 VCCIQ Vcc VCC of IQ block Power supply of IQ block 21 IFLO Input/ Output IF LOcal signal input/output IF local signal input to be fed to divider 22 GNDIQ Gnd GND of IQ block Ground of IQ block 23 IFVCOO Output IFVCO Output Emitter of IFVCO transistor 24 IFVCOI Input IFVCO I nput Base of IFVCO transistor 4 HD155101BF Pin Function (cont) Pin No. Symbol Input/ Output Meaning of symbol Function 25 QOUTB Output Q signal OUTput Bar Q negative signal output of IQ quadrature demodulator 26 QOUT Output Q signal OUTput Q positive signal output of IQ quadrature demodulator 27 IOUTB Output I signal OUTput Bar I negative signal output of IQ quadrature demodulator 28 IOUT Output I signal OUTput I positive signal output of IQ quadrature demodulator 29 VCONT Input Voltage of AGC CONTrol The DC voltage input to control the power gain of AGC 30 GNDDIV Gnd GND of DIVider block Ground of divider to make IF local signals 31 VCCDIV Vcc VCC of DIVider block Power supply of divider to make IF local signals 32 AGCOUTB Output AGC OUTput Bar AGC negative signal output to be fed to IQ quadrature demodulator 33 AGCOUT Output AGC OUTput AGC positive signal output to be fed to IQ quadrature demodulator 34 VCCAGC Vcc VCC of AGC block Power supply of AGC 35 GNDAGC Gnd GND of AGC block Ground of AGC 36 MIX2OB Output MIX2 Output Bar 2nd mixer (MIX2) negative signal output to be fed to AGC 37 MIX2O Output MIX2 Output 2nd mixer (MIX2) positive signal output to be fed to AGC 38 IFINB Input 1stIF signal INput Bar IFAMP negative signal input for 1st IF signal 39 IFIN Input 1stIF signal INput IFAMP positive signal input for 1st IF signal 40 GNDIF Gnd GND of IFMIX2 block Ground of IFAMP and 2nd mixer (MIX2) 41 VCCIF Vcc VCC of IFMIX2 block Power supply of IFAMP and 2nd mixer (MIX2) 42 MIX1OUT Output MIX1 Output 1st mixer (MIX1) positive signal output 43 MIX1OUTB Output MIX1 Output Bar 1st mixer (MIX1) negative signal output 44 RFLOIN Input RF LOcal signal INput RF 1st local signal input to be fed to 1st mixer (MIX1) and the down converter of offset PLL 45 VCCMIX1 Vcc VCC of MIX1 block Power supply of 1st mixer (MIX1) 46 GNDMIX1 Gnd GND of MIX1 block Ground of 1st mixer (MIX1) 47 MIX1INB Input MIX1 I nput Bar 1st mixer (MIX1) negative signal input 48 MIX1IN Input MIX1 I nput 1st mixer (MIX1) positive signal input 5 RFIN 9 8 7 6 11 PLLOUT 12 VCCCOMP Tx.VCO VCOIN 10 902 MHz GNDPLL VCCPLL *1 POONTX 947 MHz 4 GNDLNA 5 VCCLNA MIX1INB 14 GNDMIX1 270 MHz MIX1IN 902 MHz 13 Phase detector Vref (PLL) 1172 MHz 0 to 100 kHz QINB 16 44 MIX1OUTB 17 18 ÷2 (90 deg) VCCIF 41 40 IFIN ÷3 20 21 ÷2 22 38 23 Linearizer Vref (Div, Rx) ÷2, ÷12 39 IFLO To Synth. Vref (AGC) 45 MHz ÷2 (90 deg) 19 GNDIF 270 MHz Vref Vref (IF) (Mix2) ÷2 42 Vref (Demod) *2 Bias generator 43 IFINB MIX2O 37 24 IFVCO Bias Circuit Notes: 1. H = Active, L = Off All biases are H active 2. When POONRX1 = ‘H’ and POONRX2 = ‘L’, bias generator will be off. When Bias generator is off, all circuits will be off. 15 VCCMIX1 Vref (Mod) Vref (Div, Tx) ÷2(90 deg) *2 RFLOIN 1172 MHz 270 MHz RFOUT 3 Vref (Mix1) 0 to 100 kHz QIN 45 0 to 100 kHz IINB 1172 MHz 0 to 100 kHz IIN 46 MODB LNA Vref Bias (LNA) Circuit ICURAD MIX1OUT 540 MHz 47 MOD 48 VCCIQ *1 POONRX1 1 *1 POONRX2 2 IFLO 947 MHz GNDIQ 225 MHz IFVCOO 6 VCONT GNDDIV VCCDIV AGCOUTB AGOUT 45 MHz VCCAGC GNDAGC MIX2OB Vtune QOUTB 0 to 100 kHz 25 QOUT 0 to 100 kHz 26 IOUTB 0 to 100 kHz 27 IOUT 0 to 100 kHz 28 29 30 31 32 33 34 35 36 45 MHz IFVCOI 947 MHz HD155101BF Block Diagram Configuration 225 MHz 925 to 960 MHz LNA RF filter RF SAW filter 45 MHz IF SAW filter LC filter AGC bias circuit I Q 45 MHz 270 MHz 1150 to 1185 MHz TCXO 13 MHz I&Q Demo. Dual PLL1 synth. RF VCO IFVCO ÷2 HD155101BF 90 deg Shift ÷2 ÷6 PLL2 B.B. Block 540 MHz HD155017T 90 deg Shift ÷2 LPF 270 MHz 270 MHz 270 MHz HPA Module Loop filter buffer Phase Detector I&Q Mod I Q 880 to 915 MHz HD155101BF 7 PA 902 MHz Tx.VCO ALC RFIN 9 8 7 6 PLLOUT 12 VCCCOMP 11 VCOIN 10 GNDPLL VCCPLL POONTX 947 MHz GNDLNA 5 VCCLNA 4 RFOUT 3 POONRX2 2 MIX1IN 13 Phase detector Vref (PLL) 14 LNA Vref Bias Circuit (LNA) 902 MHz POONRX1 1 GNDMIX1 15 Vref (Mix1) 44 Vref (Div, Tx) ÷2(90 deg) 16 Vref (Mod) VCCMIX1 QIN RFLOIN 43 17 18 ÷2 (90 deg) Vref 41 19 20 ÷2 (90 deg) ÷3 21 ÷2 38 IFINB 22 Vref (Div, Rx) ÷2, ÷12 23 Linearizer 39 IFIN Vref (AGC) 45 MHz 270 MHz 40 GNDIF Vref Vref (IF) (Mix2) ÷2 42 (Demod) *2 Bias generator 1172 MHz 270 MHz MIX1INB ICURAD 45 IINB 1172 MHz MIX1OUTB IIN 46 MODB 1172 MHz 270 MHz QINB MIX1OUT 540 MHz VCCIF MOD 47 VCCIQ 48 IFLO 947 MHz GNDIQ 225 MHz 24 37 MIX2O IFVCOO 8 QOUTB 25 QOUT 26 IOUTB 27 IOUT 28 VCONT 29 GNDDIV 30 VCCDIV 31 AGCOUTB 32 AGOUT 45 MHz 33 VCCAGC 34 GNDAGC 35 MIX2OB 36 45 MHz IFVCOI 947 MHz VHF(IF) PLL Synth. Base Band Interface Processing UHF(RF) PLL Synth. DAC 10 bit DAC 10 bit ADC 12 bit DAC 10 bit ADC 12 bit Dual PLL synth. 13 MHz Base Band System Controller & Physical Layer Processor DAC 10 bit HD155101BF A GSM Application Example HD155101BF Functional Operation The HD155101BF has been designed from system stand point and incorporated a large number of the circuit blocks necessary in the design of a digital cellular handset. Receiver Operation The HD155101BF incorporates a LNA bias circuit for an external RF transistor, whose NF and power gain can be better selected. This circuit amplifies the RF signal after selection by the antenna filter before the signal enters the first mixer section. The RF signal is combined with a high side local oscillator (LO) signal to generate a wanted first IF signal in the 130 to 300 MHz range. The 1st mixer circuit uses a double-balanced Gilbert cell architecture, which has open collector differential outputs. If, at 225 MHz, a 800 Ω LC load is connected to the mixer’s outputs then a SSB NF of 9.0 dB with a gain of 7.0 dB is realizable. The corresponding input compression point is –11 dBm, which allows the device to be used within a GSM and EGSM system. A filter is used after the 1st mixer to provide image rejection and the conditioned signal is then passed through an intermediate amplifier, before being down converted to a second IF in the range of 26 to 60 MHz. The second mixer can generate a 45 MHz 2nd IF, if a 270 MHz 2nd LO signal is used. The 2nd LO is obtained by dividing the IFLO signal by 2. The 2nd mixer also uses the Gilbert cell architecture, but with internal resistive differential outputs of 300 Ω. IF amplifier and second mixer has a SSB NF of 5.6 dB, a power gain of 12 dB and an input compression point of –25 dBm. In order to improve the blocking characteristics of the device an external LC resonator across the differential outputs of the second mixer is recommended. The signal is then passed to the AGC circuit, which has a dynamic range of more than 80 dB (–42 dB to +55 dB Typ) and is controlled by a DC voltage, which is generated by the microprocessor. This DC control range is from 0.15 V to 2.3 V. The AGC, which is designed for the GSM system, provides a linearity of ±1.0 dB in any 20 dB window. The outputs of the AGC are 2 kΩ differential and are connected the external supply via inductors. The signal is then down converted by a demodulator to I and Q. Internal divider circuits convert the IFLO signal to the same frequency as the 2nd IF before passing this local signal through a phase splitter / shifter in order to generate the in phase and quadrature IQ components. The phase accuracy of the IQ demodulator is < ±1° and the amplitude mismatch is < ±0.5 dB. In order to accommodate different baseband interfaces the HD155101BF IQ differential outputs have a voltage swing of 2.4 Vp-p and a DC offset of < ±60 mV. Within each output stage a 2nd order Butterworth filter (fc = 210 kHz), is used to improve the blocking performance of the device. In order to allow flexibility in circuit implementation the HD155101BF can configured to use either a single-ended or balanced external circuitry and components. 9 HD155101BF LNA Vref Poutput 3 Vcc Pinput RFOUT VCCLNA LNA bias GNDLNA circuit 5 4 6 RFIN Figure 1 LNA Bias Circuit Transmitter Operation The transmitter chain converts differential IQ baseband signals to a suitable format for transmission by a power amplifier. The common mode DC voltage range of the modulator inputs is 0.8 to 1.2 V and they have 2.4 Vp-p Max differential swing. The modulator circuit uses double-balanced mixers for the I and Q paths. The LO signals are generated by dividing the IFLO signal by 2 and then passing them through a phase splitter / shifter. The IF signals generated are then summed and produce a single modulated IF signal which is amplified and fed into the offset PLL block. Carrier suppression due to the mixer circuit is better than 31 dBc. However, if the common mode DC voltage of the I and Q inputs is adjusted, carrier suppression can be improved better than 40 dBc easily. In addition, upper side-band suppression is better than 35 dBc. Within the offset PLL block there is a down converter, a phase comparator and a VCO driver. The down converter mixes the 1st LO signal and the TX VCO to create a reference LO signal for use in the offset PLL circuit. The phase comparator and the VCO driver generate an error current, which is proportional to the phase difference between the reference IF and the modulated IF signals. This current is used in a 2nd order loop filter to generate a voltage, which in turn modulates the TX VCO. In order to optimize the PLL loop gain, the error current value can be modified by changing the value of an external resistor - ICURAD. In order to accommodate a range of TX VCO, the offset PLL circuit has been designed to operate with a supply voltage of up to 5.25 V. Operating Modes The HD155101BF has the necessary control circuitry to implement the necessary states within the GSM system. Also provided is a power save mode which reduces the current consumption of the device by powering down unnecessary function blocks. Three pins are assigned for mode control, POONRX1, POONRX2 and POONTX. Table 1 shows the relationship between the pins and the required operating mode. Control of these pins are by the system controller. As per GSM requirements the TX and RX sections are not on at the same time. For the receiver there is a calibration mode for which the LNA bias circuit and 1st mixer are switched off. During this period the gain of the AGC can be adjusted. Also the DC offsets of the IQ demodulator are measured and subsequently canceled. In order to change between the RX and TX modes a state called “warm-up” is used to ensure that the LO signals are not unduly affected. This method of switching between TX and RX ensures that lock is achieved first time. 10 HD155101BF Power saving is implemented through use of the idle mode. All function blocks of the HD155101BF are switched off until such time as the system controller commends the device to power up again. Table 1 Operating Modes with Power Saving Receive (Rx) Calibrate (Cal) Warm-up (Lo-ON) Transmit (Tx) Idle (PS) Mode POONRX1 (pin 1) H L L L H switch POONRX2 (pin 2) H H L L L POONTX (pin 7) L L L H Don’t care HD155101BF LNA bias ON OFF OFF OFF OFF circuit status 1st mixer ON OFF OFF OFF OFF IF AMP ON ON OFF OFF OFF 2nd mixer ON ON OFF OFF OFF AGC ON ON OFF OFF OFF IO demodulator ON ON OFF OFF OFF Divider (Rx.) ON ON OFF OFF OFF Divider (Tx.) OFF OFF OFF ON OFF IO modulator OFF OFF OFF ON OFF Offset PLL OFF OFF OFF ON OFF RF 1st local buffer ON ON ON ON OFF IF local buffer ON ON ON ON OFF IFVCO ON ON ON ON OFF Total current 42.5 mA Typ 32 mA Typ 10.5 mA Typ 38 mA Typ 1 µA Typ 4.615ms 7 The slots of GSM system 0 Rx Cal Operating modes of the HD155101BF 1 2 3 4 Tx 4.615ms 5 6 7 Mon 0 Rx 1 2 3 4 Tx 6 7 0 1 Mon Cal Cal Cal Lo- Rx ON Lo- Rx Lo-ON Tx ON Rx Lo-ON Tx ON 5 Lo- Lo- Rx ON PS POONRX1(pin 1) POONRX2(pin 2) Idle(PS) mode don’t care POONTX (pin 7) Power Amplifier ON UHF PLL synth. ON UHF PLL synth. load VCO control voltage of UHF PLL synth. Figure 2 Control Diagram for Operating Mode Selection 11 HD155101BF IFVCO Operation The HD155101BF incorporates an IFVCO circuit. The IFVCO circuit consists of an IFVCO transistor and a bias circuit for it, whose current are 2.0 mA and 0.5 mA respectively. If an internal IFVCO is used, treat pin 23 (IFVCOO), pin 24 (IFVCOI) and pin 21 (IFLO) as shown figure 3-(a). Using an external IFVCO, pin 23 (IFVCOO) and pin 24 (IFVCOI) cannot be connected any pattern and component, and any component to feed direct current must be also removed from pin 21 (IFLO). If pin 23 (IFVCOO), pin 24 (IFVCOI) and pin 21 (IFLO) are treated as shown figure 3-(b), current consumption will decrease 2.0 mA. Vtune Vcc PLL IFLO synth. (a) using an internal IFVCO 23 24 HD155101BF IFVCOI 21 IFVCOO HD155101BF IFVCO bias circuit IFLO 24 IFVCOI 23 IFVCOO 21 IFLO IFVCO bias circuit External IFVCO PLL IFLO synth. (b) using an external IFVCO Figure 3 Control Diagram for Operating Mode Selection 12 Vtune HD155101BF Absolute Maximum Ratings Any stresses in excess of the absolute maximum ratings can cause permanent damage to the HD155101BF. Item Symbol Rating Unit Power supply voltage (VCC) VCC –0.3 to +4.0 V Power supply voltage (VCCCOMP) VCCCOMP VCC to +5.5 V Pin voltage VT –0.3 to VCC + 0.3 (6.0 Max) V Maximum power dissipation PT 400 mW Operating temperature Topr –20 to +85 °C Storage temperature Tstg –55 to +125 °C 13 HD155101BF Electrical Characteristics (Ta = 25°C) Specifications Symbol Min Typ Max Unit Power supply voltage (1) VCC 2.7 3.0 3.6 V 4, 8, 20, 31, 34, 41, 45 Power supply voltage (2) VCCCOMP 2.7 3.0 5.25 V 11 Power supply current (Rx.) ICC(Rx.) — 42.5 60.0 mA VCC = 3.0V VCCCOMP = 3.0V 4, 8, 20, 31, 34, 41, 45, 11 Power supply current (Tx.) ICC(Tx.) — 38.0 55.0 mA VCC = 3.0V VCCCOMP = 3.0V 4, 8, 20, 31, 34, 41, 45, 11 Power supply current (Lo-ON) ICC(Lo-ON) — 10.5 15.0 mA VCC = 3.0V VCCCOMP = 3.0V 4, 8, 20, 31, 34, 41, 45, 11 Power saving mode supply current ICC(PS) — 1.0 10.0 µA VCC = 3.0V VCCCOMP = 3.0V 4, 8, 20, 31, 34, 41, 45, 11 Power up time (Rx.) t up(Rx.) — 1.5 (5.0) µsec VCC = 3.0V VCCCOMP = 3.0V from PS mode Power up time (Tx.) t up(Tx.) — 0.2 (0.5) µsec VCC = 3.0V VCCCOMP = 3.0V from PS mode Power on control voltage range (Rx1, Rx2, Tx) VthonRX1 VthonRX2 VthonTX 2.3 — — V VCC = 3.0V 1 2 7 Power off control voltage range (RX1, Rx2, Tx) VthoffRX1 VthoffRX2 VthoffTX — — 0.8 V VCC = 3.0V 1 2 7 I/Q common-mode output voltage VIOcom/ VQOcom 1.1 1.3 1.5 V VCC = 3.0V 25, 26 27, 28 I/Q differential output swing VIOsw/ VQOsw 2.4 3.0 — Vp-p VCC = 3.0V VIOUT – VIOUTB VQOUT – VQOUTB 25, 26 27, 28 I/Q output offset voltage VIOoffset/ VQOoffset –60 0 +60 mV VCC = 3.0V VIOUTDC – VIOUTBDC VQOUTDC – VQOUTBDC 25, 26 27, 28 I/Q common-mode input voltage VIIcom/ VQIcom (0.8) 1.0 (1.2) V VCC = 3.0V 14, 15 16, 17 I/Q differential input swing VIIsw/ VQIsw — 2.0 (2.4) Vp-p VCC = 3.0V VIIN – VIINB VQIN – VQINB 14, 15 16, 17 Note: ( ) : These data are actual spread, not guaranteed. 14 Test Conditions Applicable pins Item Note HD155101BF Block Specifications • Specifications of LNA Item Min Typ Max Unit Frequency (RF) 925 940 960 MHz Power gain — 18.0 — dB RF = 940MHz , Pin = –50dBm Noise figure — 1.75 — dB RF = 940MHz i/p IP3 — –1.0 — dBm RF1 = 940.8MHz, RF2 = 941.6MHz o/p IP3 — 16 — dBm RF1 = 940.8MHz, RF2 = 941.6MHz i/p CP — –11.5 — dBm RF = 940MHz o/p CP — 5.5 — dBm RF = 940MHz Load Z — 50 — Ω 50Ω Typ i/p Z — 50 — Ω 50Ω Typ i/p VSWR — 1.5 — RF = 940MHz, 50Ω o/p VSWR — 1.5 — RF = 940MHz, 50Ω I CC @LNA Trs. 4.7 5.6 6.8 mA Test Conditions Only Trs. current Note: These AC characteristics are shown for reference only and do not form part of the HD155101BF component specification. • Specifications of Mixer 1 (Output Load = 400Ω + 400Ω balanced) Item Min Typ Max Unit Test Conditions Frequency (RF) 925 940 960 MHz Frequency (LO) 1055 1165 1260 MHz Frequency (IF) (130) 225 (300) MHz Conversion gain 4.5 7.0 9.0 dB RF = 940MHz/Pin = –50dBm, LO = 1165MHz/Pin = –10dBm, IF = 225MHz Noise figure (6.0) 9.0 (12.0) dB RF = 940MHz, LO = 1165MHz/Pin = –10dBm, IF = 225MHz i/p IP3 — –1.0 — dBm RF1 = 940.8MHz, RF2 = 941.6MHz, LO = 1165MHz/Pin = –10dBm o/p IP3 — 6.0 — dBm RF1 = 940.8MHz, RF2 = 941.6MHz, LO = 1165MHz/Pin = –10dBm i/p CP –13.5 –11.0 (–8.0) dBm RF = 940MHz, LO = 1165MHz/Pin = –10dBm, IF = 225MHz o/p CP (–9.5) –5.0 (–0.5) dBm RF = 940MHz, LO = 1165MHz/Pin = –10dBm, IF = 225MHz RF i/p VSWR — 1.5 (2.0) RF = 940MHz, 50Ω LO i/p VSWR — 1.5 (2.0) RF = 1165MHz, 50Ω IF o/p VSWR — 1.5 (2.0) RF = 225MHz, 800Ω (400Ω + 400Ω Balanced) Note: ( ) : These data are actual spread, not guaranteed. 15 HD155101BF • Specifications of IFAmp + Mixer 2 Item Min Typ Max Unit Test Conditions Input frequency (IF1) (130) 225 (300) MHz Frequency (LO2) (156) 270 (360) MHz Output frequency (IF2) (26) 45 (60) MHz Conversion gain 9.0 12.0 14.5 dB IF1 = 225MHz/Pin = –40dBm, IFLO = 540MHz/Pin = –10dBm, IF2 = 45MHz Noise figure (4.5) 5.6 (7.0) dB IF1 = 225MHz, IFLO = 540MHz/Pin = –10dBm, IF2 = 45MHz i/p IP3 — –16.0 — dBm IF11 = 225.8MHz, IF2 = 226.6MHz, IFLO = 540MHz/Pin = –10dBm o/p IP3 — –4.0 — dBm IF11 = 225.8MHz, IF2 = 226.6MHz, IFLO = 540MHz/Pin = –10dBm i/p CP –27.5 –25.0 (–23.0) dBm IF1 = 225MHz, IFLO = 540MHz/Pin = –10dBm, IF2 = 45MHz o/p CP (–18.0) –14.0 (–11.0) dBm IF1 = 225MHz, IFLO = 540MHz/Pin = –10dBm, IF2 = 45MHz Isolation (55) 60 — dB Between mixer 1 outputs and IFAmp inputs LO2 = IFLO/2 Note: ( ) : These data are actual spread, not guaranteed. • Specifications of AGC Item Min Typ Max Unit Input frequency (26) 45 (60) MHz Control voltage range 0.15 — 2.3 V Gain range 89 98 107 dB Gain 1 – Gain 3 Gain linearity (–1.0) — (1.0) dB in any 20dB window Gain 1 45 55 65 dB Vcont = 2.3V Gain 2 13 23 33 dB Vcont = 1.5V Gain 3 –55 –40 –35 dB Vcont = 0.15V i/p CP 1 (–64) –59 — dBm Gain = 50dB i/p CP 2 (–34) –29 — dBm Gain = 10dB i/p CP 3 (–22) –17 — dBm Gain = –30dB Note: ( ) : These data are actual spread, not guaranteed. 16 Test Conditions HD155101BF • Specifications of IQ Demodulator Item Min Typ Max Unit Test Conditions Power gain –0.5 1.4 3.5 dB IF2 = 45MHz, Pin = –25dBm, Rout = 10kΩ, IFLO = 540MHz, Pin = –10dBm i/p CP (–17.5) –16.0 (–14.0) dBm IF2 = 45MHz, Baseband = 67.7kHz, IFLO = 540MHz, Pin = –10dBm o/p CP (–19.0) –15.6 (–12.0) dBm IF2 = 45MHz, Baseband = 67.7kHz, IFLO = 540MHz, Pin = –10dBm IQ phase accuracy –1.0 0 1.0 deg. Baseband = 67.7kHz IQ amplitude mismatch (–0.5) 0.1 (0.5) dB Baseband = 67.7kHz Output DC offset voltage –60 0 60 mV |IOUT – IOUTB| and |QOUT – QOUTB| IQ differential output swing 2.4 3.0 — Vp-p Baseband = 67.7kHz |IOUT – IOUTB| and |QOUT – QOUTB| I/Q common mode output voltage 1.1 1.3 1.5 V VCC = 3.0V Note: ( ) : These data are actual spread, not guaranteed. 17 HD155101BF • Specifications of IQ Modulator and Offset PLL (RFLO and IFLO signals are supplied by Signal Generator) Item Min Typ Max Unit Frequency (RF) 880 902 915 MHz Frequency (LO) 1055 1172 1260 MHz Frequency (IF) (120) 135 (180) MHz Power up time — 0.3 (0.5) µsec from PS mode Lock up time — 20 (80) µsec from PS mode to 915MHz Carrier suppression ratio 31 40 — dBc All ‘1’ GMSK (Baseband = 67.7kHz) Upper side-band suppression ratio 35 45 — dBc I/Q differential input swing = 2.0Vp-p I/Q common mode input voltage = 1.0V Phase accuracy — 0.94 (2.5) deg. rms 200kHz Bandwidth (PN9, GMSK) — 2.27 (6.0) deg. peak 200kHz Bandwidth Modulation spurious — –36.5 (–33.0) dBc 200kHz offset / 30kHz Bandwidth (PN9, GMSK) — –70.0 (–63.0) dBc 400kHz offset / 30kHz Bandwidth — –74.0 (–63.0) dBc 600kHz to 1.8MHz offset / 30kHz Bandwidth — –77.0 (–66.0) dBc 1.8MHz to 3MHz offset / 100kHz Bandwidth — –80.5 (–68.0) dBc 3MHz to 6MHz offset / 100kHz Bandwidth — –82.0 (–74.0) dBc 6MHz upwards offset / 100kHz Bandwidth Tx noise in RX band — –157 (–151) dBc/Hz 925MHz to 935MHz (10MHz up from Tx band) (Tx power = 0dBc = 30dBm) — –165 (–163) dBc/Hz 935MHz to 960MHz (20MHz up from Tx band) Isolation of the 1st local input to TXVCO input (40) 43 — dB IQ differential input swing — 2.0 (2.4) Vp-p I/Q common mode input voltage (0.8) 1.0 (1.2) V Note: ( ) : These data are actual spread, not guaranteed. 18 Test Conditions (Loop bandwidth = 1.4MHz) |IIN – IINB| and |QIN – QINB| VCCVCOEXT J301 (VCOOUT) SMA VCCCOMP VCC 1000p R301 0 R304 18 C205 10p C304 0.75p C307 220p R302 R303 0 0 VCO1 C305 MQE502-902 or 1000p MQE601-902 Kv=11MHz/V 3 4 OUT VCC 2 5 R305 GND GND 220 6 MOD CON 1 C302 120p C303 100p C206 4.7k 0.5p C207 10n 0.5p C301 47p R201 L202 C203 27p R306 130 C308 3300p PLLOUT VCCCOMP VCOIN GNDPLL VCCPLL POONTX RFIN GNDLNA VCCLNA RFOUT POONRX2 MIX1INB QINB POONRX1 IC001 HD155101BF GNDMIX1 QIN J202 (LNAIN) SMA C204 1 2 3 4 5 6 7 8 9 10 11 12 VCCMIX1 IINB Q201 BPF420 RFLOIN IIN 3p MIX1OUTB MODB VCC MIX1OUT MOD C202 10p VCCIF VCCIQ 10n IFVCOO J201 (LNAOUT) SMA C201 4 4 GNDIF IFLO MIX1IN CURAD IFINB 48 47 46 45 44 43 42 41 40 39 38 37 IFIN GNDIQ R307 8.2k QIN IIN QINB IINB 18n 18n C406 1000p L401 L402 C405 8p R501 100 36 35 34 33 32 31 30 29 28 27 26 25 VCC 120p C501 C502 1000p L502 8.2n C507 8p VARICAP1 R502 HVU355 2.7k 6p C506 3p 100n J501 (IFLO) SMA L501 15n C504 3p C503 6p 6p C505 QOUTB QOUT IOUTB IOUT VCONT GNDDIV VCCDIV AGCOUTB AGCOUT VCCAGC GNDAGC MIX2OB MIX2O IFVCOI L201 65 3 3 2 2 11 3p IOUTB IOUTB 13 14 15 16 17 18 19 20 21 22 23 24 L701 C705 GND 100n C801 IOUT IOUT C810 1000p QOUT QOUT 3p GND POONRX2 10n C508 1000p GND L803 C812 QOUTB QOUTB POONRX1 IIN IIN POONTX VCONT VCONT C706 7p GND C803 1000p IINB IINB L801 GND 3.3n 1000p C701 C702 1000p C901 27p C904 27p C907 27p QIN QIN L802 QINB QINB T801 617PT-1206 T701 617DB-1018 3 4 3 4 2 2 11 65 C902 100n C905 100n C908 100n C601 1000p C903 100000n C906 100000n C606 47p 3300p C608 C609 3300p C610 3300p 3300p C703 C704 3300p C909 100000n T601 617DB-1018 3 4 3 4 2 2 11 65 C607 3300p GND C809 C808 POONTX POONTX 1000p 100p POONRX2 POONRX2 C811 2.5p GND C813 4p SLEEP R701 0 VTUNE VTUNE C805 1000p POONRX1 POONRX1 C807 1000p POONRX J801 (MIX1IF) J702 (MIX2RF) SMA SMA VCCVCOEXT VCC VCC J802 (MIX1LO) SMA VCCVCOEXT VCCCOMP VTUNE VCC VCONT IOUT IOUTB QOUT QOUTB VCC J601 (AGCOUT) SMA VCC J701 (MIX2IF/AGCIN) SMA GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 VCCCOMP J803 (MIX1RF) SMA HD155101BF Test Circuit 19 HD155101BF Measurement Results LNA Measurement Results (for reference only) Conditions: Vcc = 3.0 V POONRX1 (pin 1) = 3.0 V POONRX2 (pin 2) = 3.0 V POONTX (pin 7) = 0 V 3.0 V 1000 p 1 2 4 8 11 20 31 34 41 45 Rbias 100 TRS: Siemens BFP420 Vbias 0.56 V 3 50 Ω 3p 10 n Ic 10 p Active bias circuit Output(RF) 50 Ω 1000 p 10 n 4.7 k 6 Input(RF) 940 MHz, −50 dBm 0.5 p 0.5 p 10 p HD155101BF 5 7 9 22 30 35 40 46 Figure 4 Evaluation Circuit for LNA 20 3.5 10 3 Vcc=3.0V Pin=−50dBm Gain [dB] ICP [dBm] NF [dB] 5 2 0 1.5 −5 1 −10 −15 880 0.5 900 920 940 960 Frequency [MHz] 980 Figure 5 Gain, NF, ICP vs. Frequency 20 2.5 1000 0 1020 NF [dB] Gain [dB], ICP [dBm] 15 HD155101BF 40 18 −20 17 −40 16 −60 Interfere(1)=940.8MHz Interfere(2)=941.6MHz Gain [dB] 19 0 15 −80 14 Pout [dBm] IM3 [dBm] Gain [dB] −100 −120 −60 −50 −40 −30 −20 Pin [dBm] −10 13 12 10 0 Figure 6 Gain, Pout vs. Pin 20 19.5 Freq.=940MHz Pin=-50dBm 19 18.5 Gain [dB] Pout [dBm] 20 20 Vcc=3.0V Freq.=940MHz 18 17.5 17 −40 −20 27 80 100 16.5 16 15.5 15 2 2.5 3 3.5 4 4.5 Vcc [V] Figure 7 Gain vs. Supply Voltage 21 HD155101BF 3 Freq.=940MHz 2.5 NF [dB] 2 1.5 −40 −20 27 80 100 1 0.5 0 2 2.5 3 3.5 4 4.5 Vcc [V] Figure 8 NF vs. Supply Voltage −7 −8 Freq.=940MHz −9 ICP [dBm] −10 −11 −12 −13 −40 −20 27 80 100 −14 −15 −16 −17 2 2.5 3 3.5 Vcc [V] Figure 9 ICP vs. Supply Voltage 22 4 4.5 HD155101BF 8 −40 −20 27 80 100 7.5 Icc@TRS [mA] 7 6.5 6 5.5 5 4.5 4 2 2.5 3 3.5 4 4.5 Vcc [V] Figure 10 LNA Transistor Current vs. Supply Voltage 23 HD155101BF 1st Mixer Measurement Results Load: 400 ohm Balanced TOKO: 617PT-1206 800 Ω: 50 Ω Insertion loss: 1.5 dB@225 MHz Conditions: Vcc = 3.0 V POONRX1 (pin 1) = 3.0 V POONRX2 (pin 2) = 3.0 V POONTX (pin 7) = 0 V 3.0 V 1000 p Vcc 1 Input (LO) 1165 MHz, −10 dBm Input (RF) 940 MHz, −50 dBm 2 4 8 11 20 31 34 41 45 Lo Buff2 50 Ω 2.5 p 1000 p 44 43 3.3 n Gilbert Cell Mix Lo Buff 50 Ω 4 p 42 100 n 1000 p 3p 47 1000 p 48 Output (IF) 225 MHz 50 Ω 10 n 3p 5 7 9 22 30 35 40 46 Figure 11 Evaluation Circuit for 1st Mixer 10 16 14 C.G. [dB] ICP [dBm] NF SSB [dB] 0 Vcc=3.0V Pin=−50dBm Pin(LO)=−10dBm Freq.IF=225MHz −5 10 −10 8 −15 880 900 920 940 960 Frequency [MHz] 980 Figure 12 Gain, NF, ICP vs. Frequency 24 12 1000 6 1020 NF SSB [dB] C.G. [dB], ICP [dBm] 5 HD155101BF 10 20 Pout[dBm] 15 C.Gain[dB] −10 10 −20 5 −30 0 Vcc=3.0V Freq.RF=940MHz Freq.LO=1165MHz Pin(LO)=−10dBm Freq.IF=225MHz −40 −50 −60 C.Gain [dB] Pout [dBm] 0 −50 −40 −30 −20 Pin[dBm] −10 −5 0 −10 10 10 25 5 20 NF SSB[dB] C.Gain[dB] 0 −5 10 Freq.RF=940MHz Freq.LO=1165MHz Freq.IF=225MHz Pin(RF)=−50dBm −10 −15 −60 15 −50 −40 −30 −20 Plo [dBm] NF SSB [dB] C.Gain [dB] Figure 13 Input-Output Characteristics 5 −10 0 0 10 Figure 14 CG, NF vs. Local Input Power 25 HD155101BF 12 10 C.Gain[dB] C.Gain [dB] 8 6 4 2 Vcc=3.0V Freq.LO=1165MHz Pin(LO)=−10dBm Pin(RF)=−50dBm 0 −2 150 200 250 300 Frequency [MHz] Figure 15 Output Frequency Characteristics 10 9 8 C.Gain [dB] 7 6 5 4 −40 −20 27 80 100 3 2 1 0 2 2.5 3 3.5 Vcc [V] Figure 16 Gain vs. Supply Voltage 26 4 4.5 HD155101BF 15 14 −40 −20 27 80 100 13 SSB NF [dB] 12 11 10 9 8 7 6 5 2 2.5 3 3.5 4 4.5 Vcc [V] Figure 17 NF(SSB) vs. Supply Voltage −7 −8 −9 ICP [dBm] −10 −11 −12 −13 −40 −20 27 80 100 −14 −15 −16 −17 2 2.5 3 3.5 4 4.5 Vcc [V] Figure 18 ICP vs. Supply Voltage 27 HD155101BF IF AMP + 2nd Mixer Measurement Results Conditions: 3.0 V Vcc = 3.0 V 1000 p POONRX1 (pin 1) = 3.0 V POONRX2 (pin 2) = 3.0 V POONTX (pin 7) = 0 V Input (1st IF) 225 MHz, −40 dBm Input (IFLO) 540 MHz, −10 dBm 1 50 Ω 7 p 2 4 8 11 20 31 34 41 45 IF AMP 150 Mixer2 150 50 Ω 1000 p 270 MHz Divider 21 0.01 µ 1000 p 1/2 5 7 300 36 1000 p 200 Ω: 50 Ω TOKO 617DB-1018 Insertion loss = 3.6 dB AGC 9 Output (MIX2) 45 MHz 1000 p 37 39 100 n 38 6p Output test-circuit for IF AMP + Mixer2 evaluation only 22 30 35 40 46 Figure 19 Evaluation Circuit for IF AMP + 2nd Mixer 20 0 C.Gain Pout_2IF C.Gain [dB] 1dB 10 −20 5 −30 0 −40 ICP: −25dBm −5 −70 −60 −50 −40 −30 −20 Pin_RF [dBm] −10 −50 0 Figure 20 Input-Output Characteristics, 1dB-Compression Point 28 10 Pout_2IF [dBm] −10 15 HD155101BF 20.0 Pout [dBm] 0.0 IP3out: −4.0dBm −20.0 −40.0 −60.0 Pout_IM3 Pout_2IF IF11=225.8MHz IF12=226.6MHz −80.0 −100.0 −60 IP3in: −16.0dBm −50 −40 −30 Pin_RF [dBm] −20 −10 0 Figure 21 Intermodulation 3rd Characteristics 20 10 2.5V 27°C 2.7V 27°C 3.0V 27°C C.Gain [dB] 0 −10 4.0V 27°C −20 IF1=225MHz/Pin=−30dBm, IFLO=540MHz,IF2=45MHz −30 −40 −50 −50 −40 −30 −20 Local in [dBm] −10 0 10 Figure 22 C.Gain vs. Local in Power 29 HD155101BF 25 20 20 C.Gain Ta=−30°C Ta=25°C Ta=80°C 0 2.7V to 3.6V −10 10 −20 −30 2 15 5 NF SSB 2.5 3 3.5 0 4.5 4 Vcc [V] ICP(Input Compresion Point) [dBm] Figure 23 C.Gain, NF SSB vs. Supply Voltage −20 Vcc=4.0V Vcc=3.0V Vcc=2.7V −25 IF1=225MHz, IFLO=540MHz/Pin=−10dBm, IF2=45MHz −30 −40 −20 0 20 40 Temperature [deg] Figure 24 ICP vs. Temperature 30 60 80 100 NF SSB [dB] C.Gain [dB] 10 HD155101BF AGC Measurement Results 3.0 V 1000 p 1 2 4 45 MHz 50 Ω 1000 p 150 8 Output test-circuit for AGC block evaluation only 11 20 31 34 41 45 150 Mixer2 output R Output (MIX2) 200 Ω: 50 Ω 45 MHz 37 TOKO 617DB-1018 insertion loss = 3.6 dB 2k ATT AGC AMP POONRX2 36 POONRX1 1000 p 50 Ω: 200 Ω 3300 p 300 32 Power on/off control Linearizer 29 2k IQ Demodulator IF AMP + Mixer2 IF VCO Divider LNA & Mixer 1 Transmitter block 5 7 33 9 22 30 35 3300 p TOKO Vcont 617DB-1018 0.15 to 2.3 V insertion loss = 6.1 dB Conditions: Vcc = 3.0 V POONRX1 (pin 1) = 3.0 V POONRX2 (pin 2) = 3.0 V POONTX (pin 7) = 0 V IQ Demo 40 3300 p 46 Figure 25 Evaluation Circuit for the AGC & Power On Control Blocks 80 60 Ta=−40°C Ta= 27°C Ta= 90°C Gp [dB] 40 20 0 −20 Vcc=3.0V, Freq=45MHz, Zin=300Ω −40 −60 0 0.5 1 1.5 2 2.5 Vcont [V] Figure 26 Power Gain vs. Vcont Voltage 31 HD155101BF 60 55 Ta=−40°C Ta= 27°C Ta= 90°C Gp [dB] 50 45 40 Vcc=3.0V, Vcont=2.3V, Freq=45MHz, Pin=−100dBm, Zin=300Ω 35 30 10 20 50 100 Frequency [MHz] Figure 27 Power Gain vs. Frequency 60 50 NF [dB] 40 VCC=3V, freq.=45MHz Ta=−40°C Ta=27°C Ta=90°C 30 20 10 0 −40 −20 0 20 Gp [dB] 40 Figure 28 Noise Figure(NF) vs. Power Gain(Gp) 32 60 80 HD155101BF 10 Vcc=3V, freq.=45MHz Ta=−40°C Ta=27°C Ta=90°C 0 ICP [dBm] −10 −20 −30 −40 −50 −60 −70 −40 −20 0 20 40 60 Gp [dB] Figure 29 Input Compression Point(ICP) vs. Power Gain(Gp) 60 40 Gp [dB] 20 0 −20 Ta=−40@Vcont=2.3 Ta=27@Vcont=2.3 Ta=90@Vcont=2.3 Ta=−40@Vcont=0.15 Ta=27@Vcont=0.15 Ta=90@Vcont=0.15 Freq=45MHz, Zin=300Ω −40 −60 −80 1.5 2 2.5 3 Vcc [V] 3.5 4 4.5 Figure 30 Power Gain(Gp) vs. Supply Voltage(Vcc) 33 HD155101BF IQ Demodulator Measurement Results Conditions: Vcc = 3.0 V POONRX1 (pin 1) = 3.0 V POONRX2 (pin 2) = 3.0 V POONTX (pin 7) = 0 V 3.0 V 1000 p 1 2 4 8 11 20 31 34 41 45 10 k TOKO 45 MHz 617DB-1018 50 Ω 3300 p 50 Ω: 200 Ω 3300 p 3300 p AGC 2k 33 2k 2nd order Butterworth filter 90 MHz divider 21 45 MHz ÷2 (90° phase shifter) ÷6 0.01 µ 5 7 9 28 27 10 k 32 50 Ω Input (IFLO) 540 MHz, −10 dBm 2nd order Butterworth filter 26 IOUT IOUTB 10 k QOUT V 25 QOUTB 10 k 10 k 10 k Single ended 1kΩ input impedance Single ended 10kΩ load impedance 22 30 35 40 46 Figure 31 Evaluation Circuit for the I&Q Demodulator Block 34 V HD155101BF −15 30 Output[dBm] Vcc=3.0V Output[dBm] Vcc=2.7V Output[dBm] Vcc=3.6V 20 OCP: −15.0dBm −20 Ta = 25°C 10 1dB −25 0 Gp[dB] Vcc=3.0V Gp[dB] Vcc=2.7V Gp[dB] Vcc=3.6V −30 Gp [dB] Output [dBm] (Single ended) −10 −10 ICP: −15.5dBm −35 −35 −30 −25 −20 −15 −10 Input [dBm] (Single ended) −5 −20 0 Figure 32 Input-Output Characteristics −15 30 Output[dBm] Ta=25°C Output[dBm] Ta=−20°C Output[dBm] Ta=80°C 20 −20 10 Vcc = 3V −25 0 Gp[dB] Ta=25°C Gp[dB] Ta=−20°C Gp[dB] Ta=80°C −30 −35 −35 −30 −25 −20 −15 −10 Input [dBm] (Single ended) Gp [dB] Output [dBm] (Single ended) −10 −10 −5 −20 0 Figure 33 Input-Output Characteristics 35 HD155101BF GMSK modulated signal (All 1 GMSK) DIV f1: 45.8MHz (45MHz) + (67.7kHz) DEM f2: 46.6MHz Output [dBm] (Single ended) 0 OIP3: −0.2dBm −10 −20 −30 Output [dBm] IM3 [dBm] −40 −50 −35 −30 IIP3: −2.7dBm −25 −20 −15 −10 −5 Input [dBm] (Single ended) 0 Figure 34 Inter Modulation 3rd Characteristics Rejection @200k @400k @600k @800k @1600k @3000k @20000k spec.(Min) −0.3dB −4.0dB −9.4dB −14.0dB −25.9dB −36.8dB −50.0dB Iout −2.6dB −11.5dB −21.3dB −29.0dB −43.3dB −42.2dB −54.7dB Qout −2.4dB −11.2dB −21.1dB −28.7dB −43.0dB −42.0dB −56.1dB Rejection level [dB] 20 spec.1 spec.2 Iout Qout 0 −20 fc: 210kHz −40 −60 −80 10 100 1000 Frequency [kHz] 104 105 Figure 35 Internal LPF Frequency Characteristics 36 HD155101BF 0.09[degree] 0.1[dB] a) I&Q Phase Accuracy 1.38[V] b) I&Q Amplitude Mismatch 3.00[Vp-p] c) Common Mode Voltage d) Differential Output Swing Figure 36 Demodulator Output Waveforms (67.7 kHz) at Vcc = 3.0 V, Ta = 25°C 37 HD155101BF Transmitter Measurement Results 3.0 V 1000 p 1 51 p 14 C2 3300p PLLOUT R2 130 RICURAD 8.2k I3 12 C1 220p ICURAD Low pass filter 11 1000p R3 220 45 on ÷2 (90° phase shifter) 270 MHz GMSK modulated IF 270 MHz I1 Q baseband signal 100 kHz I2 off I baseband signal 100 kHz Phase detector Low SW1 Charge Pump pass (Current mode driver) filter Power save control POONTX=H, SW1=Off 13 5 Conditions: Vcc = 3.0 V POONRX1 (pin 1) = 0 V POONRX2 (pin 2) = 0 V POONTX (pin 7) = 3.0 V 7 9 22 30 35 40 46 18n 18 19 14 8p 18n 15 16 17 21 IFLO 5.0V 41 IIN MURATA MQE502-902 or MQE601-902 Kv=11MHz/V,C3=100pF loop band width=1.5MHz 10 VCO buffer VCCCOMP 34 I&Q modulator block Down-converter (offset mixer) 0.75 p VCO 31 IINB GMSK RF TX. signal 890 to 915MHz 20 QIN 18 1000p 8 LO buffer VCOIN 50 Ω 4 QINB RFLOIN 3.9n Spectrum analyzer 2 1st. local signal 1150 to 1185 MHz MOD 3p MODB Input(LO),−10dBm 50 Ω 1150 to 1185MHz 0.01µ fo=270MHz Vcc I&Q baseband signal generator 50Ω Input(IFLO) 540MHz, −10dBm Figure 37 Evaluation Circuit for the Upconverter (I&Q Modulator and Offset PLL Block) I1 peak, I2 peak, I3 [mA] 5 I1 peak I2 peak I3 4 3 2 1 0 2 4 6 8 10 RICURAD [kΩ] 20 Figure 38 I1 Peak, I2 Peak, I3 vs. RICURAD Characteristics 38 30 HD155101BF Phase accuracy and lock up time characteristics depend on the OPLL loop bandwidth. The following table shows measurement result of each characteristic, when the OPLL loop bandwidth is changed. Table 2 Measurement Results of Transmitter Characteristics vs. OPLL Loop Bandwidth Dependence (RICURAD = 8.2 kΩ, IFLO generated by signal generator) Conditions Item Condition1 VCO & Phase detector VCO: MURATA MQE502-902 or MQE601-902, C3 = 100 pF in VCO, RICURAD = 8.2 kΩ, kvr = 2π × 11 × 106 (rad/Vsec), k dr = ( 2.83 × 10–3) / π (A/rad) Loop bandwidth (measured) 0.8 1.1 1.3 1.5 1.6 MHz C1 680 390 300 220 180 pF C2 10.0 6.8 4.7 3.3 2.7 nF C3 100 100 100 100 100 pF R2 68 100 110 130 130 Ω R3 390 330 270 220 200 Ω Condition 2 Condition 3 Condition 4 Condition 5 Unit Item Spec. Measured1 Measured2 Measured3 Measured4 Measured5 Unit 200 kHz offset ≤ –33 –37.23 –37.09 –37.60 –37.70 –37.86 dBc 400 kHz offset ≤ –63 –67.41 –67.95 –68.49 –68.94 –69.23 dBc 600 kHz to 1.8 MHz offset ≤ –63 –72.86 –72.85 –73.09 –73.48 –73.26 dBc 1.8 MHz to 3 MHz offset ≤ –66 –79.65 –76.96 –76.45 –75.70 –74.96 dBc 3 MHz to 6 MHz offset ≤ –68 –82.11 –81.11 –80.83 –79.18 –79.58 dBc 6 MHz upwards offset ≤ –74 –82.77 –82.67 –82.59 –81.98 –82.38 dBc Carrier suppression ≥ 31 47.35 48.44 47.54 46.71 48.36 dBc Side band suppression ≥ 35 39.10 39.47 39.89 39.89 40.33 dBc Phase accuracy PN9 ≤ 2.5 1.53 1.16 1.02 0.89 0.84 deg. rms PN9 ≤ 6.0 3.30 2.90 2.81 2.72 2.64 deg. peak All ‘1’ ≤ 2.5 0.99 0.95 0.93 0.93 0.89 deg. rms All ‘1’ ≤ 6.0 2.26 2.33 2.33 2.31 2.04 deg. peak ≤ 80 58.1 41.1 29.4 19.1 17.2 µsec Lock up time Tx noise in 925 MHz –163.3 –158.6 –157.0 –155.1 –154.9 dBc/Hz Rx band 935 MHz –166.4 –165.6 –165.4 –164.1 –163.3 dBc/Hz VCO noise only 925 MHz –165.2 (0 dBc = –0.5 dBm, noise –165.7 dBm/Hz) dBc/Hz 935 MHz –166.4 (0 dBc = –0.5 dBm, noise –166.9 dBm/Hz) dBc/Hz 39 HD155101BF 3.0 Phase accuracy [deg. rms] Mod: PN9 2.5 2.0 1.5 1.0 0.5 0 0.6 0.8 1.0 1.2 1.4 OPLL Loop Bandwidth [MHz] 1.6 1.8 Figure 39 Phase Accuracy vs. OPLL Loop Bandwidth 60 50 Lock Up Time [µsec] PS mode to 915MHz 40 30 20 10 0 0.6 0.8 1.0 1.2 1.4 OPLL Loop Bandwidth [MHz] 1.6 Figure 40 Lock Up Time vs. OPLL Loop Bandwidth 40 1.8 HD155101BF Tx Noise in Rx Band [dBc/Hz] −150 −155 925MHz −160 935MHz −165 −170 0.6 0.8 1.0 1.2 1.4 OPLL Loop Bandwidth [MHz] 1.6 1.8 Figure 41 Tx Noise in Rx Band vs. OPLL Loop Bandwidth 41 HD155101BF Transmitter Measurement Results (1) (RICURAD = 8.2 kΩ and IFLO generated by signal generator) VCC 2.5p 1000p 0 0 0.01µ 3.3n 0.01µ MIX2O IFIN IFINB VCCIF GNDIF MIX1OUT RFLOIN MIX1OUTB VCCMIX1 GNDMIX1 MIX1IN AGCOUT GNDLNA AGCOUTB RFIN VCCDIV HD155101BF POONTX GNDDIV VCONT VCCPLL IOUT GNDPLL IOUTB VCOIN QOUT VCCCOMP VCC 0.01µ 0 0 0.01µ IFVCOI GNDIQ IFLO VCCIQ MOD 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 IFVCOO QOUTB PLLOUT MODB 0.01µ VCCAGC VCCLNA IIN 33µ RFOUT CURAD + 0.01µ GNDAGC IINB VCCCOMP 5V 33µ MIX2OB POONRX2 QIN + POONRX1 QINB VCC 3V 1 2 3 4 5 6 7 8 9 10 11 12 MIX1INB 48 47 46 45 44 43 42 41 40 39 38 37 50Ω Input(LO) −10dBm 1160 to 1185MHz RICURAD 8.2k Spectrum Analyzer 50Ω 100p 18 0.75p VCO VCCVCO 4.7V 0.01µ I&Q baseband Signal Generator 8p + 33µ 50Ω Input(IFLO) −10dBm 540MHz 220 0.01µ MURATA MQE502-902 130 18n 220p 3300p 18n VCC 0.01µ Figure 42 Evaluation Circuit Using Signal Generator for the I&Q Modulator and Offset PLL Table 3 Measurement Results Using SG (RICURAD = 8.2 kΩ, IFLO generated by signal generator) Item Spec. Measured frequency Measured1 Measured2 Measured3 Unit 890 902 915 MHz 200 kHz offset ≤ –33 –36.36 –36.16 –36.60 dBc 400 kHz offset ≤ –63 –68.22 –67.30 –67.02 dBc 600 kHz to 1.8 MHz offset ≤ –63 –74.84 –74.88 –74.69 dBc 1.8 MHz to 3 MHz offset ≤ –66 –77.48 –77.30 –77.10 dBc 3 MHz to 6 MHz offset ≤ –68 –79.73 –79.47 –79.16 dBc 6 MHz upwards offset ≤ –74 –81.63 –80.67 –80.94 dBc Carrier suppression ≥ 31 46.24 46.11 45.98 dBc Side band suppression ≥ 35 38.81 38.86 38.84 dBc PN9 ≤ 2.5 1.05 1.05 1.05 deg. rms PN9 ≤ 6.0 2.76 2.61 2.59 deg. peak All ‘1’ ≤ 2.5 1.00 1.02 1.01 deg. rms All ‘1’ ≤ 6.0 2.19 2.33 2.13 deg. peak Phase accuracy 42 HD155101BF a-1. Spectrum1 (890MHz, PN9) a-2. Spectrum2 (890MHz, PN9) b-1. Spectrum1 (902MHz, PN9) b-2. Spectrum2 (902MHz, PN9) c-1. Spectrum1 (915MHz, PN9) c-2. Spectrum2 (915MHz, PN9) Figure 43 GMSK Modulated Transmitter Output Spectrum (890 MHz, 902 MHz, 915 MHz) 43 HD155101BF T=–40°C 902MHz, PN9 T=–40°C 902MHz, PN9 T=27°C 902MHz, PN9 T=27°C 902MHz, PN9 T=100°C 902MHz, PN9 T=100°C 902MHz, PN9 Figure 44 GMSK Modulated Transmitter Output Spectrum vs. Temperature 44 HD155101BF 0.5V/div 0.5V/div The Acquisition response of OPLL using 8.2 kΩ icurad is shown below. The control voltage of the VCO was observed by the digital storage oscilloscope. 19.95µs 12.8µs 5µs/div 5µs/div a. from PS mode to 902MHz lock b. from PS mode to 915MHz lock Figure 45 Acquisition Time (Lock Up Time) 45 HD155101BF Transmitter Measurement Results (2) (RICURAD = 8.2 kΩ and IFLO using an internal IFVCO) VCC 1.5p 18p 0 0 0.01µ 4.7n IFIN IFINB MIX2O VCCIF GNDIF RFLOIN MIX1OUT VCCMIX1 MIX1OUTB GNDMIX1 MIX1IN AGCOUTB RFIN VCCDIV HD155101BF POONTX GNDDIV VCCPLL VCONT GNDPLL IOUT IOUTB VCOIN QOUT VCCCOMP 100p 18 0.75p Vtune VCO VCCVCO 4.7V 10p 8.2n 100 27 10p 8.2n 27p I&Q baseband Signal Generator + 33µ 0.01µ MURATA MQE502-902 130 18n 220p 0.01µ 3300p 6p 0 12k HVU355 330p 0 18k 4700p 11p 220 0.01µ 0.1µ 100p 20 19 18 17 16 15 14 13 12 11 50Ω 0 0 18n 0.01µ LMX2336 (PLL syn) 10 10 VCC 0.01µ 1 2 3 4 5 6 7 8 9 10 Spectrum Analyzer VCC 0.01µ IFVCOI GNDIQ IFLO VCCIQ MOD 8.2k 36 35 34 33 32 31 30 29 28 27 26 25 27p 13 14 15 16 17 18 19 20 21 22 23 24 IFVCOO QOUTB PLLOUT MODB 0.01µ AGCOUT GNDLNA IIN 33µ VCCLNA IINB + 0.01µ VCCAGC RFOUT QIN VCCCOMP 5V 33µ MIX2OB GNDAGC POONRX2 QINB + POONRX1 CURAD VCC 3V 1 2 3 4 5 6 7 8 9 10 11 12 MIX1INB 48 47 46 45 44 43 42 41 40 39 38 37 50Ω Input(LO) −10dBm 1160 to 1185MHz VCCPLL 3V + 33µ 0.1µ Figure 46 Evaluation Circuit Using Internal IFVCO for the I&Q Modulator and Offset PLL Table 4 Measurement Results Using an Internal IFVCO (RICURAD = 8.2 kΩ) Item Spec. (GSM Spec.) Measured frequency Measured1 Measured2 Measured3 Unit 890 902 915 MHz 200 kHz offset ≤ –33 (–30) –35.64 –36.24 –36.93 dBc 400 kHz offset ≤ –63 (–60) –63.63 –64.09 –64.09 dBc 600 kHz to 1.8 MHz offset ≤ –63 (–60) –69.85 –69.95 –70.47 dBc 1.8 MHz to 3 MHz offset ≤ –66 (–63) –76.89 –76.50 –76.04 dBc 3 MHz to 6 MHz offset ≤ –68 (–65) –81.06 –80.67 –80.38 dBc 6 MHz upwards offset ≤ –74 (–71) –82.67 –82.40 –82.34 dBc Carrier suppression ≥ 31 41.87 42.50 42.42 dBc Side band suppression ≥ 35 43.59 44.35 43.25 dBc Phase accuracy PN9 ≤ 2.5 (5) 2.43 2.09 2.01 deg. rms PN9 ≤ 6.0 (20) 6.56 6.06 6.41 deg. peak All ‘1’ ≤ 2.5 0.95 0.93 0.96 deg. rms All ‘1’ ≤ 6.0 2.67 2.67 2.61 deg. peak 46 HD155101BF a-1. Spectrum1 (890MHz, PN9) a-2. Spectrum2 (890MHz, PN9) b-1. Spectrum1 (902MHz, PN9) b-2. Spectrum2 (902MHz, PN9) c-1. Spectrum1 (915MHz, PN9) c-2. Spectrum2 (915MHz, PN9) Figure 47 GMSK Modulated Transmitter Output Spectrum Using an Iternal IFVCO 47 HD155101BF 570 Vcc=3.0V Frequency [MHz] 560 550 540 530 520 0 0.5 1 1.5 Vtune [V] 2 2.5 0.2V/div Figure 48 IFVCO Oscillation Frequency vs. Vtune Voltage 278µs 100µs/div Figure 49 IFVCO Lock Up Time (from PS mode to 540 MHz) 48 3 HD155101BF Package Dimesions Unit: mm 24 48 13 12 0.10 Dimension including the plating thickness Base material dimension 0.17 ± 0.05 0.15 ± 0.04 0.75 M 1.40 0.08 1.70 Max 1 0.21 ± 0.05 0.19 ± 0.04 0.5 37 0.10 ± 0.07 9.0 ± 0.2 9.0 ± 0.2 7.0 36 25 1.00 0.75 0° − 8° 0.50 ± 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) FP-48 Conforms 0.2 g 49 HD155101BF Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 URL NorthAmerica : http:semiconductor.hitachi.com/ Europe : http://www.hitachi-eu.com/hel/ecg Asia (Singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm Asia (Taiwan) : http://www.hitachi.com.tw/E/Product/SICD_Frame.htm Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm Japan : http://www.hitachi.co.jp/Sicd/indx.htm For further information write to: Hitachi Semiconductor (America) Inc. 2000 Sierra Point Parkway Brisbane, CA 94005-1897 Tel: <1> (800) 285-1601 Fax: <1> (303) 297-0447 Hitachi Europe GmbH Electronic components Group Dornacher Straße 3 D-85622 Feldkirchen, Munich Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Europe Ltd. Electronic Components Group. Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan. 50