Z89165/166/167/168/169 DTAD CONTROLLERS ZILOG CUSTOMER PROCUREMENT SPECIFICATION Z89165/167/169 AND Z89166/168 (ROMLESS) ENHANCED D UAL-PROCESSOR DTAD CONTROLLERS FEATURES ■ ■ Z8 RAM* (KBytes) Speed (MHz) ■ 25 Expanded Register Files Z89165 24 Z89166 ROMless Z89167 24 Z89168 ROMless Z89169 32 *General-Purpose 236 236 236 236 236 20 20 24 24 24 ■ 47 Input/Output Lines (Z89165) 31 Input/Output Lines (Z89166) 43 Input/Output Lines (Core Processor) ■ Six Vectored, Prioritized Z8 Interrupts with Programmable Polarity Part Number DSP ROM (Words) DSP RAM (Words) Speed (MHz) ■ Three Vectored, Prioritized DSP Interrupts with Programmable Polarity Z89165 Z89166 Z89167 Z89168 Z89169 6K 6K 8K 8K 8K 512 512 512 512 512 20 20 24 24 24 ■ Two Analog Comparators ■ Two Programmable Z8 8-Bit Counter/Timers, Each with Two 6-Bit Programmable Prescaler Part Number Z8 ROM (KBytes) ■ 68- and 84-Pin PLCC Packages ■ Watch-Dog Timer /Power-On Reset ■ 4.5- to 5.5-Volt Operating Range ■ On-Chip Oscillator that Accepts a Crystal, Ceramic Resonator, LC, RC, or External Clock Drive ■ Low-Power Consumption (200 mW Typical) ■ RAM and ROM Protect, Low-EMI Option ■ 0°C to +70°C Temperature Range GENERAL DESCRIPTION Zilog's Digital Voice Processor Controller family combines a Z8® microcontroller and a DSP processor on-chip for a cost-effective turnkey system in digital telephone answering devices and other voice processing applications. The dual-processor architecture is loosely coupled by mailbox registers and an interrupt system, enabling DSP or Z8 programs to be directed by events in each other's domain. The Z8 microcontroller uses an expanded register file to allow access to register-mapped peripheral and I/O circuits for programming versatility. The 16-bit DSP processor features a 24-bit ALU and accumulator with single-cycle instructions, providing the algorithm processing power necessary for telephone voice quality. CP96TAD0103 The Z89165/166 devices offer a half-flash 8-bit A/D converter with up to 128 kHz sample rate and a 10-bit Pulse-Width modulator (PWM) D/A converter, eliminating the need for an external CODEC. The Z89167/168/169 devices feature a hardware ARAM interface, as well as a dual-CODEC interface. A 10-bit PWM D/A converter is also on-chip. Notes: All Signals with a preceding front slash, "/", are active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Circuit Device Power Ground VCC GND VDD VSS 1 Z89165/166/167/168/169 DTAD CONTROLLERS ZILOG GENERAL DESCRIPTION (Continued) Address or I/O (Nibble Programmable) Address/Data or I/O (Byte Programmable) I/O (Bit Programmable) P00 P01 P02 P03 Timer 0 Capture Reg. Register File 256 x 8 Bit Timer 1 Port 0 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 Port 3 Register Bus Internal Address Bus 24 Kbytes Program ROM (Z89165) Port 1 P31 P32 P33 Z8 Core Input P34 P35 Output P36 P37 Internal Data Bus Port 4 P40 P41 P42 I/O P43 (Bit P44 Programmable) P45 P46 P47 Port 5 P50 P51 P52 P53 P54 P55 P56 P57 Expanded Register Bus Expanded Register File (Z8) Extended Bus of the DSP Peripheral Register (DSP) 256 Word RAM 0 mailbox 256 Word RAM 1 Port 2 Internal Address Bus 6K Words Program ROM DSP Core I/O (Bit Programmable) Internal Data Bus INT 1 RMLS /AS /DS R/W XTAL1 XTAL2 VDD GND /RESET INT 2 Ext. Memory Control DSP Port DSP0 DSP1 PWM (10-Bit) PWM Extended Bus of the DSP Timer 2 Timer 3 OSC ADC (8-Bit) Power AN IN AN VDD AN GND VREF+ VREF- Z89165/166 Functional Block Diagram 2 CP96TAD0103 Z89165/166/167/168/169 DTAD CONTROLLERS ZILOG GENERAL DESCRIPTION (Continued) Address or I/O (Nibble Programmable) Address/Data or I/O (Byte Programmable) P00 P01 P02 P03 Timer0 Timer1 Register File 256 x 8-Bit Port 4 Port 0 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 Internal Register Bus Z8 Core Port 1 24 Kbytes (167) 32 Kbytes (169) Program ROM Internal Address Bus Port 5 P40 P41 P42 I/O P43 (Bit P44 P45 Programmable) P46 P47 P50 I/O P51 (Bit P52 Programmable) P53 Internal Data Bus Address Bus I/O (Bit Programmable) P20 P21 P22 P23 P24 P25 P26 P27 DIN DENA0 DCLK DOUT DENA1 Data Bus Port 2 Peripheral Data Bus of the DSP ARAM Controller Mailbox Peripheral Registers (DSP) P31 Input P32 P33 P34 Output P35 P36 P37 DSP Core 8K Words Program ROM Extended Register File (Z8) Port 3 ARAM Control CODEC Interface RMLS /AS /DS R/W Z8 EXT. Memory Control PWM PWM (10-Bit) Timer3 Timer2 Data0 Data1 Data2 Data3 ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ARAM_SEL0 ARAM_SEL1 /RAS /CAS ARAM_R/W ARAM_/OE Power /RESET VDD GND -5V Control Out -5V OSC XTAL1 XTAL2 Z89167/168/169 Functional Block Diagram CP96TAD0103 3 Z89165/166/167/168/169 DTAD CONTROLLERS ZILOG 60 VREF+ XTAL1 11 59 ANIN P22 12 58 VREF- P56 13 57 ANGND P23 14 56 /AS P55 15 55 /RESET P54 16 54 R//W ANVDD GND 3 2 1 68 67 66 65 64 63 62 61 P07 /DS 4 P20 VDD 5 P21 VDD 6 P52 P04 7 P51 P50 8 10 60 VREF+ XTAL1 11 59 ANIN P22 12 58 VREF- P56 13 57 ANGND P23 14 56 /AS P55 15 55 /RESET P54 16 54 R//W GND 17 53 PWM 52 P10 Z89166 20 50 P11 P16 21 49 P46 P16 21 49 P46 P25 22 48 P53 P25 22 48 P53 P15 23 47 P45 P15 23 47 P45 P26 24 46 P44 P26 24 46 P44 P27 25 45 P43 P27 25 45 P43 N/C 26 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 N/C SCLK 26 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 /SYNC P42 P42 P41 P06 P12 P40 P37 P13 P36 DSP0 DSP1 P14 P35 VDD Z89165 68-Pin PLCC Pin Identification P41 P24 P06 P11 P12 50 P40 20 P37 P47 P24 P13 51 P36 19 DSP0 P05 DSP1 P47 P14 51 P35 19 VDD 18 P34 P17 P33 P10 P32 PWM P31 53 P34 P05 9 XTAL2 52 Z89165 P33 18 P32 17 P17 P31 GND P57 68 67 66 65 64 63 62 61 P03 /DS 1 P02 RMLS 2 10 P01 VDD 3 XTAL2 P00 P04 4 P07 P50 5 GND P57 6 P20 P03 7 P21 P02 8 P52 P01 9 P51 P00 ANVDD PIN DESCRIPTION Z89166 68-Pin PLCC Pin Identification Pin Identification Pin Name Function Direction Pin Name +5V Power GND Power AN Vref– AIN AIN P31-P37 Data I/O P40-P47 Data I/O P50-P57 Data I/O DSP0-DSP1 Data 0 XTAL1 OSC1 General-Purpose I/O Port General-Purpose I/O Port General-Purpose I/O Port General-Purpose 0 Port 20.48 MHz Crystal Oscillator Input Vref+ AIN XTAL2 OSC2 AN VDD Power /RESET PWM I/O Out 20.48 MHz Crystal Oscillator Input System RESET 10-Bit PWM, 5V TTL Output AN GND Power P00-P07 Data P10-P17 Data P20-P27 Data I/O I/O I/O 4 5V Power Input (Digital Power) Device Ground (Digital Ground) 8-Bit A to D Converter Input Low Reference Level for A to D Converter High Reference Level for A to D Converter ADC +5V Power (Analog Power) ADC Ground (Analog Ground) General-Purpose I/O Port General-Purpose I/O Port General-Purpose I/O Port Function Direction CP96TAD0103 Z89165/166/167/168/169 DTAD CONTROLLERS ZILOG VCC P41 P40 C_DIN C_DOUT P43 P42 P47 P46 P45 P44 /DS P22 P21 P20 XTAL1 XTAL2 P27 P26 P25 P24 P23 PIN DESCRIPTION (Continued) 1 84 11 12 75 74 ADDR0 C_CLOCK C_EN0 C_EN1 ADDR1 ADDR2 ADDR3 P50 P51 ADDR4 ADDR5 P52 P53 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ARAM_SEL0 ARAM_SEL1 DATA0 DATA1 OUT_5V GND /AS P37 P36 P35 P34 Z89168 84-Pin PLCC 54 R/W P13 P16 P15 P14 P17 53 VCC VCC P02 P01 P00 P03 ARAM_R/W /RESET P07 P06 P05 P04 42 43 P33 P32 P31 PWM P10 GND P12 P11 32 33 ARAM_OE DATA2 DATA3 /RAS /CAS GND VCC Z89168 84-Pin PLCC Pin Identification CP96TAD0103 5 Z89165/166/167/168/169 DTAD CONTROLLERS ZILOG PIN DESCRIPTION (Continued) Z89168 84-Pin PLCC Pin Identification I/O Port Functions Pin Number VSS VCC 32, 54, 65 12, 44, 74, 45 P00-P07 P10-P17 P20-P27 P31-P37 43-36 55, 53-51, 49-46 2-9 57-63 Input/Output Input/Output Input/Output Input/Output P40-P47 P50-P53 77-84 70-67 Input/Output Input/Output P00-P07 (General-purpose nibble programmable I/O port.) P10-P17 (General-purpose byte programmable I/O port.) P20-P27 (General-purpose bit programmable I/O.) P31-P37 (General-purpose I/O port. Bits P31-P33 are inputs, while bits P34-P37 are outputs.) P40-P47 (General-purpose bit programmable I/O.) P50-P53 (General-purpose bit programmable I/O.) C_DIN C_DOUT C_CLOCK C_ENA0 C_ENA1 76 75 73 72 71 Input Output Output Output Output Data input from CODEC. Data output to CODEC. CODEC clock (2.048 MHz) CODEC 0 enable (8 kHz) CODEC 1 enable (8 kHz) PWM 56 Output Pulse Width Modulator output DATA0 DATA1 DATA2 DATA3 ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 26 27 28 29 13 14 15 16 17 18 19 20 21 22 23 Input/Output Input/Output Input/Output Input/Output Output Output Output Output Output Output Output Output Output Output Output ARAM_SEL0 24 Output ARAM_SEL1 25 Output /RAS /CAS ARAM_R/W ARAM_/OE 30 31 34 33 Output Output Output Output Data 0 I/O of the ARAM Interface Data 1 I/O of the ARAM Interface Data 2 I/O of the ARAM Interface Data 3 I/O of the ARAM Interface Address 0 line of the ARAM Interface Address 1 line of the ARAM Interface Address 2 line of the ARAM Interface Address 3 line of the ARAM Interface Address 4 line of the ARAM Interface Address 5 line of the ARAM Interface Address 6 line of the ARAM Interface Address 7 line of the ARAM Interface Address 8 line of the ARAM Interface Address 9 line of the ARAM Interface Address 10 line of the ARAM Interface for 4 Meg ARAMs. Select 2 output of ARAM Interface for 1 Meg ARAMs support. The latter mode is used to switch between different pages of ARAM. Select 0 output of ARAM Interface. Used to switch between different pages of ARAM. Select 1 output of ARAM Interface. Used to switch between different pages of ARAM. Row Address Strobe of ARAM Interface. Column Address Strobe of ARAM Interface. Read/Write Strobe of ARAM Interface. Output Enable Strobe of ARAM Interface. XTAL1 XTAL2 11 10 Input Output 24.57 MHz crystal input 24.57 MHz crystal output /Reset R/W /AS /DS 35 50 64 1 Input Output Output Output /RESET input Z8 ® external memory interface R/W output Z8 external memory interface /AS output Z8 external memory interface /DS output 6 I/O Function Digital Ground Digital VCC = +5 V CP96TAD0103 Z89165/166/167/168/169 DTAD CONTROLLERS ZILOG VCC P41 P40 C_DIN C_DOUT P43 P42 P47 P46 P45 P44 /DS P22 P21 P20 XTAL1 XTAL2 P27 P26 P25 P24 P23 PIN DESCRIPTION (Continued) 1 84 11 12 75 74 ADDR0 C_CLOCK C_EN0 C_EN1 ADDR1 ADDR2 ADDR3 P50 P51 ADDR4 ADDR5 P52 P53 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ARAM_SEL0 ARAM_SEL1 DATA0 DATA1 OUT_5V GND /AS P37 P36 P35 P34 Z89C169/Z89C167 84-Pin PLCC 54 R/W P13 P16 P15 P14 P17 53 VCC RMLS P02 P01 P00 P03 ARAM_R/W /RESET P07 P06 P05 P04 42 43 P33 P32 P31 PWM P10 GND P12 P11 32 33 ARAM_OE DATA2 DATA3 /RAS /CAS GND VCC Z89167/169 84-Pin PLCC Pin Identification CP96TAD0103 7 Z89165/166/167/168/169 DTAD CONTROLLERS ZILOG PIN DESCRIPTION (Continued) Z89169/Z89167 84-Pin PLCC, Pin Identification I/O Port Functions Pin Number VSS VCC 32, 54, 65 12, 44, 74 P00-P07 P10-P17 P20-P27 P31-P37 43-36 55, 53-51, 49-46 2-9 57-63 Input/Output Input/Output Input/Output Input/Output P40-P47 P50-P53 77-84 70-67 Input/Output Input/Output P00-P07 (General-purpose nibble programmable I/O port.) P10-P17 (General-purpose byte programmable I/O port.) P20-P27 (General-purpose bit programmable I/O.) P31-P37 (General-purpose I/O port. Bits P31-P33 are inputs, while bits P34-P37 are outputs.) P40-P47 (General-purpose bit programmable I/O.) P50-P53 (General-purpose bit programmable I/O.) C_DIN C_DOUT C_CLOCK C_ENA0 C_ENA1 76 75 73 72 71 Input Output Output Output Output Data input from CODEC. Data output to CODEC. CODEC clock (2.048 MHz) CODEC 0 enable (8 kHz) CODEC 1 enable (8 kHz) PWM 56 Output Pulse Width Modulator output DATA0 DATA1 DATA2 DATA3 ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 26 27 28 29 13 14 15 16 17 18 19 20 21 22 23 Input/Output Input/Output Input/Output Input/Output Output Output Output Output Output Output Output Output Output Output Output ARAM_SEL0 24 Output ARAM_SEL1 25 Output /RAS /CAS ARAM_R/W ARAM_/OE 30 31 34 33 Output Output Output Output Data 0 I/O of the ARAM Interface Data 1 I/O of the ARAM Interface Data 2 I/O of the ARAM Interface Data 3 I/O of the ARAM Interface Address 0 line of the ARAM Interface Address 1 line of the ARAM Interface Address 2 line of the ARAM Interface Address 3 line of the ARAM Interface Address 4 line of the ARAM Interface Address 5 line of the ARAM Interface Address 6 line of the ARAM Interface Address 7 line of the ARAM Interface Address 8 line of the ARAM Interface Address 9 line of the ARAM Interface Address 10 line of the ARAM Interface for 4 Meg ARAMs. Select 2 output of ARAM Interface for 1 Meg ARAMs support. The latter mode is used to switch between different pages of ARAM. Select 0 output of ARAM Interface. Used to switch between different pages of ARAM. Select 1 output of ARAM Interface. Used to switch between different pages of ARAM. Row Address Strobe of ARAM Interface. Column Address Strobe of ARAM Interface. Read/Write Strobe of ARAM Interface. Output Enable Strobe of ARAM Interface. XTAL1 XTAL2 11 10 Input Output 24.57 MHz crystal input 24.57 MHz crystal output ROMLESS 45 Input /Reset R/W /AS /DS 35 50 64 1 InputOutput Output Output Output Z8 ® Romless mode input (P0 and P1 are switched to D/A mode if this pin is connected to VCC). Internally this pin is tight to GND. /RESET input/output Z8 external memory interface R/W output Z8 external memory interface /AS output Z8 external memory interface /DS output 8 I/O Function Digital Ground Digital VCC = +5 V CP96TAD0103 Z89165/166/167/168/169 DTAD CONTROLLERS ZILOG ABSOLUTE MAXIMUM RATINGS Symbol V CC TSTG TA Description Min Max Supply Voltage (*) –0.3 Storage Temp –65° Oper Ambient Temp Power Dissipation +7.0 +150° † 2.2 Units V C C W Notes: * Voltage on all pins with respect to GND. † See Ordering Information. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability. STANDARD TEST CONDITIONS +5V The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (Test Load Diagram). 2.1 kΩ From Output Under Test 150 pF 9.1 kΩ Test Load Diagram CAPACITANCE TA = 25°C, VCC = GND = 0V, f = 1.0 MHz, unmeasured pins to GND. Parameter Max Input capacitance Output capacitance I/O capacitance 12 pF 12 pF 12 pF DC ELECTRICAL CHARACTERISTICS Sym Parameter ICC ICC1 ICC2 Supply Current Halt Mode Current Stop Mode Current VCC Note [1] 5.0 V 5.0 V TA = 0°C to +70°C Min Max 65 20 Typical @ 25°C Units 40 6 mA mA Notes [2] Notes: [1] 5.0V ± 0.5V. [2] The typical Stop Mode Current value is 500 µA. The transient characteristics of the Stop Mode Current will vary according to the application and should be validated in the specific application by the customer. CP96TAD0103 9 Z89165/166/167/168/169 DTAD CONTROLLERS ZILOG DC ELECTRICAL CHARACTERISTICS Z89165/Z89166 Sym Parameter VCC Note [1] TA = 0° C to +70° Min Max Typical @ 25°C Units Conditions VMAX VCH Max Input Voltage Clock Input High Voltage 5.0V 5.0V 0.9 VCC 7 VCC+0.3 2.5 V V IIN = 250 µA Driven by External Clock Generator VCL VIH Clock Input Low Voltage Input High Voltage 5.0V 5.0V GND-0.3 0.7 VCC 0.1 VCC VCC+0.3 1.5 2.5 V V Driven by External Clock Generator VIL VOH Input Low Voltage Output High Voltage 5.0V 5.0V GND-0.3 VCC-0.4 0.2 VCC 1.5 4.8 V V IOH = -2.0 mA (Does not include XTAL2) VOL1 VOL2 Output Low Voltage Output Low Voltage 5.0V 5.0V 0.4 1.2 0.1 0.3 V V IOH = +4.0 mA IOL = +12 mA, 3 Pin Max VCC 0.2 VCC 2.1 1.7 V V 25 10 mV (Does not include XTAL2) VRH VRl Reset Input High Voltage Reset Input Low Voltage 5.0V 5.0V VOFFSET Comparator Input Offset Voltage IIL Input Leakage 5.0V 5.0V -5 5 <5 µA VIN = OV, VCC IOL IIR 5.0V 5.0V -5 5 -55 <5 -30 µA µA VIN = OV, VCC Output Leakage Reset Input Current 0.8 VCC GND-0.3 Notes: [1] 5.0 ± 10% (V). 10 CP96TAD0103 Z89165/166/167/168/169 DTAD CONTROLLERS ZILOG Z891650A ADDITIONAL DC ELECTRICAL CHARACTERISTICS 1. A/D CONVERTER: ABSOLUTE INPUT CURRENT VALUES Symbol Parameter Maximum Notes Iil Iih Iinput Anin Anin Vref+ Iinput Vref– 40 µA 2 µA 1.1 mA 80 µA 1.1 mA 80 µA With Vref– = 0V With Vref– = Vref+ With Vref+ = 5.5V With Vref+ = Vref+ Vref+ = 5.5V Vref+ = 5.5V Vref– = 0V Vref– = 0V The following parameters should be verified on the ATE under these conditions: 5.5V @ 25°C. 2. OTHER PINS Pin Under Test V a l u e Additional Condition Romless Pin Iih(max) = Iil (max) = Iih(max) = 6 µA 6 µA 1mA No Reset No Reset During Reset XTAL1 Iih(max) = Iil (max) = 30 µA 30 µA While XTAL2 = 0V While XTAL2 = 5.5V No Reset No Reset XTAL2 Iih(max) = Iil (max) = 10 µA 10 µA While XTAL1 = 0V While XTAL2 = 5V Stop Mode Invoked Stop Mode Invoked Iih (max) = Iil (max) = 1 mA 1 mA While XTAL1 = 0V While XTAL2 = 5V No Reset No Reset Iih(max) = Iil (max) = 4 mA 4 mA While XTAL1 = 0V While XTAL2 = 5V During Reset During Reset IOL(min) = IOH(min) = 2 mA -1mA VOL = 1V VOH = VDD -1V VDD = 4.5V Temp = 70°C VDD = 4.5V Temp = 70°C IOL(max) = IOH(max) = 7 mA 6mA VOL = 1V VOH = VDD -1V VDD = 5.5V Temp = 0°C VDD = 5.5V Temp = 0°C P31, P32, P33 Iih(max) = (max) = 1 µA 1 µA CP96TAD0103 11 Z89165/166/167/168/169 DTAD CONTROLLERS ZILOG DC ELECTRICAL CHARACTERISTICS Z89167/168/169 T A = 0° C to +70 °C Sym Parameter VCC Min Max Max Input Voltage 4.5V 5.5V 4.5V 5.5V 0.9 VCC 0.9 VCC 7 7 VCC+0.3 VCC+0.3 4.5V 5.5V 4.5V 5.5V GND-0.3 GND-0.3 0.7 VCC 0.7 VCC 4.5V 5.5V 4.5V 5.5V GND-0.3 GND-0.3 VCC-0.4 VCC-0.4 4.5V 5.5V 4.5V 5.5V 0.6 0.4 1.2 1.2 4.5V 5.5V 4.5V 5.5V .8 VCC .8 VCC GND-0.3 GND-0.3 -5 -5 VCH Clock Input High Voltage VCL Clock Input Low Voltage VIH Input High Voltage VIL Input Low Voltage VOH Output High Voltge VOL1 Output Low Voltage VOL2 Output Low Voltage VRH Reset Input High Voltage VRl Reset Input Low Voltage VOFFSET IIL Comparator Input Offset Voltage Input Leakage 4.5V 5.5V 4.5V 5.5V IOL Output Leakage IIR Reset Input Current 4.5V 5.5V 4.5V 5.5V -5 -5 Typical Units 25°C at Conditions Notes 1.3 2.5 V V V V IIN 250 uA IIN 250 uA Driven by External Clock Generator Driven by External Clock Generator 0.1 VCC 0.1 VCC VCC+0.3 VCC+0.3 0.7 1.5 1.3 2.5 V V V V Driven by External Clock Generator Driven by External Clock Generator 0.2 VCC 0.2 VCC 0.7 1.5 3.1 4.8 V V V V IOH = -2.0 mA IOH = -2.0 mA 0.2 0.1 0.3 0.3 V V V V IOH = +4.0 mA IOL = +4.0 mA IOL = +6 mA, 3 Pin Max IOL = +12 mA, 3 Pin Max VCC VCC 0.2 VCC 0.2 VCC 1.5 2.1 1.1 1.7 V V 25 25 5 5 10 10 <5 <5 mV mV µA µA 5 5 -45 -55 <5 <5 -20 -30 µA µA µA µA [1] VIN = OV, VCC VIN = OV, VCC VIN = OV, VCC VIN = OV, VCC Note: [1] P10, P11 are measured at 4.5V only. 12 CP96TAD0103 Z89165/166/167/168/169 DTAD CONTROLLERS ZILOG AC CHARACTERISTICS External I/O or Memory Read and Write Timing Diagram R//W 13 12 Port 0, /DM 16 3 19 Port 1 A7 - A0 1 D7 - D0 IN 2 9 /AS 8 18 11 4 5 /DS (Read) 6 17 10 Port1 A7 - A0 D7 - D0 OUT 14 15 7 /DS (Write) External I/O or Memory Read/Write Timing CP96TAD0103 13 Z89165/166/167/168/169 DTAD CONTROLLERS ZILOG AC CHARACTERISTICS Z89165/166 External I/O or Memory Read and Write Timing Table TA=0°C to +70 °C Min Max No Symbol Parameter VCC Note [4] 1 2 TdA(AS) TdAS(A) Address Valid to /AS Rise Delay /AS Rise to Address Float Delay 5.0V 5.0V 25 35 3 4 TdAS(DR) TwAS /AS Rise to Read Data Req’d Valid /AS Low Width 5.0V 5.0V 5 6 TdAZ(DS) TwDSR Address Float to /DS Fall /DS (Read) Low Width 7 8 TwDSW TdDSR(DR) 9 10 Units Notes ns ns [2,3] [2,3] 35 ns ns [1,2,3] [2,3] 5.0V 5.0V -3 125 ns ns [1,2,3] /DS (Write) Low Width /DS Fall to Read Data Req’d Valid 5.0V 5.0V 75 ns ns [1,2,3] [1,2,3] ThDR(DS) TdDS(A) Read Data to /DS Rise Hold Time /DS Rise to Address Active Delay 5.0V 5.0V 0 40 ns ns [2,3] [2,3] 11 12 TdDS(AS) TdR/W(AS) /DS Rise to /AS Fall Delay R//W Valid to /AS Rise Delay 5.0V 5.0V 35 25 ns ns [2,3] [2,3] 13 14 TdDS(R/W) /DS Rise to R//W Not Valid TdDW(DSW) Write Data Valid to /DS Fall (Write) Delay 5.0V 5.0V 35 40 ns ns [2,3] [2,3] 15 16 TdDS(DW) TdA(DR) /DS Rise to Write Data Not Valid Delay Address Valid to Read Data Req’d Valid 5.0V 5.0V 25 ns ns [2,3] [1,2,3] 17 18 19 TdAS(DS) TdDI(DS) TdDM(AS) /AS Rise to /DS Fall Delay Data Input Setup to /DS Rise /DM Valid to /AS Fall Delay 5.0V 5.0V 5.0V 48 50 20 ns ns ns [2,3] [1,2,3] [2,3] 150 90 180 Notes: [1] When using extended memory timing add 2 TpC. [2] Timing numbers given are for minimum TpC. [3] See clock cycle dependent characteristics table. [4] 5.0 V ± 0.5 V. Standard Test Load All timing references use 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0. 14 CP96TAD0103 Z89165/166/167/168/169 DTAD CONTROLLERS ZILOG AC CHARACTERISTICS Z89167/168/169 External I/O or Memory Read and Write Timing Table TA=0°C to +70°C Min Max No Symbol Parameter VCC Note [4] 1 2 TdA(AS) TdAS(A) Address Valid to /AS Rise Delay /AS Rise to Address Float Delay 5.0V 5.0V 18 22 3 4 TdAS(DR) TwAS /AS Rise to Read Data Req’d Valid /AS Low Width 5.0V 5.0V 5 6 TdAZ(DS) TwDSR Address Float to /DS Fall /DS (Read) Low Width 7 8 TwDSW TdDSR(DR) 9 10 Units Notes ns ns [2,3] [2,3] 28 ns ns [1,2,3] [2,3] 5.0V 5.0V 0 90 ns ns [1,2,3] /DS (Write) Low Width /DS Fall to Read Data Req’d Valid 5.0V 5.0V 62 ns ns [1,2,3] [1,2,3] ThDR(DS) TdDS(A) Read Data to /DS Rise Hold Time /DS Rise to Address Active Delay 5.0V 5.0V 0 36 ns ns [2,3] [2,3] 11 12 TdDS(AS) TdR/W(AS) /DS Rise to /AS Fall Delay R//W Valid to /AS Rise Delay 5.0V 5.0V 25 18 ns ns [2,3] [2,3] 13 14 TdDS(R/W) /DS Rise to R//W Not Valid TdDW(DSW) Write Data Valid to /DS Fall (Write) Delay 5.0V 5.0V 22 18 ns ns [2,3] [2,3] 15 16 TdDS(DW) TdA(DR) /DS Rise to Write Data Not Valid Delay Address Valid to Read Data Req’d Valid 5.0V 5.0V 23 ns ns [2,3] [1,2,3] 17 18 19 TdAS(DS) TdDI(DS) TdDM(AS) /AS Rise to /DS Fall Delay Data Input Setup to /DS Rise /DM Valid to /AS Fall Delay 5.0V 5.0V 5.0V 32 28 18 ns ns ns [2,3] [1,2,3] [2,3] 130 55 160 Notes: [1] When using extended memory timing add 2 TpC. [2] Timing numbers given are for minimum TpC. [3] See clock cycle dependent characteristics table. [4] 5.0 V ± 0.5 V. Standard Test Load All timing references use 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0. CP96TAD0103 15 Z89165/166/167/168/169 DTAD CONTROLLERS ZILOG AC ELECTRICAL CHARACTERISTICS Additional Timing Diagram 3 1 Clock 2 7 2 3 7 TIN 4 5 6 IRQN 8 9 Clock Setup 11 Stop Mode Recovery Source 10 Additional Timing 16 CP96TAD0103 Z89165/166/167/168/169 DTAD CONTROLLERS ZILOG AC ELECTRICAL CHARACTERISTICS Z89165/166 Additional Timing Table No Symbol Parameter VCC Note [6] TA=0°C to +70°C Min Max 1 2 TpC TrC,TfC Input Clock Period Clock Input Rise & Fall Times 5.0 V 5.0 V 48.83 3 4 TwC TwTinL Input Clock Width Timer Input Low Width 5.0 V 5.0 V 17 70 5 6 TwTinH TpTin Timer Input High Width Timer Input Period 5.0 V 5.0 V 3TpC 8TpC TrTin, TfTin 8A TwIL Timer Input Rise & Fall Timer 5.0 V Int. Request Low Time 5.0 V 70 8B TwIL 9 TwIH Int. Request Low Time Int. Request Input High Time 5.0 V 5.0 V 3TpC 3TpC 10 Twsm Stop-Mode Recovery Width Spec 5.0 V ns 11 Tost Oscillator Startup Time 5.0 V 12 5TpC 5TpC 12 Twdt Watch-Dog Timer 5.0 V 5.0 V 5.0 V 5.0 V 3 6 12 50 ms ms ms ms 7 6 Units Notes ns ns [1] [1] ns ns [1] [1] [1] 100 ns [1] ns [1,2] [1] [1] [1] [3] D1=0, D0 = 0 [4] D1=0, D0 = 1 [4] D1=1, D0 = 0 [4] D1=1, D0 = 1 [4] Notes: [1] Timing Reference uses 0.9 V CC for a logic 1 and 0.1 VCC for a logic 0. [2] Interrupt request via Port 3 (P31-P33). [3] SMR-D5 = 0. [4] Reg. WDT. [5] 5.0V ± 0.5V. CP96TAD0103 17 Z89165/166/167/168/169 DTAD CONTROLLERS ZILOG AC ELECTRICAL CHARACTERISTICS Z89167/168/169 Additional Timing Table No Symbol Parameter VCC Note [5] TA=0°C to +70 °C Min Max 1 2 TpC TrC,TfC Input Clock Period Clock Input Rise & Fall Times 5.0 V 5.0 V 41.67 3 4 TwC TwTinL Input Clock Width Timer Input Low Width 5.0 V 5.0 V 16 70 5 6 TwTinH TpTin Timer Input High Width Timer Input Period 5.0 V 5.0 V 3TpC 8TpC 7 Timer Input Rise & Fall Timer 5.0 V 8A TrTin, TfTin TwIL Int. Request Low Time 5.0 V 70 8B 9 TwIL TwIH Int. Request Low Time Int. Request Input High Time 5.0 V 5.0 V 3TpC 3TpC 10 Twsm Stop-Mode Recovery Width Spec 5.0 V ns 11 Tost Oscillator Startup Time 5.0 V 12 5TpC 5TpC 12 Twdt Watch-Dog Timer 5.0 V 5.0 V 5.0 V 5.0 V 5 15 25 100 ms ms ms ms 6 Units Notes ns ns [1] [1] ns ns [1] [1] [1] 100 ns [1] ns [1,2] [1] [1] [1] [3] D1=0, D0 = 0 [4] D1=0, D0 = 1 [4] D1=1, D0 = 0 [4] D1=1, D0 = 1 [4] Notes: [1] Timing Reference uses 0.9 V CC for a logic 1 and 0.1 VCC for a logic 0. [2] Interrupt request via Port 3 (P31-P33). [3] SMR-D5 = 0. [4] Reg. WDT. [5] 5.0V ± 0.5V. 18 CP96TAD0103 Z89165/166/167/168/169 DTAD CONTROLLERS ZILOG AC ELECTRICAL CHARACTERISTICS Handshake Timing Diagrams Data In Valid Data In Next Data In Valid 2 1 3 /DAV (Input) Delayed DAV 4 5 RDY (Output) 6 Delayed RDY Input Handshake Timing Data Out Valid Data Out Next Data Out Valid 7 /DAV (Output) Delayed DAV 8 9 11 10 RDY (Input) Delayed RDY Output Handshake Timing CP96TAD0103 19 Z89165/166/167/168/169 DTAD CONTROLLERS ZILOG AC ELECTRICAL CHARACTERISTICS Z89165/166 Handshake Timing Table TA=0°C to +70 °C Min Max No Symbol Parameter VCC Note [1] Units Data Direction 1 2 TsDI(DAV) ThDI(RDY) Data In Setup Time RDY to Data Hold Time 5.0 V 5.0 V 0 0 ns ns IN IN 3 4 TwDAV TdDAVI(RDY) Data Available Width DAV Fall to RDY Fall Delay 5.0 V 5.0 V 40 ns ns IN IN 5 6 TdDAVId(RDY) TdDO(DAV) DAV Rise to RDY Rise Delay RDY Rise to DAV Fall Delay 5.0 V 5.0 V 0 ns ns IN IN 7 8 TcLDAV0(RDY) TcLDAV0(RDY) Data Out to DAV Fall Delay DAV Fall to RDY Fall Delay 5.0 V 5.0 V TpC 0 ns ns OUT OUT 9 TdRDY0(DAV) 10 TwRDY 11 TdRDY0d(DAV) RDY Fall to DAV Rise Delay RDY Width RDY Rise to DAV Fall Delay 5.0 V 5.0 V 5.0 V 40 ns ns ns OUT OUT OUT Units Data Direction ns ns IN IN ns ns IN IN 70 40 70 40 Notes: [1] 5.0 V ± 0.5 V AC ELECTRICAL CHARACTERISTICS Z89167/168/169 Handshake Timing Table TA=0°C to +70 °C Min Max No Symbol Parameter VCC Note [1] 1 2 TsDI(DAV) ThDI(RDY) Data In Setup Time Ready to Data In Hold Time 5.0 V 5.0 V 0 0 3 4 TwDAV TdDAVI(RDY) Data Available Width DAV Fall to RDY Fall Delay 5.0 V 5.0 V 110 5 6 TdDAVId(RDY) TdDO(DAV) DAV Rise to RDY Rise Delay RDY Rise to DAV Fall Delay 5.0 V 5.0 V 0 ns ns IN IN 7 8 TcLDAV0(RDY) TcLDAV0(RDY) Data Out to DAV Fall Delay DAV Fall to RDY Fall Delay 5.0 V 5.0 V 25 0 ns ns OUT OUT 9 TdRDY0(DAV) 10 TwRDY 11 TdRDY0d(DAV) RDY Fall to DAV Rise Delay RDY Width RDY Rise to DAV Fall Delay 5.0 V 5.0 V 5.0 V 80 ns ns ns OUT OUT OUT 115 80 115 80 Notes: [1] 5.0 V ± 0.5 V 20 CP96TAD0103 Z89165/166/167/168/169 DTAD CONTROLLERS ZILOG ELECTRICAL CHARACTERISTICS Z89165/166 A/D CONVERTER A/D Converter Electrical Characteristics V CC = 5.0V ± 10% Parameter Resolution Integral non-linearity Differential non-linearity Zero Error at 25°C Supply Range Input voltage range Conversion time Input capacitance on ANA VAHI range VALO range VAHI -–VALO Minimum 4.5 VALO 25 VALO +2.5 ANGND 2.5 Typical 8 0.5 0.5 5.0 Maximum 1 1 250 Units Bits LSB LSB mV 5.5 VAHI Volts Volts 2 60 AVCC AVCC–2.5 AVCC µsec pF Volts Volts Volts Notes: Voltage 4.5V –5.5V Temp 0-70°C © 1997 by Zilog, Inc. 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CP96TAD0103 Zilog’s products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 FAX 408 370-8056 Internet: http://www.zilog.com 21 ZILOG 22 Z89165/166/167/168/169 DTAD CONTROLLERS CP96TAD0103