INTEGRAL IW4050B

TECHNICAL DATA
IW4050B
Hex Buffer/Converter
High-Voltage Silicon-Gate CMOS
The IW4050B is noninverting hex buffers and feature logic-level
conversion using only one supply (voltage (VCC). The input-signal high
level (VIH) can exceed the VCC supply voltage when these devices are
used for logic-level conversions. These devices are intended for use as
CMOS to DTL/TTL converters.
• Operating Voltage Range: 3.0 to 18 V
• Maximum input current of 1 µA at 18 V over full packagetemperature range; 100 nA at 18 V and 25°C
• Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
• High-to-low level conversion
ORDERING INFORMATION
IW4050BN Plastic
IW4050BD SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
NC = NO CONNECTION
FUNCTION TABLE
PINS 13, 16 = NO CONNECTION
PIN 1 =VCC
PIN 8 = GND
Inputs
Output
A
Y
L
L
H
H
93
IW4050B
MAXIMUM RATINGS*
Symbol
VCC
VIN
VOUT
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
Value
Unit
-0.5 to +20
V
VCC**
to +18
V
-0.5 to VCC +0.5
V
IIN
DC Input Current, per Pin
±10
mA
PD
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
mW
PD
Power Dissipation per Output Transistor
100
mW
-65 to +150
°C
260
°C
Tstg
TL
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
**
The IW4050B has high-to-low level voltage conversion capability but not low-to-high level; therefore it is
recommended that VIN ≥ VCC
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VIN
VOUT
TA
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Min
Max
Unit
3.0
18
V
VCC**
18
V
0
VCC
V
-55
+125
°C
**
The IW4050B has high-to-low level voltage conversion capability but not low-to-high level; therefore it is
recommended that VIN ≥ VCC
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range
GND≤(VIN or VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.
94
IW4050B
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC
Guaranteed Limit
V
≥-55°C
25°C
≤125
°C
Unit
5.0
10
15
3.5
7
11
3.5
7
11
3.5
7
11
V
Maximum Low -Level VOUT= 0.5V
Input Voltage
VOUT= 1.0 V
VOUT= 1.5V
5.0
10
15
1.5
3
4
1.5
3
4
1.5
3
4
V
VOH
Minimum High-Level
Output Voltage
VIN= VCC
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
4.95
9.95
14.95
V
VOL
Maximum Low-Level
Output Voltage
VIN=GND
5.0
10
15
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
V
IIN
Maximum Input
Leakage Current
VIN= GND or VCC
18
±0.1
±0.1
±1.0
µA
ICC
Maximum Quiescent
Supply Current
(per Package)
VIN= GND or VCC
5.0
10
15
20
1
2
4
20
1
2
4
20
30
60
120
600
µA
IOL
Minimum Output Low VIN= GND or VCC
(Sink) Current
UOL=0.4 V
UOL=0.4 V
UOL=0.5 V
UOL=1.5 V
4.5
5
10
15
3.3
4
10
26
2.6
3.2
8
24
1.8
2.4
5.6
18
Minimum Output
VIN= GND or VCC
High (Source) Current UOH=2.5 V
UOH=4.6 V
UOH=9.5 V
UOH=13.5 V
5.0
5.0
10
15
-2.6
-0.81
-2.0
-5.2
-2.1
-0.65
-1.65
-4.3
-1.55
-0.48
-1.18
-3.1
Symbol
Parameter
VIH
Minimum High-Level
Input Voltage
VIL
IOH
Test Conditions
VOUT= VCC - 0.5V
VOUT= VCC - 1.0 V
VOUT= VCC - 1.5V
mA
mA
95
IW4050B
AC ELECTRICAL CHARACTERISTICS(CL=50pF, RL=200kΩ, Input tr=tf=20 ns)
VIN
VCC
Guaranteed Limit
Symbol
Parameter
V
V
≥-55°C
25°C
≤125°C
Unit
tPLH
Maximum Propagation Delay, Input A to
Output Y (Figure 1)
5
10
10
15
15
5
10
5
15
5
140
80
90
60
80
140
80
90
60
80
280
160
180
120
160
ns
tPHL
Maximum Propagation Delay, Input A to
Output Y (Figure 1)
5
10
10
15
15
5
10
5
15
5
110
55
100
30
100
110
55
100
30
100
220
110
200
60
200
ns
tTLH
Maximum Output Transition Time, Any
Output (Figure 1)
5
10
15
5
10
15
160
80
60
160
80
60
320
160
120
ns
tTHL
Maximum Output Transition Time, Any
Output (Figure 1)
5
10
15
5
10
15
60
40
30
60
40
30
120
80
60
ns
CIN
Maximum Input Capacitance
-
-
Figure 1. Switching Waveforms
EXPANDED LOGIC DIAGRAM
(1/6 of the Device)
96
7.5
pF