AKM AK5602A

[AK5602A]
AK5602A
Energy Metering LSI for multi phase, high accurate application
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AK5602A
C IF
C_IF
C IF
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Operational Summary
Features
Suitable for three phase, 3 wired or 4 wired
AK5602A is one of the most advanced and functional
energy metering or energy monitoring application
LSIs for multi phase energy measurement.
Provide less than 0.1 % active & reactive energy
Current and voltage signals through CT, Hall sensor, or
error over a dynamic range of 1000 to 1,
Shunt Resistors are converted into digital signal with
compatible with IEC 0.5S
18bit ADC.
Provide instantaneous active power, reactive
Instantaneous voltage and current in each phase is
power and apparent power
multiplied and is added in total phases.
Provide voltage RMS, current RMS, voltage
The value changes into active power after passing
instantaneous value, current instantaneous value
through LPF and added with the value of a light load
and power factor in each phase.
register. After this value is compared with the value of
Provide less than 0.5 % voltage RMS, current
rated standard value register, it outputs pulses in
RMS and power factor error
proportion to the calculation.
Provide very accurate 90 degree phase shifter over
Regarding reactive power, input current is precisely
45Hz to 65Hz input frequency range, which is
shift by 90 degree and multiplied with respective voltage
used for reactive power calculation
input signal. It outputs pulses in the same manner of
Provide minute input voltage monitoring function
active power calculation.
And apparent power can be selectively derived from
Wide phase adjust. range between V & I (11 °)
Provide positive and negative power indication
either active power and reactive power calculation or
Built-in temperature sensor
VRMS x IRMS calculation and it outputs pulses as the
Single power supply (3 V or 5V)
result of calculation.
48LQFP
System Block Diagram
VIF
VIF
VIF
Active Power ( pulse, register )
Reactive Power ( pulse, register )
Apparent Power ( pulse, register )
Voltage RMS value, Current RMS value
Instantaneous voltage value & current value
Power factor
Wide phase adjustment range between
voltage and current ( ±11 ° at 50Hz)
Temperature sensor ( °C : Celsius )
Single voltage power supply ( 3V or 5V)
48P LQFP package
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Serial IF
LCD
MPU
Comm.
N Φ1 Φ2 Φ3
MS1285-E-00
EEPROM
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[AK5602A]
RPL
Ich 1
I1P
I1
I1N
V1
Ich 2
I2P
x1 to x32
PGA
I2N
Ich 3
I3P
SigmaDelta
Mod.
Gain
Adj.
HPF
x
Gain
Adj.
HPF
Phase
Adj.
FIR
90 degree
phase
shifter
x
RMS
Value
x
Vch 1
FIR
V2
PGA
SigmaDelta
Mod.
Phase
Adj.
I3
Calculation
Block (ch2)
Q1
V3P
Reference
Voltage
RPO
TPST
TPO
TPL
Q
RQL
XQ
+
+
Reactive
XQ+RQL (Apparent )
Power to
-1 x
Frequency
-XQ+TQL
Conversion
-XQ +
RQST
RQO
TQST
TQO
TQL
Vn
Threshold
VIN
Temp.
sensor
RPST
+
XP+RPL
P3
Q3
S3
PF3
Calculation
Block (ch3)
V3
Vch 3
LPF
P2
Q2
S2
PF2
x1 to x4
V2P
P1
Apparent S1
Power
I2
V1P
LPF
+
XP
Active
Power to
-1 x
Frequency
XP+TPL Conversion
-XP +
Power PF1
Factor
Calculation
Block (ch1)
I3N
Vch 2
P
V1 Frequency
Output
F1
V2 Frequency
Output
F2
V3 Frequency
Output
F3
Serial to pararell
conversion control
Oscillator
TEST3
TEST2
TEST1
DVSS
DVDD
BVSS
AVSS
AVDD
DO
DI
SCLK
CS
RDY
DIS
STBY
RST
XOUT
XIN
VCOM
VREFI
VREFO
VS
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[AK5602A]
2. Block feature
Block
PGA
(Programmable
Gain Amp)
Sigma Delta
Modulator
Phase Adjuster
Function
Current Input Gain selection (from ×1 to ×32)
Voltage Input Gain selection (from ×1 to ×4)
This PGA becomes operative with RST = STBY = “H”
Sigma Delta Modulator with 3 channel differential inputs.
This modulator becomes operative with RST = STBY = “H”
This adjusts the phase difference between current IF and voltage IF.
This phase shifter becomes operative with RST = STBY = “H”
FIR Filter
LPF. This produces 18 bit ADC data in current side and 16 bit ADC data
in voltage side from the sigma delta modulator.
This Filter becomes operative with RST = STBY = “H”
HPF
This HPF is a selectable filter. It removes the DC part arising from DC
offset of ADC or input signal.
In a case of passing through the DC part of input signal, only DC offset of
ADC can be removed by calibration command. This HPF is not selected
in the default setting. This HPF becomes operative with RST = STBY
Gain Adjustment
= “H”
Values of input current and input voltage can be adjusted against ideal
values with a gain adjustment (full-scale) command.
This adjustment becomes operative with RST = STBY = “H”
90 degree phase
shifter
90-degree phase shifter.
This shifter becomes operative with RST = STBY = “H”
RMS value calculator It calculates RMS value from an instantaneous signal.
This calculator becomes operative with RST = STBY = “H”
LPF
LPF.
This filter becomes operative with RST = STBY = “H”
Apparent power
calculator
Apparent power can be derived from either VRMS × IRMS calculation or
active power & reactive power calculation.
This calculator becomes operative with RST = STBY = “H”
Power Factor
Power factor can be derived from active power & apparent power
calculation.
Power factor becomes operative with RST = STBY = “H”
Active energy to
Positive active energy or negative active energy is converted into
frequency conversion respective frequency, which is proportional to its active energy.
This block becomes operative with RST = STBY = DIS = “H”
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[AK5602A]
Reactive energy to
Positive reactive energy or negative reactive energy is converted into
frequency conversion respective frequency, which is proportional to its reactive energy.
This block becomes operative with RST = STBY = DIS = “H”
Block
Function
Temperature sensor
This block measures the temperature of AK5602A.
This block becomes operative with RST = STBY = DIS = “H”
Frequency pulse
outputs
Each voltage input is digitized according to each threshold value, and
digitized frequency is output.
This block becomes operative with RST = STBY = “H”
Reference voltage
generator
This block generates 1.17V reference voltage.
This block becomes operative with RST = STBY = “H”
Oscillator
The crystal oscillator which oscillates around 12.9024MHz is connected.
This block becomes operative with RST = STBY = “H”
Serial to parallel
controller
Serial interface to CPU.
This block becomes operative with RST = “H”
2-1 Block operation mode
RST
STBY
DIS
L
H
H
H
L
L
H
H
L
L
L
H
Block operation mode
All blocks are off
Only serial to parallel controller block is operative.
All blocks except power to frequency conversion blocks are operative.
All blocks are operative.
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3. Pin description
AI : Analog input
AO : Analog output
Pin
Number
Pin
Name
DI : Digital input
DO : Digital output
PWR : Power
GND : Ground
Type
Function
1
RST
DI
Reset input ( Schmitt trigger input )
All circuits become inoperative with “L” level input.
All registers including input or output registers,
controlling registers, data registers are initialized.
2
STBY
DI
Standby input ( Schmitt trigger input )
All circuits except serial pararell controller block become
inoperative with “L” level input after RST = “H”
It is possible to write in and read registers through the
serial to the parallel conversion controller.
3
DIS
DI
Disable input ( Schmitt trigger input )
Active energy to frequency conversion and reactive energy
to frequency conversion blocks are stopped and data
registers in those blocks are initialized with “L” level input
after RST = STBY = “H”.
4
TQO
DO
Negative reactive power pulse output
“H” pulse is output when accumulated negative reactive
energy value is over the setting standard value.
This pin becomes inoperative when RST
= “L” or
STBY = “L” or DIS = “L”.
5
TQST
DO
Negative reactive energy flag output (This pin is not used
in IEC mode.)
“H” level is output when an interval of output pulses at
TQO is under the setting starting value.
This pin becomes inoperative when RST
= “L” or
STBY = “L” or DIS = “L”.
6
RQO
DO
Positive reactive energy pulse output
“H” pulse is output when accumulated positive reactive
power value is over the setting standard value.
This pin becomes inoperative when RST = “L” or STBY
= “L” or DIS = “L”.
7
RQST
DO
Positive reactive energy flag output (This pin is not used in
IEC mode.)
“H” level is output when an interval output pulses at RQO
is under the setting starting value.
This pin becomes inoperative when RST = “L” or STBY
= “L” or DIS = “L”.
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[AK5602A]
Pin
Number
8
Pin
Name
DVSS
9
10
Type
Function
GND
Digital ground.
DVDD
PWR
Digital power.
TPO
DO
Negative active energy pulse output.
“H” pulse is output when accumulated negative active power
value is over the setting standard value.
This pin becomes inoperative when RST = “L” or STBY =
“L” or DIS = “L”.
11
TPST
DO
Negative active power flag output.
“H’ level is output when an interval of output pulses at TPO
is under the setting starting value.
This pin becomes inoperative when RST = “L” or STBY
= “L” or DIS = “L”.
12
TEST1
DI
Internal use only. Connects to DVSS.
13
RPO
DO
Positive active energy pulse output
“H” pulse is output when accumulated positive active power
value is over the setting standard value.
This pin becomes inoperative when RST = “L” or STBY =
“L” or DIS = “L”.
14
RPST
DO
Positive active power flag output.
“H” level is output when an interval output pulses at RPO is
under the setting starting value.
This pin becomes inoperative when RST = “L” or STBY =
“L” or DIS = “L”.
15
16
17
18
TEST2
TEST3
BVSS
XOUT
DI
DI
GND
AO
Internal use only. Connects to DVSS.
Internal use only. Connects to DVSS.
Silicon base reference GND. Connects AVSS.
Crystal oscillator connection.
Connects 12.8 MHz oscillator.
19
XIN
AI
20
AVDD
PWR
Analog power.
21
AVSS
GND
Analog ground.
22
VREFO
AO
Reference voltage output, 1.17V
It outputs with the reference to AVSS. This output usually
connects to VREFI pin. Connects 4.7uF (under 10uF)
electrolytic capacitor and 0.1uF ceramic capacitor between
this pin and AGND. This output is an internal use only and
should not be connected to circuits outside the IC.
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[AK5602A]
Pin
number
23
Pin
name
VREFI
Type
Function
AI
Reference voltage input.
It usually connects to VREFO.
An outside VREF is connected between this pin and AVSS in
a case that an inside VREF of the IC is not used.
24
VCOM
AO
Common voltage output, 1.17V.
It feeds a common voltage to an internal block of the IC.
It should not be connected to the outside circuits of the LSI.
Connect 0.1uF ceramic capacitor between this pin and AVSS.
25
VS
AO
Controlling voltage output for input switches.
It generates the voltage which controls input switches
referenced to AVSS in ON and OFF state.
This is an internal use only. It should not be connected to the
outside circuits of the IC. Connects 0.1uF ceramic capacitor
between this pin and AVSS.
26
VIN
AI
Voltage side common analog negative input.
27
V3P
AI
Voltage side ch3 analog positive input.
28
V2P
AI
Voltage side ch2 analog positive input.
29
V1P
AI
Voltage side ch1 analog positive input.
30
NC
NC
31
I1P
AI
Current side ch1 analog positive input.
32
I1N
AI
Current side ch1 analog negative input.
33
I2P
AI
Current side ch2 analog positive input.
34
I2N
AI
Current side ch2 analog negative input.
35
I3P
AI
Current side ch3 analog positive input.
36
I3N
AI
Current side ch2 analog negative input.
No connection. Connects to AVSS.
37
NC
NC
No connection. Connects to AVSS.
38
RDY
DO
Reading approval pin of registers
The content of registers can be read when this pin becomes
“low”.
This pin becomes “high” when RST = “L” or STBY = “L” or
DIS = “L”.
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[AK5602A]
Pin
number
Pin
name
Type
Function
39
CS
DI
Serial interface selection input (Schmitt trigger input)
Serial interface become operative with “L” level input at
this pin while RST = “H”.
40
SCLK
DI
Serial data clock input
41
BVSS
GND
Silicon base reference GND. Connects to AVSS.
42
DVSS
GND
Digital ground.
43
DVDD
PWR
Digital power.
44
DI
DI
Serial data input
This DI pin becomes valid with CS = “L” while RST =
“H” and it inputs data in synchronization with the rising
edge of the clock at SCLK pin. Stored data is transferred
into the respective register in the synchronization with
the rising edge of CS .
45
DO
DO
Serial data output
This DO pin becomes valid with CS = “L” while RST =
“H” and it outputs data in synchronization with the
falling edge of the clock at SCLK pin.
This DO pin becomes a high impedance state except
CS = “L” while RST = “H”.
46
F3
DO
V3 frequency output
A rectangular wave produced by a waveform shaping
circuit is output.
This pin becomes low level when RST = “L” or STBY
47
F2
DO
= “L”.
V2 frequency output
A rectangular wave produced by a waveform shaping
circuit is output.
This pin becomes low level when RST = “L” or STBY
48
F1
DO
= “L”.
V1 frequency output
A rectangular wave produced by a waveform shaping
circuit is output.
This pin becomes low level when RST = “L” or STBY
= “L”.
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[AK5602A]
4. Electrical characteristics
4.1 Absolute maximum rating
Item
Symbol
MIN
MAX
Power supply voltage DVDD
-0.3
+6.5
AVDD
-0.3
+6.5
Ground level
AVSS
DVSS
BVSS
Input current
IIN
Analog input
voltage1
V INA1
Analog input
voltage2
0
Unit Reference
V
V
Voltage reference level
±10
mA
Except power pin
-0.3
(AVDD)+0.3
V
V INA2
-3.0
+3.0
V
Digital input voltage
I IND
-0.3
DVDD+0.3
V
Storage temperature
T stg
-50
125
°C
I1P, I1N, I2P,
I2N, I3P, I3N,
V1P, V2P, V3P, VIN
Note ) It may cause a permanent damage to the device if used beyond listed conditions.
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4.2 Recommended operating conditions
Item
Symbol
MIN
TYP
Unit
Reference
Power supply
voltage
AVDD
2.7
5.25
DVDD
2.7
5.25
V
Note 1
Analog reference
input voltage
VREF
1.11
1.23
V
Note 2
Analog input
maximum voltage
V AIN
MAX
-1.0
1.0
V
Note 3
Analog input
voltage
Operating
temperature
V AIN
-FS
+FS
V
Note 4
Ta
-40
85
°C
1.17
MAX
Note 1: -0.1V ≤ DVDD - AVDD ≤ +0.1V
Note 2: This is a case when outside reference voltage is connected to VREFI.
1.17V±5%
Note 3: This range of analog input signal is to be calculated.
Note 4:
VAIN = ( AINP ) - (AINN)
AINP: V1P, V2P, V3P; AINN: VIN
Gain
× 1 : -FS = -1.0V, +FS = 1.0V
× 2 : -FS = -0.5V, +FS = 0.5V
× 4 : -FS = -0.25V, +FS = 0.25V
AINP: I1P, I2P, I3P; AINN: I1N, I2N, I3N
Gain
× 1 : -FS = -1.0V, +FS = 1.0V
× 2 : -FS = -0.5V, +FS = 0.5V
× 8 : -FS = -0.125V, +FS = 0.125V
× 16 : -FS = -0.0625V, +FS = 0.0625V
× 24 : -FS = -0.0417V, +FS = 0.0417V
× 32 : -FS = -0.03125V, +FS = 0.03125V
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Regarding the analog voltage input, ADC outputs a plus full scale code (7FFFh ) against
the input over a +FS input and outputs a minus full scale code (8000h) against the input
under -FS.
Regarding the analog current input, ADC outputs a plus full scale code (1FFFFh) against
the input over a +FS input and outputs a minus full scale code (20000h) against the input
under -FS.
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[AK5602A]
4.3 Analog characteristics
Conditions: Ta=25°C, AVDD=DVDD=5.0V,
VREF = 1.17V, XCLK = 12.9024MHz,
Signal frequency = 50Hz, Measured bandwidth = 10 to 1.5kHz;
Unless otherwise specified.
4.3.1 PGA
Voltage side
Item
Input range
Gain setting :
×4 (12 dB)
×2 (6 dB)
×1 (0 dB)
Input impedance
MIN
TYP
±0.25
±0.5
±1.0
±0.95
350
MAX
±1.05
Unit
Reference
Vp-p
Note 5
kΩ
Note 6
Note 5: Only applicable for V (voltage) input. This is a full-scale value of analog input voltage
(VAIN= (AINP) - (AINN)). VIN is usually connected to AGND and each analog input
voltage is added with reference to VIN.
Note 6: Input impedance between AINP (V1P, V2P, V3P) and AINN (VIN).
Minimum value is when gain is set at ×4 (12dB). Input impedance is reversed
proportional to the gain setting.
Current side
Item
Input range
Gain setting:
×32 (30dB)
×24 (27.6dB)
×16 (24 dB)
×8 (18 dB)
×4 (12 dB)
×2 (6 dB)
×1 (0 dB)
Input impedance
MIN
TYP
±0.0313
±0.0417
±0.0625
±0.125
±0.25
±0.5
±1.0
±0.95
200
MAX
±1.05
Unit
Reference
Vp-p
Note 7
kΩ
Note 8
Note 7: Only applicable for I(current) input (differential input). This is a full-scale value of
analog input voltage (VAIN = (AINP) - (AINN)).
Note 8: Input impedance between AINP (I1P, I2P, I3P) and AINN (I1N, I2N, I3N).
Minimum value is when gain is set at ×8 (18dB). Input impedance is reversed
proportional to gain setting.
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[AK5602A]
4.3.2 ADC
Voltage side
Item
MIN
TYP
Resolution
MAX
Unit
16
bit
S/N+D
65
dB
Isolation between
current and voltage
100
dB
100
dB
Crosstalk between
voltage channels
Power factor adjustment
range between current
and voltage
Power factor adjustment
accuracy between
current and voltage
ADC period
-613.84
613.84
Reference
Note 9
Note 10
us
Note 11
1.24
us
Note 12
3.15
kHz
Note 13
Note 9: This is the value when analog input signal is applied at -6dB of full scale value with
PGA = 0 dB. This is the ratio between RMS value of input signal and summation of
RMS values of all frequencies from 10Hz to 1.5kHz excluding the input signal.
Note 10: This is the isolation value between voltage side ADC and current side ADC.
Note 11: This is the delay adjustment range of voltage side against current side.
+ side setting delays starting point of A/D conversion at voltage side against starting
point of A/D conversion at current side in the range of 0us to +613.84us, while - side
setting delays starting point of A/D conversion at current side against starting point of
A/D conversion at voltage side in the range of 0us to +613.84us. This enables the delay
adjustment range at voltage side against current side from -613.84us to +613.84us.
Please note that when the delay adjustment is changed from + to - or - to + during the
operation of the IC, A/D conversion data becomes uncontinuous.
Note 12: Delay adjustment step is 1.24us.
Note 13: ADC period is 3.15kHz at every channel.
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[AK5602A]
Current side
Item
MIN
TYP
Resolution
MAX
Unit
18
bit
S/N+D
65
dB
Isolation between
current and voltage
100
dB
100
dB
3.15
kHz
Crosstalk between
current channels
ADC period
Reference
Note 14
Note 15
Note 16
Note 14: This is the value when analog input signal is applied at -6dB of full scale value with
PGA = 0 dB. This is the ratio between RMS value of input signal and summation of
RMS values of all frequencies from 10Hz to 1.5kHz excluding the input signal.
Note 15: This is the isolation value between voltage side ADC and current side ADC.
Note 16: ADC period is 3.15kHz at every channel.
4.3.3 Reference voltage
Item
MIN
TYP
MAX
Unit
Reference
VREF output level
1.11
1.17
1.23
V
Note 17
ppm/°C
Note 18
VREF temperature drift
30
Note 17: Output level of VREFO. It outputs 1.17V±5% with reference to AVSS.
Note 18: The temperature drift of VREFO output level.
4.3.4 Temperature sensor
Item
MIN
Temperature range
-40
TYP
MAX
Unit
85
°C
Reference
Resolution
1
°C
Note 19
Accuracy
±5
°C
Note 20
Note 19: Resolution value when the value of temperature register is read from the register.
Note 20: This is the difference between the value of temperature register and real value at
25°C.
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[AK5602A]
4.3.5 Power supply
Item
MIN
TYP1
TYP2
MAX
Unit
Reference
Power consumption
18
40
70
mW
Note 21
Standby Current
1
1
20
uA
Note 21
Note 21: TYP1 is the value at AVDD = DVDD = 3.0V and TYP2 is the value at AVDD = DVDD
= 5.0V. Consumption current is measured on condition of which all digital inputs
are connected to DVDD or DVSS and all analog inputs are connected to analog
input bias level. It does not contain output current. AVDD = DVDD = 2.7V to 5.25V.
4.3.6 Filter characteristics
Ta = -40 to 85°C, AVDD=DVDD=2.7V to 5.25V,
XCLK=12.9024 MHz (Filter characteristics is proportional to the frequency of XCLK.)
4.3.6.1 FIR filter (LPF)
Item
Pass band
MIN
±0.008dB
45
+0.008dB
-0.910dB
0
Attenuation
at 10.0kHz
level at stop band
TYP
MAX
Unit
66
Hz
Reference
1500
74.0
dB
4.3.6.2 HPF
Item
Frequency
response
Phase shift value
MIN
-3 dB
-0.5 dB
-0.1dB
-0.004 dB
-0.002 dB
45 to 66Hz
TYP
MAX
1.3
3.6
8.7
45
Unit
Reference
Hz
66
1.13
MS1285-E-00
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degree
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[AK5602A]
4.3.6.3 90 degree phase shifter
Item
Phase shift
value
45 to 66Hz
Gain error
0 to 1500Hz
MIN
TYP
MAX
Unit
Reference
89.98
90
90.02
degree
Note 22
± 0.001
dB
Note 23
Note 22: Phase difference between two inputs.
Note 23: Gain error between input and output of 90 degree phase shifter.
4.3.6.4 IIR filter ( LPF )
Item
MIN
Pass band
Attenuation
level at stop
band
±0.1dB
0
at 100Hz
60
TYP
MAX
Unit
0.4
Hz
Reference
dB
4.3.7 DC characteristics
Ta = -40 to 85°C, AVDD=DVDD=2.7 to 5.25V
Item
Symbol
MIN
High level input voltage
VIH
0.7(DVDD)
Low level input voltage
VIL
High level output voltage VOH
Iout=0.5mA
For RPO/TPO/RQO/TQO
Iout=2mA
TYP
MAX
Unit
Reference
V
Note 24
0.3(DVDD)
V
Note 24
(DVDD)-0.4
Low level output voltage
Iout=-0.5mA
For RPO/TPO/RQO/TQO
Iout=-2mA
VOL
0.4
V
Input leak current
IIN
±10
uA
Note 24: Except TEST1, TEST2, and TEST3 pins.
MS1285-E-00
2011/02
- 15 -
[AK5602A]
4.3.8 Switching characteristics
Ta=-40 to 85°C, AVDD=DVDD=2.7~5.25V,
CL=20pF, XCLK=12.9024MHz
Item
Symbol
Pin
Serial Clock Frequency
fSCLK
SCLK
“H” pulse width
tSCKH
SCLK
tOUTH
RPO,TPO
RQO,TQO
tSCKL
SCLK
100
tRSTL
RST
1
tSTBL
STBY
1
tDISL
DIS
1
tCCKH
CS→SCLK
100
tCKDH
SCLK
→DI
50
tCKDS
SCLK
→DI
50
tCCKS
CS
→ SCLK
100
tCKDV
SCLK
→DO
SCLK
→DO
“L” pulse width
Hold time
Setup time
Data output
tCKDZ
MIN
TYP
MAX
Unit
4
MHz
100
59.5
±0.2
ns
Fig.1
us
Fig.3
Note 25
ns
Fig.1
us
80
Reference
Fig.4
ns
Fig.1
ns
Fig.1
ns
Fig.2
200
Note 25: In case of PULSW11-0=000H (default).
MS1285-E-00
2011/02
- 16 -
[AK5602A]
In writing
0.7DVDD
CS
0.3DVDD
tCCKH
tSCKH
tCCKS
0.7DVDD
SCLK
0.3DVDD
tCKDS
tCKDH
tSCKL
0.7DVDD
DI
0.3DVDD
Fig.1
In reading
0.7DVDD
CS
0.3DVDD
tCCKH
tSCKH
tCCKS
0.7DVDD
SCLK
0.3DVDD
tCKDV
DO
tSCKL
tCKDZ
High-Z
High-Z
Fig.2
tOUTH
RPO
RST
TPO
STBY
RQO
Fig.3
0.7DVDD
0.3DVDD
tRSTL
tSTBL
DIS
Fig.4
TQO
tDISL
(Note) Reading and writing control is executed by commands of Control setting register,
ADD.’21h’.
MS1285-E-00
2011/02
- 17 -
[AK5602A]
5. Function
5.1 Power on sequence
Operation
Comment
phase
Ph1
Operation of all circuits including serial interface and oscillator
circuits is halted and digital circuits including input / output register,
control register and data register are initialized. At the same time F1,
F2, F3, RPO, TPO, RQO,TQO, TPST, RQST and TQST becomes “L”
RST : L
level and DO becomes high impedance state.
A serial interface circuit (input / output register) becomes active and it
Ph2
STBY : L
is possible to write in and read registers.
RST : H
All circuits except active power to frequency conversion circuit and
Ph3
reactive power to frequency conversion circuit become active. At this
moment, RPO, TPO, RQO, TQO, RPST, TPST, RQST and TQST keeps
“L” level.
Oscillator circuit starts oscillation with RST = STBY = “H” and ADC
DIS
STBY
RST
:L
:H
:H
Ph4
DIS
STBY
RST
sequence is started. It normally needs 300mS before oscillation
frequency and HPF are stabilized. The accuracy of ADC and
calibration is not guaranteed during this period.
All circuits become active, but the changing of the state from Ph3 to
:H
Ph4 must be done after 300mS are being elapsed in Ph3 state.
:H
:H
AVDD=DVDD
RST
STBY
DIS
ph1
ph2
ph3
Fig.5
ph4
ph3
ph4
Power on sequence
MS1285-E-00
2011/02
- 18 -
[AK5602A]
5.2 Registers
5.2.1 Writing data into registers
It is possible to access a serial interface circuit with RST = “H”, CS = “L”.
By applying a serial clock at SCLK pin, input data is written into an input shift register.
Input data consists of 7 bits of address, one bit “L” level writing command and 16 bits data
strings.
The state of DI is sampled at rising edge of SCLK for 24 times after CS = “L” and
transferred into the shift register. 16 bits data, which have been written into input shift
data register will be transferred to the corresponding control register at the rising edge
of CS .
In a case that the number of clocks of SCLK is either less than 24 times or more than 25
times, input data will not be transferred into the corresponding control register.
The number of clocks of SCLK should be applied for 24 times even if the writing data
consist of less than 16 bits format. And SCLK must be started at “H” state and ended at
“H” state.
CS
1
2
7
8
9
10
A6
A5
A0
L
D15
D14
23
24
SCLK
DI
Starting address (8bit)
D1
D0
Writing in data
Fig.6 writing timing to registers
MS1285-E-00
2011/02
- 19 -
[AK5602A]
5.2.2 Reading data from registers
It is possible to access a serial interface circuit with RST = “H”, CS = “L”.
By applying a serial clock at SCLK pin, input data is written into an input shift register.
Input data consists of 7 bits of address, one-bit “H” level reading command is followed.
The state of DI is sampled at rising edge of SCLK for 8 times after CS = “L”, transferred
into the shift register and specified the starting address.
In the starting address, the first 7 bits show the address of the control register which data
should be stored and the next 1 bit shows either reading or writing. If the bit is “H”, it means
reading. If the bit is “L”, it means writing.
In case that data specified with only one address is read (when ADD. ‘21h’, bit1=’1’), 16 bit
data which is specified by reading indication register is loaded into the shift register from
the controlling register at the first falling edge of SCLK following after the starting address
and data is output at DO pin. After that, data is continuously output at every SCLK’s falling
edge and 16-bit data, which have been loaded into the output shift register are output.
Furthermore, the next 16-bit data at the next address are output if SCLK is input
continuously. This makes it possible to read data from registers continuously without
readdressing.
If SCLK is applied even after, data at the last address ADD. ‘59h’ being output, the LSI
outputs “L” as far as CS pin remains “L”. DO pin becomes high impedance state when
CS pin is controlled at “H” state. In a case that CS pin becomes “H” state before all data
being output, DO pin becomes high impedance state and reading procedure is halted.
In addition, SCLK must be started at “H” state and ended at “H” state.
When the data loading period into the output register and data renewal period coincide
each other, the bit15 (INVALID) of data at ADD. ‘21h’ becomes “H” level. The INVALID bit
at ADD. ‘21h’ keeps “H” level until the content of ADD. ‘21h’ will have been read, and it will
be cleared after the reading.
CS
1
2
7
8
A6
A5
A0
H
9
10
D15
D14
23
24
SCLK
DI
DO
Hi-Z
Starting address(8bit)
D1
D0
"L"
Reading data output
Fig.7 Reading timing from controlling registers
Initialization of registers
All registers are initialized and the initial values are loaded with “L” level at RST pin.
MS1285-E-00
2011/02
- 20 -
Hi-Z
[AK5602A]
5.2.3 Mapping of controlling registers
[Readable and writable registers]
Initial value of controlling registers below is set to comply with Japanese standard.
In a case that the LSI is used to comply with IEC standard, initial value of some registers
should be modified. Please refer to the chapter 5.5, which describes the way of the system
calibration in IEC mode.
Address
Initial
R/W
Symbol
Name
A6-0
value
00h
9999h
R/W
RPR
RP rated active power threshold value
01h
00C9h
02h
9999h
R/W
TPR
TP rated active power threshold value
03h
00C9h
04h
9999h
R/W
RQR
RQ rated reactive power threshold value
05h
00C9h
06h
9999h
R/W
TQR
TQ rated reactive power threshold value
07h
00C9h
RPST/TPST/
RP/TP/RQ/TQ starting power threshold
08h
R/W
1111h
RQST/TQST
value for Japanese specification
09h
R/W
B2B
B2 balance value
0000h
0Ah
R/W
B3B
B3 balance value
0000h
0Bh
R/W
RPL/RQL
RP/RQ light load value
0000h
0Ch
R/W
TPL/TQL
TP/TQ light load value
0000h
0Dh
R/W
PFCN1
N1 power factor adjustment value
0000h
0Eh
R/W
PFCN2
N2 power factor adjustment value
0000h
0Fh
R/W
PFCN3
N3 power factor adjustment value
0000h
10h
R/W
PGAV1/PGAI1
PGA1 gain
0401h
11h
R/W
PGAV2/PGAI2
PGA2 gain
0401h
12h
R/W
PGAV3/PGAI3
PGA3 gain
0401h
13h
R/W VTHR1/VTHF1
F1 threshold value
2B2Dh
14h
R/W VTHR2/VTHF2
F2 threshold value
2B2Dh
15h
R/W VTHR3/VTHF3
F3 threshold value
2B2Dh
16h
R/W
FULV1/FULI1
Full scale adjustment 1
0000h
17h
R/W
FULV2/FULI2
Full scale adjustment 2
0000h
18h
R/W
FULV3/FULI3
Full scale adjustment 3
0000h
19h
R/W
0000h
VOFF
Voltage offset
1Ah
R/W
0000h
1Bh
R/W
0000h
IOFF
Current offset
1Ch
R/W
0000h
1Dh
R/W
PWADD
Power addition able or disable control
0000h
Creeping current threshold value for
1Eh
R/W
SENDOU
003Ah
IEC specification
Pulse width of output powers for IEC
1Fh
R/W
PULSW
0000h
specification
R/W
FUNC_SET
Function setting
0000h
20h
R/W
CONTL_SET
Control setting
0000h
21h
MS1285-E-00
2011/02
- 21 -
[AK5602A]
[Read only registers]
Address
A6-0
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2F
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
3Dh
3Eh
3Fh
40h
41h
42h
43h
44h
45h
46h
47h
48h
49h
R/W
Symbol
Name
R
R
R
R
R
R
R
R
R
R
R
R
R
V1AD
V2AD
V3AD
I1HAD
I2HAD
I3HAD
ILAD
V1RMS
V2RMS
V3RMS
I1RMS
I2RMS
I3RMS
V(voltage)1 instantaneous value
V(voltage)2 instantaneous value
V(voltage)3 instantaneous value
I(current)1 instantaneous value (upper bits)
I(current)2 instantaneous value (upper bits)
I(current)3 instantaneous value (upper bits)
I1/I2/I3 instantaneous value (lower bits)
V(voltage)1 RMS value
V(voltage)2 RMS value
V(voltage)3 RMS value
I(current)1 RMS value
I(current)2 RMS value
I(current)3 RMS value
Reserved
R
P1
P1 instantaneous active power
R
P2
P2 instantaneous active power
R
P3
P3 instantaneous active power
R
PSUM
Total instantaneous active power
R
Q1
Q1 instantaneous reactive power
R
Q2
Q2 instantaneous reactive power
R
Q3
Q3 instantaneous reactive power
R
QSUM
Total instantaneous reactive power
R
PTOTR
R
PTOTT
R
QTOTR
R
QTOTT
R
R
PPULSE
QPULSE
All total instantaneous active power
(Receiving)
All total instantaneous active power
(Transmitting)
All total instantaneous reactive power
(Receiving)
All total instantaneous reactive power
(Transmitting)
Active energy pulse
Reactive energy pulse
MS1285-E-00
Initial
value
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
2011/02
- 22 -
[AK5602A]
Address
A6-0
4Ah
4Bh
4Ch
4Dh
4Eh
4Fh
50h
51h
52h
53h
54h
55h
56h
57h
58h
59h
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R/W
R/W
Symbol
Name
S1
S2
S3
S1 apparent power
S2 apparent power
S3 apparent power
SSUM
Total apparent power
RXPO
TXPO
RXQO
TXQO
PF1
PF2
PF3
TEMP
TEMP_COEF
TOFFSET
Reserved
RPO active power accumulated value
TPO active power accumulated value
RQO reactive power accumulated value
TQO reactive power accumulated value
φ1 Power factor
φ2 Power factor
φ3 Power factor
Temperature
Temp. adjustment coefficient (Gain)
Temp. adjustment coefficient (Offset)
MS1285-E-00
Initial
value
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0080h
1C2Ah
0000h
2011/02
- 23 -
[AK5602A]
Minute register mapping
Address
A6-0
bit15
bit7
bit14
bit6
bit13
bit5
00h
(R/W)
01h
(R/W)
-
-
-
Data
bit12
bit11
bit4
bit3
RPR15-8
RPR7-0
-
-
-
-
-
-
RPR25-24
-
-
-
-
-
TPR25-24
-
-
RQR25-24
TQR15-8
TQR7-0
-
-
-
-
-
TQST3-0
TPST3-0
09h
(R/W)
-
0Ah
(R/W)
-
-
TQR25-24
RQST3-0
RPST3-0
-
-
-
B2B11-8
-
00C9h
1111h
0000h
B2B7-0
-
00C9h
9999h
TQR23-16
08h
(R/W)
00C9h
9999h
RQR23-16
-
00C9h
9999h
RQR15-8
RQR7-0
-
Initial
value
9999h
TPR23-16
06h
(R/W)
07h
(R/W)
bit8
bit0
TPR15-8
TPR7-0
04h
(R/W)
05h
(R/W)
bit9
bit1
RPR23-16
02h
(R/W)
03h
(R/W)
-
bit10
bit2
B3B11-8
0000h
B3B7-0
0Bh
(R/W)
RQL7-0
RPL7-0
0000h
0Ch
(R/W)
TQL7-0
TPL7-0
0000h
0Dh
(R/W)
-
0Eh
(R/W)
-
0Fh
(R/W)
-
-
-
-
-
-
PFCN1_9-8
-
-
PFCN2_9-8
-
-
PFCN3_9-8
PFCN1_7-0
-
-
PFCN2_7-0
-
-
PFCN3_7-0
MS1285-E-00
2011/02
- 24 -
0000h
0000h
0000h
[AK5602A]
Address
A6-0
Data
bit15
bit7
bit14
bit6
10h
(R/W)
-
-
-
-
11h
(R/W)
-
-
-
-
12h
(R/W)
-
-
-
-
bit13
bit5
bit12
bit4
-
-
bit9
bit1
bit8
bit0
-
-
-
-
0401h
PGAV2_2-0
PGAI3_5-0
-
-
-
0401h
PGAV3_2-0
VTHF1_7-0
2B2Dh
VTHR1_7-0
VTHF2_7-0
2B2Dh
VTHR2_7-0
VTHF3_7-0
15h
(R/W)
2B2Dh
VTHR3_7-0
FULI1_7-0
16h
(R/W)
0000h
FULV1_7-0
FULI2_7-0
17h
(R/W)
0000h
FULV2_7-0
FULI3_7-0
18h
(R/W)
0000h
FULV3_7-0
VOFF15-8
19h
(R/W)
0000h
VOFF7-0
-
-
-
-
-
-
-
-
VOFF23-16
IOFF15-8
1Bh
(R/W)
-
-
-
1Dh
(R/W)
-
QSSEL
S3DIS
-
-
-
-
-
-
-
-
-
S2DIS
S1DIS
Q3DIS
Q2DIS
Q1DIS
-
-
-
P3DIS
P2DIS
P1DIS
-
-
-
-
-
SENDOU8
IOFF23-16
1Fh
(R/W)
SENDOU7-0
RDIV1-0
QODIS
PODIS
PULSW11-8
2011/02
- 25 -
0000h
0000h
003Ah
0000h
PULSW7-0
MS1285-E-00
0000h
0000h
IOFF7-0
1Ch
(R/W)
Initial
value
0401h
PGAV1_2-0
PGAI2_5-0
14h
(R/W)
1Eh
(R/W)
bit10
bit2
PGAI1_5-0
13h
(R/W)
1A
(R/W)
bit11
bit3
[AK5602A]
Address
A6-0
20h
(R/W)
21h
(R/W)
Data
bit15
bit7
bit14
bit6
bit13
bit5
bit12
bit4
bit11
bit3
bit10
bit2
bit9
bit1
bit8
bit0
-
-
ZSI3
ZSI2
ZSI1
ZSV3
ZSV2
ZSV1
CAL
PFSEL
SSEL
IEC
HPF
TEMP
FULLI
FULLV
INVALID
-
-
-
-
-
-
-
-
-
RMSRD1-0
ADRD1-0
22h
(R)
V1AD15-8
23h
(R)
V2AD15-8
24h
(R)
V3AD15-8
25h
(R)
I1AD17-10
26h
(R)
I2AD17-10
27h
(R)
I3AD17-10
28h
(R)
RDY1-0
0000h
V3AD7-0
0000h
I1AD9-2
0000h
I2AD9-2
0000h
I3AD9-2
-
-
29h
(R)
2Ah
(R)
2Bh
(R)
-
-
-
I3AD1-0
-
-
I2AD1-0
I1AD1-0
V1RMS15-8
V1RMS7-2
-
-
-
-
-
-
V2RMS15-8
V2RMS7-2
V3RMS15-8
V3RMS7-2
2Ch
(R)
I1RMS15-8
2Dh
(R)
I2RMS15-8
2Eh
(R)
I3RMS15-8
2Fh
(R)
Reserved
0000h
0000h
0000h
0000h
I2RMS7-0
0000h
I3RMS7-0
0000h
Reserved
2011/02
- 26 -
0000h
0000h
I1RMS7-0
MS1285-E-00
0000h
0000h
V2AD7-0
-
0000h
0000h
V1AD7-0
-
Initial
value
[AK5602A]
Address
A6-0
Data
bit15
bit7
bit14
bit6
bit13
bit5
bit12
bit4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P1_19-16
-
-
-
P2_19-16
-
-
-
-
P3_19-16
-
-
-
-
-
-
-
-
-
-
-
-
-
Q1_19-16
Q2_15-8
-
-
-
-
-
-
-
-
-
-
-
Q2_19-16
Q3_15-8
-
-
-
-
-
-
-
-
-
-
-
Q3_19-16
QSUM15-8
-
-
-
-
-
-
-
-
-
QSUM21-16
MS1285-E-00
2011/02
- 27 -
0000h
0000h
QSUM7-0
-
0000h
0000h
Q3_7-0
-
0000h
0000h
Q2_7-0
-
0000h
0000h
Q1_7-0
-
0000h
0000h
Q1_15-8
-
0000h
0000h
PSUM21-16
-
0000h
0000h
-
-
3Eh
(R)
3Fh
(R)
-
PSUM7-0
3Ch
(R)
3Dh
(R)
-
PSUM15-8
3Ah
(R)
3Bh
(R)
-
P3_7-0
38h
(R)
39h
(R)
-
P3_15-8
-
Initial
value
0000h
P2_7-0
36h
(R)
37h
(R)
bit8
bit0
P2_15-8
34h
(R)
35h
(R)
bit9
bit1
P1_7-0
32h
(R)
33h
(R)
bit10
bit2
P1_15-8
30h
(R)
31h
(R)
bit11
bit3
0000h
[AK5602A]
Address
A6-0
Data
bit15
bit7
bit14
bit6
bit13
bit5
bit12
bit4
-
-
-
-
-
-
-
PTOTT15-8
-
-
-
-
-
-
-
PTOTT23-16
QTOTR15-8
-
-
-
-
-
-
-
QTOTR23-16
QTOTT15-8
-
48h
(R)
PD
49h
(R)
QD
-
-
-
-
-
-
-
QTOTT23-16
-
PPULSE13-8
QPULSE13-8
0000h
QPULSE7-0
4Ah
(R)
S1_15-8
4Bh
(R)
S2_15-8
4Ch
(R)
S3_15-8
4Dh
(R)
SSUM15-8
0000h
S1_7-0
0000h
S2_7-0
0000h
S3_7-0
0000h
SSUM7-0
-
-
-
-
-
-
-
-
-
-
-
-
4Fh
(R)
-
SSUM17-16
Reserved
2011/02
- 28 -
0000h
0000h
Reserved
MS1285-E-00
0000h
0000h
PPULSE7-0
-
0000h
0000h
QTOTT7-0
47h
(R)
0000h
0000h
QTOTR7-0
-
0000h
0000h
PTOTT7-0
-
Initial
value
0000h
-
46h
(R)
4Eh
(R)
bit8
bit0
PTOTR23-16
44h
(R)
45h
(R)
bit9
bit1
PTOTR7-0
42h
(R)
43h
(R)
bit10
bit2
PTOTR15-8
40h
(R)
41h
(R)
bit11
bit3
[AK5602A]
Address
A6-0
Data
bit15
bit7
bit14
bit6
bit13
bit5
bit12
bit4
bit11
bit3
50h
(R)
RXPO15-8
51h
(R)
TXPO15-8
52h
(R)
RXQO15-8
53h
(R)
TXQO15-8
bit10
bit2
bit9
bit1
bit8
bit0
0000h
RXPO7-0
0000h
TXPO7-0
0000h
RXQO7-0
0000h
TXQO7-0
54h
(R)
-
55h
(R)
-
56h
(R)
-
57h
(R)
-
PF1_14-8
58h
(R/W)
-
59h
(R/W)
-
-
-
-
-
-
0000h
PF1_7-0
PF2_14-8
0000h
PF2_7-0
PF3_14-8
0000h
PF3_7-0
-
-
-
-
-
-
-
TEMP7-0
-
-
TCOEF12-8
-
-
-
-
TOFFSET4-0
MS1285-E-00
2011/02
- 29 -
0080h
1C2Ah
TCOEF7-0
-
Initial
value
0000h
[AK5602A]
5.2.4 Controlling registers
Rated power threshold value setting (ADD. 00h, 01h, 02h, 03h, 04h, 05h, 06h, 07h)
Address
A6-0
bit15
bit7
00h
(R/W)
01h
(R/W)
-
02h
(R/W)
03h
(R/W)
-
-
06h
(R/W)
07h
(R/W)
bit13
bit5
TPR15-8 (Same as below)
TPR7-0 (Rated active power threshold value at transmitting mode)
TPR25-24
(Same as below)
TPR23-16 (Rated active power threshold value at transmitting mode)
RQR15-8 (Same as below)
RQR7-0 (Rated reactive power threshold value at receiving mode)
04h
(R/W)
05h
(R/W)
Data
bit12
bit11
bit10
bit9
bit8
bit4
bit3
bit2
bit1
bit0
RPR15-8 (Same as below)
RPR7-0 (Rated active power threshold value at receiving mode)
RPR25-24
(Same as below)
RPR23-16 (Rated active power threshold value at receiving mode)
bit14
bit6
-
-
-
-
9999h
00C9h
9999h
00C9h
9999h
RQR25-24
(Same as below)
RQR23-16 (Rated reactive power threshold value at receiving mode)
-
Initial
value
-
TQR15-8 (Same as below)
TQR7-0 (Rated reactive power threshold value at transmitting mode)
TQR25-24
(Same as below)
TQR23-16 (Rated reactive power threshold value at transmitting mode)
00C9h
9999h
00C9h
[RP Rated active power threshold value] This is the threshold value for producing the pulse
of active power at receiving mode.
The value should be 0000000h ≤ WRPR ≤ 3FFFFFFh
[TP Rated active power threshold value] This is the threshold value for producing the pulse
of active power at transmitting mode.
0000000h ≤ WTPR ≤ 3FFFFFFh
[RQ Rated reactive power threshold value] This is the threshold value for producing the
pulse of reactive power at receiving mode.
0000000h ≤ WRQR ≤ 3FFFFFFh
[TQ Rated reactive power threshold value] This is the threshold value for producing the
pulse of reactive power at transmitting mode.
0000000h ≤ WTQR ≤ 3FFFFFFh
The initial value of RP, TP, RQ and TQ is set to meet the Japanese specification. 1000 pulses
are output for one second when the half of full-scale signal is applied at each voltage and
current input of three phases. It is needed to change these values into 3225h to meet IEC
specification.
Starting power threshold value setting ( ADD. 08h)
This value should be modified to 0FFFh to meet IEC standard.
Address
A6 -0
08h
(R/W)
Data
bit15
bit14
bit13
bit12
bit7
bit6
bit5
bit4
TQST3-0 (TQ starting power threshold value)
TPST3-0 (TP starting power threshold value)
MS1285-E-00
bit11
bit10
bit9
bit8
bit3
bit2
bit1
bit0
RQST3-0 (RQ starting power threshold value)
RPST3-0 (RP starting power threshold value)
2011/02
- 30 -
Initial
value
1111h
[AK5602A]
RP starting power threshold value setting
Setting value Starting power
Function
threshold value
bit3 bit2 bit1 bit0
(Sec)
When “L” level pulse width at RPO pin is narrower than
0
0
0
0
0.70
the starting power threshold value, the level at RPST
0
0
0
1
0.75
pin becomes “H” level at the next rising edge of RPO
0
0
1
0
0.80
pulse.
0
0
1
1
0.85
When “L” level pulse width at RPO pin is wider than the
0
1
0
0
0.90
starting power threshold value, the level at RPST pin
0
1
0
1
0.95
becomes “L” level after the starting power threshold
0
1
1
0
1.00
value.
0
1
1
1
1.05
Regardless of the value at bit2 to bit0, ‘0’ second is
selected as the starting power threshold value. The level
1 X X X
0
of RPST becomes “H” when the value of XP + RPL is
positive. The level of RPST becomes “L” when the value
of XP + RPL is negative.
TP starting power threshold value setting
Setting value Starting power
Function
threshold value
bit7 bit6 bit5 bit4
(Sec)
When “L” level pulse width at TPO pin is narrower than
0
0
0
0
0.70
the starting power threshold value, the level at TPST
0
0
0
1
0.75
pin becomes “H” level at the next rising edge of TPO
0
0
1
0
0.80
pulse.
0
0
1
1
0.85
When “L” level pulse width at TPO pin is wider than the
0
1
0
0
0.90
starting power threshold value, the level at TPST pin
0
1
0
1
0.95
becomes “L” level after the starting power threshold
0
1
1
0
1.00
value.
0
1
1
1
1.05
Regardless of the value at bit6 to bit4, ‘0’ second is
selected as the starting power threshold value. The level
1 X X X
0
of TPST becomes “H” when the value of -XP + TPL is
positive. The level of TPST becomes “L” when the value
of -XP + TPL is negative.
RQ starting power threshold value setting
Setting value
Starting power
Function
threshold value
bit11 bit10 bit9 bit8
(Sec)
0
0
0
0
0.70
When “L” level pulse width at RQO pin is narrower
0
0
0
1
0.75
than the starting power threshold value, the level at
0
0
1
0
0.80
RQST pin becomes “H” level at the next rising edge of
0
0
1
1
0.85
RQO pulse.
When “L” level pulse width at RQO pin is wider than
0
1
0
0
0.90
the starting power threshold value, the level at RQST
0
1
0
1
0.95
pin becomes “L” level after the starting power
0
1
1
0
1.00
threshold value.
0
1
1
1
1.05
Regardless of the value at bit10 to bit8, ‘0’ second is
selected as the starting power threshold value. The
1
X
X X
0
level of RQST becomes “H” when the value of XQ +
RQL is positive. The level of RQST becomes “L” when
the value of XQ + RQL is negative.
MS1285-E-00
2011/02
- 31 -
[AK5602A]
TQ starting power threshold value setting
Setting value
Starting power
threshold value
bit15 bit14 bit13 bit12
(Sec)
0
0
0
0
0.70
0
0
0
1
0.75
0
0
1
0
0.80
0
0
1
1
0.85
0
1
0
0
0.90
0
1
0
1
0.95
0
1
1
0
1.00
0
1
1
X
1
X
1
1.05
X
Function
When “L” level pulse width at TQO pin is narrower
than the starting power threshold value, the level at
TQST pin becomes “H” level at the next rising edge
of TQO pulse.
When “L” level pulse width at TQO pin is wider than
the starting power threshold value, the level at
TQST pin becomes “L” level after the starting power
threshold value.
Regardless of the value at bit14 to bit12, ‘0’ second is
selected as the starting power threshold value. The
level of TQST becomes “H” when the value of -XQ +
TQL is positive. The level of TQST becomes “L” when
the value of -XQ + TQL is negative.
0
Initial value of starting power threshold value of TP, RP, TQ and RQ is set at 0.75 second.
1.0 s
0.5 s
0.5 s
0.5 s
1.0 s
1.0 s
0.5s
RPO(TPO,RQO
,TQO) output
When starting power threshold value is set to “0” second,
RPO(TPO,RQO,TQO)
RPST,TPST,RQST,TQST
The polarity of
XP+RPL (-XP+TPL,XQ+RQL,-XQ+TQL)
When starting power threshold value is set “0.75” second in this case,
RPO (TPO,RQO,TQO)
0.75 s
RPST (TPST,RQST,TQST)
Fig.6 Output waveform of RPST(TPST,RQST,TQST)
MS1285-E-00
2011/02
- 32 -
[AK5602A]
Balance value setting (ADD. 09h, 0Ah)
Address
Data
A6-0
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
09h (R/W)
B2 balance value
0Ah (R/W)
B3 balance value
Initial
value
X000h
X000h
B2 balance value: the value to adjust the gain of V2 against V1
B3 balance value: the value to adjust the gain of V3 against V1
The gain can be adjusted from 0 times to (2-1/2048) times.
When the value is ‘000h’, the gain is ‘1’.
The value should be 000h ≤ B2 balance value, B3 balance value ≤ FFFh
Setting value
Gain
7FFh
1+ 1/2 + 1/4 + 1/8 + … + 1/2048
∼
400h
1+ 1/2 (1.5)
∼
200h
1+ 1/4 (1.25)
1FFh
1+ 1/8 + 1/16 + … + 1/2048
∼
100h
1+ 1/8 (1.125)
0FFh
1+ 1/16 + 1/32 + … + 1/2048
∼
001h
1+ 1/2048
000h
1
FFFh
1- 1/2048
FFEh
1 – 1/1024
∼
F01h
1 - 1/16 - 1/32 - … - 1/2048
F00h
1 - 1/8 (0.875)
∼
E00h
1 - 1/4 (0.75)
∼
C00h
1 - 1/2 (0.5)
∼
800h
1 - 1 (0)
Do not set the value to 800h. This value makes the scale ‘0’, which is invalid.
Initial value of B2 balance and B3 balance is set at ×1.
MS1285-E-00
2011/02
- 33 -
[AK5602A]
Light load value setting (ADD. 0Bh, 0Ch)
Address
Data
A6-0
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
0Bh(R/W)
RQ light load value
RP light load value
0Ch(R/W)
TQ light load value
TP light load value
Initial
value
0000h
0000h
RP light load value, RQ light load value: the value is used to adjust the offset at RP side or
RQ side in light load mode.
Value
Offset
7Fh
+31.75
7Eh
+31.5
:
∼
01h
+0.25
00h
0
FFh
-0.25
:
∼
81h
-31.75
80h
-32
TP light load value, TQ light load value: the value is used to adjust the offset at TP side or
TQ side in light load mode.
Value
Offset
7Fh
+31.75
7Eh
+31.5
:
∼
01h
+0.25
00h
0
FFh
-0.25
:
∼
81h
-31.75
80h
-32
The initial value of each light load is set at ‘0’.
MS1285-E-00
2011/02
- 34 -
[AK5602A]
Power factor adjustment value setting (ADD. 0Dh, 0Eh, 0Fh)
Address
A6-0
bit15
bit7
-
bit14
bit6
-
bit13
bit5
-
0Eh
(R/W)
-
-
-
0Fh
(R/W)
-
-
-
0Dh
(R/W)
Data
bit12
bit11
bit4
bit3
PFCN1_7-0 (N1_Adj.)
bit10
bit2
-
bit9
bit8
bit1
bit0
PFCN1_9-8 (N1_Adj.)
PFCN2_7-0 (N2_Adj)
-
PFCN2_9-8 (N2_Adj)
PFCN3_7-0 (N3_Adj)
-
PFCN3_9-8 (N3_Adj)
N1_Adjust: This value is used to delay the starting point of AD conversion at voltage side
against current side in the AD conversion of [ (I1P) – (I1N), (V1P) – (VIN) ].
Value
Delay (XCLK=12.9024MHz)
1EFh
7920 XCLK (613.84us)
1EEh
7904XCLK (612.60us)
∼
01h
16 XCLK (1.24us)
00h
0 XCLK (0us)
3FFh
-16XCLK (-1.24us)
∼
212h
-7904XCLK (-612.60us)
211h
-7920XCLK (-613.84us)
N2_Adjust: This value is used to delay the starting point of AD conversion at voltage side
against current side in the AD conversion of [ (I2P) – (I2N), (V2P) – (VIN) ].
Value
Delay (XCLK=12.9024MHz)
1EFh
7920 XCLK (613.84us)
1EEh
7904 XCLK (612.60us)
∼
01h
16 XCLK (1.24us)
00h
0 XCLK (0us)
3FFh
-16XCLK (-1.24us)
∼
212h
-7904XCLK (-612.60us)
211h
-7920XCLK (-613.84us)
N3_Adjust: This value is used to delay the starting point of AD conversion at voltage side
against current side in the AD conversion of [ (I3P) – (I3N), (V3P) – (VIN) ].
Value
Delay (XCLK=12.9024MHz)
1EFh
7920 XCLK (613.84us)
1EEh
7904XCLK (612.60us)
∼
01h
16 XCLK (1.24us)
00h
0 XCLK (0us)
3FFh
-16XCLK (-1.24us)
∼
212h
-7904XCLK (-612.60us)
211h
-7920XCLk (-613.84us)
In a case that the value which is more than ‘1EFh’ is set at the above register, the delay will be
7920XCLK . And if the value is less than ‘211h’, the delay will be -7920XCLK.
Initial value of each power factor adjustment value is set ‘0’, which means no adjustment.
MS1285-E-00
2011/02
- 35 -
Initial
value
0000h
0000h
0000h
[AK5602A]
PGA setting(ADD. 10h, 11h, 12h)
Address
A6-0
Data
bit15
bit7
bit14
bit6
10h
(R/W)
-
-
-
-
11h
(R/W)
-
-
-
-
12h
(R/W)
-
-
-
-
bit13
bit5
bit12
bit4
bit11
bit3
bit10
bit2
bit9
bit1
bit8
bit0
PGAI1_5-0 (CH1 current side PGA)
-
-
-
PGAV1_2-0 (CH1 voltage side PGA)
PGAI2_5-0 (CH2 current side PGA)
-
-
-
PGAV2_2-0 (CH2 voltage side PGA)
PGAI3_5-0 (CH3 current side PGA)
-
-
-
PGAV3_2-0 (CH3 voltage side PGA)
PGAV1 (bit2 – 0): to select CH1voltage side PGA
Value
Analog input
Gain
Full scale voltage
bit2
bit1 bit0
0
0
0
x1
±1.0V
0
0
1
x1
±1.0V
0
1
0
x2
±0.5V
0
1
1
x3
±0.333V
1
0
0
x4
±0.25V
PGAI1 (bit13 – 8): to select CH1 current side PGA
Value
bit13 bit12 bit11 bit10 bit9 bit8
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
1
0
1
0
0
1
0
0
0
0
0
1
1
0
0
0
1
0
0
1
0
0
1
1
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
MS1285-E-00
Gain
x1
x1
x2
x3
x4
x5
x8
x12
x18
x24
x31
x32
Analog input
Full scale voltage
±1.0V
±1.0V
±0.5V
±0.333V
±0.25V
±0.20V
±0.125V
±0.0833V
±0.0556V
±0.0417V
±0.0323V
±0.03125V
2011/02
- 36 -
Initial
value
0401h
0401h
0401h
[AK5602A]
PGAV2 (bit2-0): to select CH2 voltage side PGA
Value
Analog input
Gain
Full scale voltage
bit2
bit1 bit0
0
0
0
x1
±1.0V
0
0
1
x1
±1.0V
0
1
0
x2
±0.5V
0
1
1
x3
±0.333V
1
0
0
x4
±0.25V
PGAI2 (bit13-8): to select CH2 current side PGA
Value
Gain
bit13 bit12 bit11 bit10 bit9 bit8
0
0
0
0
0
0
x1
0
0
0
0
0
1
x1
0
0
0
0
1
0
x2
0
0
0
0
1
1
x3
0
0
0
1
0
0
x4
0
0
0
1
0
1
x5
0
0
1
0
0
0
x8
0
0
1
1
0
0
x12
0
1
0
0
1
0
x18
0
1
1
0
0
0
x24
0
1
1
1
1
1
x31
1
0
0
0
0
0
x32
Analog input
Full scale input
±1.0V
±1.0V
±0.5V
±0.333V
±0.25V
±0.20V
:
±0.125V
:
±0.0833V
:
±0.0556V
:
±0.0417V
:
±0.0323V
±0.03125V
PGAV3 (bit2-0): to select CH3 voltage side PGA
Value
Analog input
Gain
Full scale input
bit2
bit1 bit0
0
0
0
x1
±1.0V
0
0
1
x1
±1.0V
0
1
0
x2
±0.5V
0
1
1
x3
±0.333V
1
0
0
x4
±0.25V
MS1285-E-00
2011/02
- 37 -
[AK5602A]
PGAI3 (bit13-8): to select CH3 current side PGA
Value
Analog input
Gain
Full scale voltage
bit13 bit12 bit11 bit10 bit9 bit8
0
0
0
0
0
0
x1
±1.0V
0
0
0
0
0
1
x1
±1.0V
0
0
0
0
1
0
x2
±0.5V
0
0
0
0
1
1
x3
±0.333V
0
0
0
1
0
0
x4
±0.25V
0
0
0
1
0
1
x5
±0.20V
0
0
1
0
0
0
x8
±0.125V
0
0
1
1
0
0
x12
±0.0833V
0
1
0
0
1
0
x18
±0.0556V
0
1
1
0
0
0
x24
±0.0417V
0
1
1
1
1
1
x31
±0.0323V
1
0
0
0
0
0
x32
±0.03125V
Initial value of voltage side PGA on each phase is set x1 and initial value of current side PGA
on each phase is set x4.
Threshold value of frequency pulse output setting (ADD. 13h, 14h, 15h)
Address
A6-0
Data
bit15
bit7
bit14
bit6
bit13
bit5
bit12
bit4
bit11
bit3
bit10
bit2
bit9
bit1
bit8
bit0
VTHF1_7-0 (F1 falling threshold)
13h
(R/W)
2B2Dh
VTHR1_7-0 (F1 rising threshold)
VTHF2_7-0 (F2 falling threshold)
14h
(R/W)
2B2Dh
VTHR2_7-0 (F2 rising threshold)
VTHF3_7-0 (F3 falling threshold)
15h
(R/W)
2B2Dh
VTHR3_7-0 (F3 rising threshold)
F1 rising threshold value: This is the rising threshold value of F1 output to determine the
frequency based on AD conversion value of V1(voltage input1). F1pin outputs “H” level over
the threshold value.
The value should be 00h ≤ VTH1R ≤ 7Fh.
Initial value is set about 70% of voltage input1 at initial value of rated active power register.
Value
7Fh
Threshold
7F00h
7Eh
02h
01h
00h
7E00h
0200h
0100h
0000h
MS1285-E-00
2011/02
- 38 -
Initial
Value
[AK5602A]
F1 falling threshold value: This is the falling threshold value of F1 output to determine the
frequency based on AD conversion value of V1 (voltage input1). F1pin outputs ‘L’ level under
the threshold value.
The value should be 00h ≤ VTH1F ≤ 7Fh.
Initial value is set about 68% of voltage input at initial value of rated active power register in
Japanese specification.
Value
Threshold
7Fh
7F00h
7Eh
7E00h
02h
0200h
01h
0100h
00h
0000h
The rising threshold value and falling threshold value of F2 and F3 are set in the same
manner of F1 and have the same initial values of F1. In addition, it is ignored that even if ‘1’ is
written into the ‘bit7’ of the threshold register.
Full scale adjustment value setting (ADD. 16h, 17h, 18h)
Address
A6-0
Data
bit15
bit7
16h
(R/W)
17h
(R/W)
18h
(R/W)
bit14
bit6
bit13
bit5
bit12
bit4
bit11
bit3
bit10
bit2
bit9
bit1
bit8
bit0
FULI1_7-0 (Current side CH1 full scale adjustment)
0000h
FULV1_7-0 (Voltage side CH1 full scale adjustment)
FULI2_7-0 (Current side CH2 full scale adjustment)
0000h
FULV2_7-0 (Voltage side CH2 full scale adjustment)
FULI3_7-0 (Current side CH3 full scale adjustment)
0000h
FULV3_7-0 (Voltage side CH3 full scale adjustment)
This register is to adjust the variations produced by PGA and / or VREF from ideal value so
that the result of ADC has an ideal ADC code when a half of full-scale DC voltage, 0.5 V is
applied to each voltage and current channel. When using this function, the gain of all voltage
channels should be the same value as well as the gain of all current channels. The gain
between current and voltage can be changed. It should be very careful for using this function
because after the adjustment, every calculation including an instantaneous value, RMS value
and active & reactive power is affected.
The adjustment of gain on voltage side is performed by setting ‘1’ to bit0, FULLV of Function
setting register,ADD.‘20h’.
And the adjustment of gain on current side is performed by setting ‘1’ to ‘bit1’, FULLI of
Function setting register,ADD.’20h’.
After the execution of this command, the adjustment value can be read from ADD. ‘16h’, ‘17h’,
‘18h’ respectively. It is also possible to set the values as well by writing the values into these
registers directly.
Refer to the table below to confirm the relationship between setting value and adjustment
value.
MS1285-E-00
2011/02
- 39 -
Initial
Value
[AK5602A]
Value
7Fh
7Eh
∼
01h
00h
FFh
FEh
∼
81h
80h
Gain
(1024+127)/1024 = 1.124023
(1024+126)/1024 = 1.123047
∼
(1024+1)/1024 = 1.0009766
(256+0)/ 256= 1.00
(1024-1)/1024 = 0.999023
(1024-2)/1024 = 0.998047
∼
(1024-127)/1024 = 0.875976
(1024-128)/1024 = 0.875
V(voltage) offset adjustment setting (ADD. 19h, 1Ah)
Address
A6-0
Data
bit15
bit7
bit14
bit6
bit13
bit5
bit11
bit3
bit10
bit2
bit9
bit1
bit8
bit0
VOFF15-8 (V offset middle)
19h
(R/W)
1A
(R/W)
bit12
bit4
0000h
VOFF7-0 (V offset lower)
-
-
-
-
-
Initial
Value
-
-
-
VOFF23-16 (V offset higher)
0000h
This register is for setting offset value of ADC at voltage side. The calibration is executed by
setting ‘1’ to bit7, CAL bit of Function setting register,ADD.‘20h’. It is possible to read the V
offset value after the calibration.
I(current) offset adjustment setting (ADD. 1Bh, 1Ch)
Address
A6-0
Data
bit15
bit7
bit14
bit6
bit13
bit5
bit11
bit3
bit10
bit2
bit9
bit1
bit8
bit0
IOFF15-8 (I offset middle)
1Bh
(R/W)
1Ch
(R/W)
bit12
bit4
0000h
IOFF7-0 (I offset lower)
-
-
-
-
-
-
-
-
IOFF23-16 (I offset higher)
This register is for setting offset value of ADC at current side. The calibration is executed by
setting ‘1’ to bit7, CAL bit of Function setting register, ADD. ‘20h’. It is possible to read the I
offset value after the calibration.
MS1285-E-00
2011/02
- 40 -
Initial
Value
0000h
[AK5602A]
Power addition “disable” setting (ADD. 1Dh)
Address
A6-0
1Dh
(R/W)
Data
bit15
bit7
bit14
bit6
bit13
bit5
bit12
bit4
bit11
bit3
bit10
bit2
bit9
bit1
bit8
bit0
-
QSSEL
S3DIS
S2DIS
S1DIS
Q3DIS
Q2DIS
Q1DIS
-
-
-
-
-
P3DIS
P2DIS
P1DIS
Initial
Value
0000h
This register enables the addition control of active power (P1/P2/P3), reactive power
(Q1/Q2/Q3) and apparent power (S1/S2/S3) when power summation is executed. When ‘1’ is set
to the corresponding bit, the addition of the corresponding channel is canceled.
Initial setting is that power at each channel is summed in active power, reactive power and
apparent power. And QSSEL, bit14 is to select either reactive power pulse, ‘0’ or apparent
power pulse,’1’. The initial setting of QSSEL is reactive power pulse.
IEC creeping value setting (ADD. 1Eh)
Address
A6-0
1Eh
(R/W)
Data
bit15
bit7
bit14
bit6
bit13
bit5
bit12
bit4
bit11
bit3
bit10
bit2
bit9
bit1
bit8
bit0
-
-
-
-
-
-
-
SENDOU8
SENDOU7-0
Initial
Value
003Ah
This register enables to set ‘0’ at power input to pulse conversion block when the value of XP
=P1+P2+P3, XQ=Q1+Q2+Q3 or XS=S1+S2+S3 is less than the setting value.
Initial value is ‘3Ah’. This means that power input to pulse conversion block is set ‘0’ when the
summation of power each channel is less than 0.0075% of full-scale value.
Since this value is writable, it is possible to modify the value.
IEC power pulse width setting (ADD. 1Fh)
Address
A6-0
Data
bit15
bit7
1Fh
(R/W)
bit14
bit6
RDIV1-0
bit13
bit5
bit12
bit4
QODIS
PODIS
bit11
bit3
bit10
bit2
bit9
bit1
bit8
bit0
PULSW11-8 (IEC power pulse width higher)
PULSW7-0 (IEC power pulse width lower)
PULSW11-0 (bit11-0): This determines the IEC compliant power pulse width. The pulse width
will be 59.5us x (setting value +1). It is possible to set the pulse width between 59.5us and
243.7ms. The initial value of pulse width is 59.5us, which comply with the Japanese
standard.
PODIS (bit12): Active power pulse output disable. This stops the output of active power pulse
when ‘1’ is set. This does not stop the procedure of the conversion from power to pulse.
QODIS (bit13): Reactive power / apparent power pulse output disable. This stops the output of
reactive power / apparent power when ‘1’ is set. This does not stop the procedure of the
conversion from power to pulse. Initial value of PODIS and QODIS is set to ‘0’ respectively.
RDIV1-0 (bit15, bit14): This determines the frequency of accumulated addition. The frequency
becomes 16.8kHz if the value is set ‘00’,(initial value), becomes 8.4kHz if the value is set ‘01’
and becomes 4.2kHz if the value is set ‘10’.
MS1285-E-00
2011/02
- 41 -
Initial
Value
0000h
[AK5602A]
Function setting (ADD. 20h)
Address
A6-0
20h
(R/W)
Data
bit15
bit7
bit14
bit6
bit13
bit5
bit12
bit4
bit11
bit3
bit10
bit2
bit9
bit1
bit8
bit0
-
-
ZSI3
ZSI2
ZSI1
ZSV3
ZSV2
ZSV1
CAL
PFSEL
SSEL
IEC
HPF
TEMP
FULLI
FULLV
FULLV (bit0): To set ‘1’ in this bit when the full-scale adjustment for voltage side is to be
executed. When the adjustment is completed successfully, this bit becomes ‘0’ automatically.
The initial value of this bit is set ‘0’.
FULLI (bit1): To set ‘1’ in this bit when the full-scale adjustment for current side is to be
executed. When the adjustment is completed, this bit becomes ‘0’ automatically. The initial
value of this bit is set ‘0’.
TEMP (bit2): To set ‘1’ in this bit when the measurement of the temperature of the LSI is to be
executed. When the measurement is completed, this bit becomes ‘0’ automatically. The initial
value of this bit is set ‘0’.
HPF (bit3): To set ‘1’ in this bit when HPF is inserted into each voltage input and current
input. This setting is enabled for all channels simultaneously. The initial value of this bit is set
‘0’.
IEC (bit4): To set ‘1’ in this bit when IEC value ,ADD.’1Eh’ is used as the creeping judgment
value. The initial value of this bit is set ‘0’, which means that the creeping judgment value
complies with the Japanese standard.
SSEL (bit5): This bit is to select which type of apparent power is used. One is that the
apparent power is derived from the calculation of active power and reactive power. The other
is derived from the calculation of RMS voltage value and RMS current value. The initial value
is set ‘0’, which means that the apparent power is derived from the calculation of active power
and reactive power.
PFSEL (bit6): In the calculation of power factor, this bit is to select which type of apparent
power is used. The first one is to use the apparent power, which is derived from the calculation
of active power and reactive power. The other is to select the apparent power, which is derived
from RMS voltage and RMS current. The initial value is set ‘0’, which means that the apparent
power is derived from the calculation of active power and reactive power.
CAL (bit7): To set ‘1’ in this bit when the calibration of the ADC at voltage side and current
side is to be executed. When the calibration is completed successfully, this bit becomes ‘0’
automatically. The initial value of this bit is set ‘0’.
ZSV1-ZSV3 (bit8-bit10): When setting each voltage input from CH1 through CH3 in a short
mode, the corresponding bit should be set ‘1’. Initial value is set ‘0’, which means that the
corresponding bit is set NOT in a short mode.
ZSI1-ZSI3 (bit11-bit13): When setting each current input from CH1 through CH3 in a short
mode, the corresponding bit should be set ‘1’. Initial value is set ‘0’, which means that the
corresponding bit is set NOT in a short mode.
MS1285-E-00
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- 42 -
Initial
Value
0000h
[AK5602A]
Control setting (ADD. 21h)
Address
A6-0
21h
(R/W)
Data
bit15
bit7
bit14
bit6
bit13
bit5
bit12
bit4
bit11
bit3
bit10
bit2
Bit9
Bit1
bit8
bit0
INVALID
-
-
-
-
-
-
-
-
-
RDY1
RDY0
RMSRD1-0
ADRD1-0
Initial
Value
0000h
RDY1-0 (bit1, bit0): These bits assign RDY pin of the LSI to the one of the instantaneous value
registers, RMS value registers or other read-only registers. ‘00’ (initial value) is for RMS
registers,’01’ is for instantaneous registers, ’10’ or ’11’ is for other read-only
registers ,ADD.’22h’ to ‘57h’. There is no need RDY_control for readable and writable registers,
ADD. ‘00h’ to ‘21h’, ‘58h’ and ‘59h’. When the collision is occurred between reading and writing
without RDY control, INVALID (bit15) bit is set. This means that wrong data had been read.
Initial value of INVALID bit is ‘00’, which is RDY control for RMS.
ADRD1-0 (bit3, bit2) assign the renewal frequency of instantaneous values. ’00’ means that
the renewal frequency is 3.15kHz, ’01’ is 1.575kHz frequency, ’10’ is 0.7875kHz. Initial value is
3.15kHz.
RMSRD1-0 (bit5, bit4) assign the renewal frequency of RMS values. ’00’ means that the
renewal frequency is 3.15kHz, ’01’ is 1.575kHz frequency, ’10’ is 0.7875kHz. Initial value is
3.15kHz.
INVALID (bit15) is set when the collision is occurred between reading and writing controlling
registers. When INVALID bit is set, it is needed to read the corresponding data again. This
INVALID bit is cleared when this bit is read.
Instantaneous value (ADD. 22h, 23h, 24h, 25h, 26h, 27h, 28h)
Address
A6-0
Data
bit15
bit7
bit14
bit6
bit13
bit5
bit12
bit4
bit11
bit3
bit10
bit2
bit9
bit1
22h
(R)
V1AD15-8 (Higher bits of CH1 instantaneous voltage)
23h
(R)
V2AD15-8(Higher bits of CH2 instantaneous voltage)
24h
(R)
V3AD15-8(Higher bits of CH3 instantaneous voltage)
25h
(R)
I1AD17-10(Higher bits of CH1 instantaneous current)
26h
(R)
I2AD17-10(Higher bits of CH2 instantaneous current)
27h
(R)
I3AD17-10(Higher bits of CH3 instantaneous current)
28h
(R )
bit8
bit0
0000h
V1AD7-0 (Lower bits of CH1 instantaneous voltage)
0000h
V2AD7-0 (Lower bits of CH2 instantaneous voltage)
0000h
V3AD7-0 (Lower bits of CH3 instantaneous voltage)
0000h
I1AD9-2 (Lower bits of CH1 instantaneous current)
0000h
I2AD9-2 (Lower bits of CH2 instantaneous current)
0000h
I3AD9-2 (Lower bits of CH3 instantaneous current)
-
-
-
-
-
-
-
-
I3AD1-0(Lowest bits of I2AD1-0(Lowest bits of
CH3 instant. current)
CH2 instant. current)
-
-
I1AD1-0(Lowest bits of 0000h
CH1 instant. current)
These registers store the instantaneous value of each input voltage and current. Voltage is
expressed in 16bit format and current is expressed in 18bit format.
MS1285-E-00
2011/02
- 43 -
Initial
value
[AK5602A]
RMS value (ADD. 29h, 2Ah, 2Bh, 2Ch, 2Dh, 2Eh)
Address
A6-0
data
bit15
bit7
bit14
bit6
bit13
bit5
bit12
bit4
bit11
bit3
bit10
bit2
29h
(R)
V1RMS15-8 (Higher bits of CH1 voltage RMS value)
2Ah
(R)
V2RMS15-8 (Higher bits of CH2 voltage RMS value)
2Bh
(R)
V3RMS15-8 (Higher bits of CH3 voltage RMS value)
V1RMS7-2 (Lower bits of CH1 voltage RMS value)
bit9
bit1
bit8
bit0
-
-
-
-
-
-
V2RMS7-2 (Lower bits of CH2 voltage RMS value)
V3RMS7-2 (Lower bits of voltage RMS value)
2Ch
(R)
I1RMS17-10 (Higher bits of CH1 current RMS value)
2Dh
(R)
I2RMS17-10(Higher bits of CH2 current RMS value)
2Eh
(R)
I3RMS17-10(Higher bits of CH3 current RMS value)
Initial
value
0000h
0000h
0000h
0000h
I1RMS9-2(Lower bits of CH1 current RMS value)
0000h
I2RMS9-2(Lower bits of CH2 current RMS value)
0000h
I3RMS9-2(Lower bits of CH3 current RMS value)
These registers store the RMS value of each input voltage and each input current. Voltage is
expressed in 14 bit format and Current is expressed in 16 bit format.
Active power value (ADD. 30h, 31h, 32h, 33h, 34h, 35h, 36h, 37h)
Address
A6-0
data
bit15
bit7
bit14
bit6
bit13
bit5
-
-
-
-
bit9
bit1
bit8
bit0
-
-
-
-
-
P1_19-16 (Highest bits of CH1 active power)
-
-
-
-
-
-
-
-
-
-
-
P2_19-16 (Highest bits of CH2 active power)
P3_15-8 (Higher bits of CH3 active power)
-
-
-
-
-
-
-
-
-
-
-
P3_19-16(Highest bits of CH3 active power)
PSUM15-8(Higher bits of total active power (P1+P2+P3 ))
-
-
-
-
-
-
-
-
PSUM21-16(Highest bits of total active power(P1+P2+P3))
These registers store the active power value of each input channel. Each active power value is
expressed in 20 bit format and total active power value is expressed in 22 bit format.
MS1285-E-00
2011/02
- 44 -
0000h
0000h
PSUM7-0(Lower bits of total active power (P1+P2+P3))
-
0000h
0000h
P3_7-0 (Lower bits of CH3 active power)
-
0000h
0000h
P2_7-0 (Lower bits of CH2 active power)
-
Initial
value
0000h
P2_15-8 (Higher bits of CH2 active power)
36h
(R)
37h
(R)
-
-
34h
(R)
35h
(R)
bit10
bit2
P1_7-0 (Lower bits of CH1 active power)
32h
(R)
33h
(R)
bit11
bit3
P1_15-8 (Higher bits of CH1 active power)
30h
(R)
31h
(R)
bit12
bit4
0000h
[AK5602A]
Reactive power value (ADD. 38h, 39h, 3Ah, 3Bh, 3Ch, 3Dh, 3Eh, 3Fh)
Address
A6-0
data
bit15
bit7
bit14
bit6
-
-
-
-
-
-
-
-
bit9
bit1
bit8
bit0
-
-
-
-
-
-
-
-
Q1_19-16 (Highest bits of CH1 reactive power)
-
-
-
-
-
-
-
-
Q2_19-16 (Highest bits of CH2 reactive power)
-
-
-
-
-
-
-
-
-
-
Q3_19-16 (Highest bits of CH3 reactive power)
QSUM15-8 (Higher bits of total reactive power (Q1+Q2+Q3))
-
-
-
-
-
-
-
0000h
0000h
QSUM7-0 (Lower bits of total reactive power (Q1+Q2+Q3))
-
0000h
0000h
Q3_7-0 (Lower bits of CH3 reactive power)
-
0000h
0000h
Q3_15-8 (Higher bits of CH3 reactive power)
-
Initial
value
0000h
Q2_7-0 (Lower bits of CH2 reactive power)
3Eh
(R)
3Fh
(R)
bit10
bit2
Q2_15-8 (Higher bits of CH2 reactive power)
3Ch
(R)
3Dh
(R)
bit11
bit3
Q1_7-0 (Lower bits of CH1 reactive power)
3Ah
(R)
3Bh
(R)
bit12
bit4
Q1_15-8 (Higher bits of CH1 reactive power)
38h
(R)
39h
(R)
bit13
bit5
-
-
QSUM21-16(Highest bits of total reactive power (Q1+Q2+Q3))
0000h
These registers store the reactive power value of each input channel. Each reactive power
value is expressed in 20 bit format and total reactive power value is expressed in 22 bit format.
All total active power value(ADD. 40h, 41h, 42h, 43h)
Address
A6-0
data
bit15
bit7
bit14
bit6
bit11
bit3
bit10
bit2
bit9
bit1
bit8
bit0
-
-
-
-
-
-
-
-
PTOTR23-16 (Highest bits of all total receiving active power)
PTOTT15-8 (Higher bits of all total transmitting active power)
-
-
-
-
-
-
-
PTOTT23-16 (Highest bits of all total transmitting active power)
These registers store all total receiving active power value (P1+P2+P3+RPL) and all total
transmitting active power value (P1+P2+P3+TPL). The value is expressed in 24 bit format
MS1285-E-00
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- 45 -
0000h
0000h
PTOTT7-0 (Lower bits of all total transmitting active power)
-
Initial
value
0000h
PTOTR7-0 (Lower bits of all total receiving active power)
42h
(R)
43h
(R)
bit12
bit4
PTOTR15-8 (Higher bits of all total receiving active power)
40h
(R)
41h
(R)
bit13
bit5
0000h
[AK5602A]
All total reactive power value (ADD. 44h, 45h, 46h, 47h)
Address
A6-0
data
bit15
bit7
bit14
bit6
bit11
bit3
bit10
bit2
bit9
bit1
bit8
bit0
-
-
-
-
-
-
-
-
QTOTR23-16 (Highest bits of all total receiving reactive power)
QTOTT15-8 (Higher bits of all total transmitting reactive power)
-
-
-
-
-
-
0000h
0000h
QTOTT7-0 (Lower bits of all total transmitting reactive power)
-
Initial
value
0000h
QTOTR7-0 (Lower bits of all total receiving reactive power)
46h
(R )
47h
(R )
bit12
bit4
QTOTR15-8 (Higher bits of all total receiving reactive power)
44h
(R )
45h
(R )
bit13
bit5
-
QTOTT23-16 (Highest bits of all total transmitting reactive power)
0000h
These registers store all total receiving reactive power value (Q1+Q2+Q3+RQL) and all total
transmitting reactive power value (Q1+Q2+Q3+TQL). The value is expressed in 24 bit format
Pulse count value of energy(ADD. 48h, 49h )
Address
A6-0
Data
bit15
bit7
bit14
bit6
48h
(R)
PD
-
49h
(R)
QD
bit13
bit5
bit12
bit4
bit11
bit3
bit10
bit2
bit9
bit1
bit8
bit0
PPULSE13 - 8
0000h
PPULSE7-0
-
QPULSE13-8
0000h
QPULSE7-0
These registers store active energy pulse values and reactive energy pulse values for one
second period. Both active energy pulse values (PPULSE13-PPULSE0) and reactive energy
pulse values (QPULSE13-QPULSE0) are expressed in 14 bit format. If the pulse count value
is overflowed, the count value is stopped with a maximum value. PD(ADD.’48h’ :bit15) shows
whether the active energy pulse is receiving pulse ( PD=’0’) or transmitting pulse(PD=’1’) as
same as QD(ADD.’49h’:bit15) shows whether the reactive energy pulse is receiving pulse
(QD=’0’) or transmitting pulse(QD=’1’).
‘1’ second timer is assumed that the frequency of using crystal is 12.9024MHz. If the frequency
of using crystal is not 12.9024MHz but ,for example 12.8MHz, the number of pulse count will
be ‘1008’, which is equal to 12.9024MHz / 12.8MHz at the rated voltage and the rated current.
MS1285-E-00
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Initial
value
[AK5602A]
Apparent power value (ADD. 4Ah, 4Bh, 4Ch, 4Dh, 4Eh)
Address
A6-0
Data
bit15
bit7
bit14
bit6
bit13
bit5
bit12
bit4
bit11
bit3
bit10
bit2
4Ah
(R)
S1_15-8 (Higher bits of CH1 apparent power)
4Bh
(R)
S2_15-8 (Higher bits of CH2 apparent power)
4Ch
(R)
S3_15-8 (Higher bits of CH3 apparent power)
4Dh
(R)
SSUM15-8 (Higher bits of total apparent power)
4Eh
(R)
bit9
bit1
bit8
bit0
0000h
S1_7-0 (Lower bits of CH1 apparent power)
0000h
S2_7-0 (Lower bits of CH2 apparent power)
0000h
S3_7-0 (Lower bits of CH3 apparent power)
0000h
SSUM7-0 (Lower bits of total apparent power)
-
-
-
-
-
-
-
-
-
-
-
-
Initial
value
SSUM17-16 (Highest bits 0000h
of total apparent power)
These registers store an apparent value (S1, S2, S3) on each phase and a total apparent power
value. The value of apparent value on each phase is expressed in 16 bit format and the value of
total apparent value is expressed in 18 bit format.
Accumulated power pulse value (ADD. 50h, 51h, 52h, 53h)
Address
A6-0
Data
bit15
bit7
bit14
bit6
bit13
bit5
bit12
bit4
bit11
bit3
bit10
bit2
50h
(R)
RXPO15-8 (Upper bits of RPO accumulated power pulse)
51h
(R)
TXPO15-8 (Upper bits of TPO accumulated power pulse)
52h
(R)
RXQO15-8 (Upper bits of RQO accumulated power pulse)
53h
(R)
TXQO15-8(Upper bits of TQO accumulated power pulse)
bit9
bit1
bit8
bit0
0000h
RXPO7-0 (Lower bits of RPO accumulated power pulse)
0000h
TXPO7-0 (Lower bits of TPO accumulated power pulse)
0000h
RXQO7-0 (Lower bits of RQO accumulated power pulse)
0000h
TXQO7-0 (Lower bits of TQO accumulated power pulse)
These registers store upper 16 bits of accumulated power pulse. Each register is expressed in
16 bit format.
MS1285-E-00
2011/02
- 47 -
Initial
value
[AK5602A]
Power factor (54h, 55h, 56h)
Address
A6-0
Data
bit15
bit7
54h
(R)
-
55h
(R)
-
56h
(R)
-
bit14
bit6
bit13
bit5
bit12
bit4
bit11
bit3
bit10
bit2
bit9
bit1
bit8
bit0
PF1_14-8(CH1 power factor)
0000h
PF1_7-0(CH1 power factor)
PF2_14-8(CH2 power factor)
0000h
PF2_7-0(CH2 power factor)
PF3_14-8(CH3 power factor)
0000h
PF3_7-0(CH3 power factor)
These registers store power factors of CH1, CH2, CH3.Power factor is expressed by the value
between -1 and +1. There are two different ways of calculating power factor.
The one is to use the apparent power, which is derived from active power and reactive power
calculation. This selection of the calculation is the default setting. The other is to use the
apparent power, which is derived from RMS voltage and RMS current calculation. The
selection is made by the PFSEL (bit 6) bit of Function setting register,ADD.’20h’.
Power factor is expressed in two’s complementary expression.
The polarity of the reactive power in each input express whether the θ being derived from
power factor in each input is positve or nagative.
If bit3 of ADD. ‘39h’ or ‘3Bh’ or ‘3Dh’ is ‘0’, the θ in the input represents positive. If not, the θ
represents negative.
Power factor (-1.0 ∼ 1.0)
Value
2000h
1FFFh
∼
1000h
∼
0001h
0000h
7FFFh
∼
7000h
∼
6001h
6000h
Power factor
1.0
0.999878(8191/8192)
θ [degree]
0.0
0.8952
0.5
60.0
0.00012207
0.0
-0.00012207
89.993
90.0
90.00699
-0.5
120.0
-0.999878
-1.0
179.1047
180.0
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Initial
value
[AK5602A]
Temperature data (57h, 58h, 59h)
Address
A6-0
Data
bit15
bit7
bit14
bit6
bit13
bit5
bit12
bit4
bit11
bit3
bit10
bit2
bit9
bit1
bit8
bit0
57h
(R)
-
-
-
-
-
-
-
-
58h
(R/W)
-
59h
(R/W)
-
-
-
-
-
-
TEMP7-0 (Temperature data)
-
-
TEMP_COEF12-8 (Temperature gain coefficient)
-
-
-
-
TOFFSET4-0 (Temperature offset coefficient)
Temperature related data are stored in these registers.
It is possible to set TEMP bit (bit2) with ‘1’ of Function setting segister, ADD. ‘20h’ to
measure the temperature of the LSI and the measured temperature data is written into
Temperature register, ADD. ‘57h’.
Temperature data can be adjusted with the value of Temperature gain coefficient register,
ADD.‘58h’ and Temperature offset coefficient register,ADD.’59h’. When modifying the values
of the Temperature gain coefficient register and Temperature offset coefficient register, it is
needed to measure VREFI voltage at room temperature first and modify the value of the
Temperature gain coefficient register,ADD.’58h’ according to the following formula.
Relationship between VREFI voltage and setting value of the register is expressed as follows.
TEMP_COEF = 1C2Ah × (VREFI voltage / 1.17V)
After modifying the value of TEM_COEF, it is needed to measure the temperature by
setting TEMP bit (bit2) with ‘1’ of Function setting register,ADD.’20h’ to set the temperature
offset coefficient.
It is needed to adjust the difference after comparing this value with the value of present
room temperature according to the table of Temperature offset coefficient register,ADD.59h’
below.
It is needed to measure the temperature again by setting TEMP bit (bit2) with ‘1’ of Function
setting register,ADD.’20h’ to confirm that an appropriate adjustment is done.
As the initial value of temperature register is an invalid value, which is ‘80h’, please do not
use it as the temperature data.
Temperature register (-40 °C to 85 °C) : ADD. 57h
Value
Temperature (Celsius)
7Fh
55h
85 °C
∼
01h
1°C
00h
0°C
FFh
-1°C
∼
D8h
-40°C
80h
-
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0080h
1C2Ah
TEMP_COEF7-0 (Temperature gain coefficient)
-
Initial
value
0000h
[AK5602A]
Temperature offset coefficient register (ADD. 59h)
Value
Adjustment temperature (degree)
0Fh
+15°C
∼
01h
+1°C
00h
0°C
1Fh
-1°C
∼
10h
-16°C
Measured temperature data is written into the Temperature data register,ADD.’57h’ after the
temperature adjustment above is done against the value of temperature sensor.
5.3 PGA (Programmable Gain Controller)
Gain can be set from ‘1’ to ‘4’ at voltage input side and ‘1’ to ‘32’ at current input side.
Maximum input range is specified according to analogue input full-scale voltage. This
makes it possible to use ADC with the maximum resolution.
5.4 ADC block
5.4.1 ADC
ADC is started with RST = STBY = “H”
CH1’s, CH2’s and CH3’s ADC is timesharingly processed every 16XCLKs. 3 channel’s
ADC is processed by using 4096XCLKs. This means that ADCs for 3 channels are
performed at the rate of 3.15kHz when XCLK is 12.9024MHz.
It usually requires about 300mS to stabilize the VREF, XCLK and HPF after ADC is
started with RST = STBY = “H”. And it is not guaranteed the accuracy of ADC during
this 300ms period.
RST
STBY
4096XCLK
A/D
ch1/ch2/ch3
ch1/ch2/ch3
ch1/ch2/ch3
ch1/ch2/ch3
RDY
3820XCLK
Fig.8 ADC timing
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5.4.2 Calibration of ADCs
Calibration, offset adjustment of ADC will be started when CAL bit( bit7) of Function
setting register,ADD.’20h’ is set ‘1’ under the condition of RST = STBY = “H”.
It requires 4096 XCLKs to complete the calibration and ADC will be restarted after the
calibration.
RDY
signal becomes “High” state as soon as the calibration starts. The RMS
calculation and the active power to frequency conversion block are suspended during the
calibration. The calibration operation is not executed when only the power is applied to
the LSI ( RST =“L”). HPF is not set in the default setting. In a case that HPF is not used
in the system, it is recommended to execute the calibration command once or write the
calibration data, which has been measured before into the offset register in order to get an
accurate ADC data. And in the case that HPF is used in the system, it is recommended to
set a HPF after the calibration command being executed.
It is needed to execute the calibration operation after the setting of PGA. The setting of
PGA should be executed after more than 300ms has passed under the state of RST =
STBY = “H” .
RST
CAL (Internal)
4096XCLK
A/D
ch1/ch2/ch3
ch1/ch2/ch3
CAL
ch1/ch2/ch3
RDY
3820XCLK
Fig.9 Calibration timing
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5.4.3 RDY ( ADC’s instantaneous value) control
RDY signal for reading instantaneous values of ADC is set and output by setting
RDY1-0 (bit1-0)=’01’ of the Control setting register, ADD. ‘21h’.
When RDY becomes “L”, it means that accurate values of registers storing ADC’s value
can be read out.
The low level of RDY is output while CH1’s ADC is executed after the ADC block has
started under the condition of RST = STBY = “H”.
RDY signal becomes “L” in 280XCLKs after CH1’s ADC has started and returns “H”
in 3816XCLKs(about 295.7us).
RDY remains “H” while RST or STBY is “L”.
XCLK
A/D
ADC value
register
4095 0
279 280
4095 0
ch 1/ch 2/ch 3
279 280
ch 1/ch 2/ch 3
V1, I1, V2, I2, V3, I3
V1,I1,V2,I2,V3,I3
write inst. v alue
Rewrite inst. value
3816XCLK
RDY
Fig10 ADC inst. value readout timing
When the reading out data timing of instantaneous values of ADCs collide with the timing
of writing into instantaneous values by the LSI, INVALID status (bit15) of the controlling
register, ADD.‘21h’ is set. When the collision occurs, it is necessary to read the register
again.
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5.4.4 RDY (ADC’s RMS value) control
RDY
signal for reading RMS values of ADC is set and output
by setting
RDY1-0(bit1-0)=’00’ of Control setting register, ADD. ‘21h’.
When RDY becomes “L”, it means that accurate values of registers storing ADC’s value
can be read out.
The low level of RDY is output while CH1’s ADC is executed after the ADC block has
started under the condition of RST = STBY = “H”.
RDY signal becomes “L” in 1872XCLK after CH1’s ADC has started and returns “H” in
3384XCLK(about 262.3us) .
RDY remains “H” while RST or STBY is “L”.
XCLK
A/D
ADC value
register
4095 0
1019 1020
1871 1872
4095 0
1019 1020
ch 1/ch 2/ch 3
ch 1/ch 2/ch 3
V1,I1,V2,I2,V3,I3
V1,I1,V2,I2,V3,I3
write RMS value
Rewrite RMS value
3384XCLK
RDY
Fig.11 ADC RMS readout timing
When the reading out data timing of RMS values of ADCs collide with the timing of
writing RMS values into registers by the LSI , INVALID status (bit15) of Control setting
register, ADD. ‘21h’ is set. When the collision occurs, it is necessary to read the register
again.
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5.4.5 RDY (Other registers: Add.22h - 57h) control
RDY signal for reading registers addressing ‘22h’ to ‘57h’ is set and output by setting
RDY1-0 (bit1-0)=’10’ or ‘11’ of Control setting register, ADD. ‘21h’.
When RDY becomes “L”, it means that accurate values of various registers can be read
out.
The low level of RDY is output while CH1’s ADC is executed after the ADC block has
started under the condition of RST = STBY = “H”.
RDY signal becomes “L” in 3164XCLK after CH1’s ADC has started and returns “H” in
932XCLK(about 72.2us).
RDY remains “H” while RST or STBY is “L”.
When the reading out data timing of a register collide with the timing of writing data into
the register by the LSI, INVALID status (bit15) of Control setting register, ADD.‘21h’ is set.
When the collision occurs, it is necessary to read the register again.
XCLK
ADC
ADC
registers
4095 0
3163 3164
4095 0
ch 1/ch 2/ch 3
ch 1/ch 2/ch 3
Write data into registers (Add. 22h
to57h) by the LSI
932XCLK
RDY
Fig.12 Data registers readout timing
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[AK5602A]
5.5 HPF
It is possible to insert a HPF into voltage sides and current sides in order to remove DC
components on input channels. This HPF is placed on a path after each ADC block. This
means that DC components super imposed on as one part of an input signal and produced
by an ADC block can be removed.
HPFs are inserted into all channels of voltages and currents simultaneously. It is possible
to use HPF by setting bit3=’1’ of Function setting register, ADD.‘20h’.
HPFs are not set in the default setting with RST = “L”.
In case of using HPFs, it is recommended to set HPFs after executing the calibration
command.
Gain and phase characteristics of the HPFs are shown from Fig.13 to Fig15.
Gain Response
0
-0.5
-1
Magnitude [dB]
-1.5
-2
-2.5
-3
-3.5
-4
-4.5
-5
0.1
1
10
100
1000
Frequency [Hz]
Fig.13 Gain – Frequency characteristics
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Phase Response
10
9
8
Phase [degrees]
7
6
5
4
3
2
1
0
0.1
1
10
100
1000
Frequency [Hz]
Fig.14 Phase –Frequency characteristics
Phase Response
2.0
1.8
1.6
Phase [degrees]
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
40
45
50
55
60
65
70
Frequency [Hz]
Fig.15 Phase – Frequency Characteristics (40Hz to 70Hz)
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5.6 RMS calculation
RMS calculation block calculates RMS value of V1, I1, V2, I2, V3 and I3 from ADC value.
These values can be read from RMS registers.
RMS calculation flow is shown in fig.16
(1) To calculate square value of V1 (I1, V2, I2, V3, I3)
(2) Averaging
(3) To calculate the square root
V1 (I1, V2, I2, V3, I3)
(1)
(2)
(3)
LPF
RMS
Fig .16 RMS calculation flow
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5.7 Active power and reactive power to frequency converter
XP+RPL or -XP+TPL data, which consists of significant 24bit, is supplied to active or
reactive frequency converter at the rate of 3.15kHz. (note 1)
Active or reactive power to frequency converter is making an arithmetic operation at
the rate of 16/3 (16.8kHz) and produces RPO (RQO), TPO (TQO), RPST (RQST) and TPST
(TQST) output.
Active or reactive power to frequency converter stops its operation with RST = “L” or
STBY = “L” or DIS = “L”.
(note 1) The structure of XP+RPL
21
0
22 bit
XP
+)
7
RPL
23
8 bit
0
24 bit
XP+RPL
0
It is possible to select an apparent power as an input of reactive power to frequency
converter by setting ‘1’ of bit14 at Power addition “disable” setting register, ADD.’1Dh’.
Furthermore, as an apparent power does not have the light load register, 22 bit apparent
power value is shift in two bits left. As the result, 24 bit format data is input at ALU and is
converted into the power pulse.
3.15kHz 16.8kHz
XP+RPL
24 bit
Reg
ALU (28 bit)
Magnitude comparator
if PO = 1
then
A Å A+XP+RPL–WRP
else
A Å A+XP+RPL
A
if A ≥ WRP
then
PO Å 1
else
PO Å 0
Creep protection
PO
RP: rated value WRP
-XP+TPL
24 bit
Reg
if PO = 1
then
B Å B–XP+TPL–WTP
else
B Å B–XP+TPL
B
if B ≥ WTP
then
PO Å 1
else
PO Å 0
if PO frequency ≥ TRP
then
RPO Å 0
RPST Å 0
else
RPO Å PO
RPST Å 1
PO
if PO frequency ≥ TTP
then
TPO Å 0
TPST Å 0
else
TPO Å PO
TPST Å 1
TP: starting value TTP
Fig .17 Active power to frequency conversion
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RPST
RP : starting value T RP
TP: rated value WTP
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RPO
TPO
TPST
[AK5602A]
7FFFFFFh
WRP (WTP)
0000000h
underflow
F000000h
When ALU’s underflow occurs, the 28 bit
register is reset.
59.5us
RPO
(TPO, RQO, TQO)
T RP (TTP,T RQ,T TQ )
RPST
(TPST, RQST, TQST)
Fig.18 RPO (TPO, RQO, TQO) OUTPUT timing
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5.8 Frequency pulse output of V1, V2 and V3
The frequencies of voltage inputs are detected, being based on ADC value of V1, V2 and V3.
For example, when the rising threshold value of F1, F2,and F3 is set at ‘3000h’ and the falling
threshold value is set at ‘2000h’, the waveform will be shown below.
When V1, V2, V3 equals or greater than ‘3000h’, Fn (n=1, 2, 3) becomes “H”.
When V1, V2, V3 equals or smaller than ‘2000h’, Fn (n=1, 2, 3) becomes “L”.
This function is stopped at RST = “L” or STBY = “L”.
V1(V2,V3)
7FFFh
3000h
2000h
0000h
8000h
F1(F2,F3)
Fig.19 V1(V2,V3) frequency pulse output
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5.9 The way of various system calibrations
5.9.1 Calibration procedures of active power and reactive power (Japanese specification)
Japanese standard of power metering specifies that 1000 of power pulses per one second
should be output when rated input voltages and currents are applied to the system.
AK5602A provides an easy calibration method to comply with the specification.
By adjusting rated active or reactive power threshold value in receiving and transmitting
side, the accuracy of the equipment would be attained. General way of the calibration is
described below.
(1) Power on the system.
(2) To control RST = “H”
(3) To control STBY = “H”
(4) To control DIS = “H”
(5) To write ‘0080h’ at Function setting register, ADD. ‘20h’ to calibrate ADCs
(6) To write ‘0008h’ at Function setting register, ADD. ‘20h’ to insert HPF on each voltage and
current input
(7) When calibrating receiving active power, apply 50Hz or 60Hz of 0.35Vrms(0.5Vop) AC
signal to each current and voltage input. The phase difference between voltage and
current of the signal on each channel should be ‘0’ degree. This means that the power
factor of each channel should be ‘1.0’. The amplitude of the signal should be 0.35Vrms
when the PGA is set ×1. If the value of PGA is set other value rather than ×1 , the
amplitude of the signal should be changed accordingly. For instance, if the PGA set ×2, the
amplitude of the signal should be the half of 0.35Vrms. Under the condition, the number
of output pulses at RPO pin is counted over checking RPST flag and should be adjusted
until the number equals to 1000 for one second by modifying the value of RP rated active
power threshold value register, ADD.’00h’ and ‘01h’.
(8) When calibrating tranmitting active power, apply 50Hz or 60Hz of 0.35Vrms(0.5Vop) AC
signal to each current and voltage input. The phase difference between voltage and
current of the signal on each channel should be set at ‘180’ degree. This means that the
power factor of each channel should be ‘-1.0’. Under the condition, the number of output
pulses at TPO pin is counted over checking TPST flag and should be adjusted until the
number equals to 1000 for one second by modifying the value of TP rated active power
threshold value register, ADD. ‘02h’ and ‘03h’.
(9) When calibrating receiving reactive power, apply 50Hz or 60Hz of 0.35Vrms(0.5Vop) AC
signal to each current and voltage input. The phase difference between voltage and
current of the signal on each channel should be ‘90’ degree. This means that the power
factor of each channel should be 0. The amplitude of the signal should be 0.35Vrms when
the PGA is set ×1. If the value of PGA is set other value rather than ×1 , the amplitude of
the signal should be changed accordingly. For instance, if the PGA set ×2, the amplitude of
the signal should be the half of 0.35Vrms. Under the condition, the number of output
pulses at QPO pin is counted over checking RQST flag and should be adjusted until the
number equals to 1000 for one second by modifying the value of RQ rated reactive power
threshold value register, ADD.’04h’ and ‘05h’.
(10)
When calibrating tranmitting reactive power, apply 50Hz or 60Hz of 0.35Vrms(0.5Vop)
AC signal to each current and voltage input. The phase difference between voltage and
current of the signal on each channel should be ‘270’ degree. This means that the power
factor of each channel should be ‘0’. Under the condition, the number of output pulses at
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TQO pin is counted over checking TQST flag and should be adjusted until the number
equals to 1000 for every one second by modifying the value of TQ rated active power
threshold value register,ADD. ‘06h’ and ‘07h’.
(11)
It is possible to use pulse count values,ADD. ‘48h’ and ‘49h’ as the mothod of measuring
the number of output pulses instead of counting the number of output pulses from pulse
output pins(RPO, TPO, RQO, TQO). In this case, the inside timer of the AK5602A is used
for one second timer and the value of the timer will be changed according to the frequency
of using crystal. AK5602A defines that one second timer is attained when 12.9024MHz
crystal is used.
5.9.2 Initial value of Rated power threshold value (Japanese specification)
The initial value of Rated power threshold value is set so that 1000 power pulses for one
second would be output when the half of full scale AC signal is applied to each current input
and each voltage input. The initial value is calculated as follows.
Power value per channel is expressed as follows.
XP1=1/2×Vin×Iin
,where Vin = maximum voltage input (±1.0Vpp)
Iin = maximum current input (±1.0Vpp)
Initial value of Rated power threshold value is defined when half of maximum input voltage
and maximum input current is applied. Input voltage and current per channel is
Vin = 1/2 × (2^15) = 16384
Iin = 1/2 × (2^17) = 65536
And the bit width of Vin × Iin is 34 bit width, which is 16bit + 18bit, but it is needed to be
shrinked to 20bit wide by taking upper 20 bit and the result should be devided by 2^13.
So, power value per channel is XP1 = (1/2) ×16384 × 65536 × (1/(2^13)) = 65536
In a case that the same signal is applied to all 3ch, total power would be
XP = 65536 × 3=196608
The light load value is added to the XP, so the relsult is shifted left by 2 bit.
In a case of calculating receiving active power, using light load power value is RPL.
XP = XP + RPL = XP × 4 = 786432
This value is accumulated at the rate of 16.8 kHz and the pulse is output 1000 pulses per one
second. So, the enegy, W is described below.
W = (XP + RPL) × 16.8 = 13212057 = C99999h
This value is an initial value of receiving Rated active power threshold value.
This initial value is also applied to the initial value of transmitting Rated active power
threshold value, receiving Rated reactive power threshold value and transmitting Rated
reactive power threshold value.
5.9.3 Calibration procedures of active power and reactive power (IEC specification)
In IEC specification, the specification of creeping, starting current, pulse outputs is different
from that of Japanese standard. To comply with the IEC standard, it is needed to change
initial values of some registers. The following example shows that 1000 of power pulses per
one second are output and general relationship between power pulses and rated power
threshold value. Please calibrate the energy of the system by adjusting rated power threshold
values.
(1) Power on the system.
(2) To control RST = “H”
To set registers to comply with the IEC standard.
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1. To set the starting power threshold value register ‘o’ second : ‘FFFFh’ at Starting
power threshold value register,ADD. ‘08h’
2. To set the accumulation frequency of IEC power pulse width setting register
‘4.2kHz’ : ‘8000h’ at IEC power pulse width setting register,ADD. ‘1Fh’
3. To set the Function setting register ‘IEC creeping threshold value’ : ‘0010h’ at
Function setting register,ADD. ‘20h’
(3) To set rated active or reactive power threshold values in receiving and transmitting side
so that 1000 pulses per second would be output. In this case, it is assumed that using
crystal frequency is 12.9024MHz. When setting the IEC standard mode, the relationship
between the number of pulses and rated power threshold value is expressed as follows.
F (the number of pulses) = 3225600 / W (rated power threshold value)
W = 3225600 / 1000 = 3225.6 = 0C99h
‘0C99h’ is set at ADD.‘00h’, ‘02h’, ‘04h’, ‘06h’ and ‘0000h’ is set at ADD. ‘01h’, ‘03h’, ’05h’,
‘07h’.
(4) To control STBY = “H”
(5) To control DIS = “H”
(6) To write ‘0080h’ at Function setting register,ADD.‘20h’ to calibrate ADCs
(7) To write ‘0008h’ at Function setting register,ADD.’20h’ to insert HPF on each voltage and
current input
(8) When calibrating receiving active power, apply 50Hz or 60Hz of 0.35Vrms (0.5Vop) AC
signal to each current and voltage input. The phase difference between voltage and
current of the signal on each channel should be ‘0’ degree. This means that the power
factor of each channel should be ‘1.0’. The amplitude of the signal should be 0.35Vrms
when the PGA is set ×1. If the value of PGA is set other value rather than ×1, the
amplitude of the signal should be changed accordingly. For instance, if the PGA is set ×2,
the amplitude of the signal should be the half of 0.35Vrms. Under the condition, the
number of output pulses at RPO pin is counted and should be adjusted until the number
equals to 1000 for every one second by modifying the value of RP rated active power
threshold value register at ADD.’00h’ and ‘01h’.
(9) When calibrating tranmitting active power, apply 50Hz or 60Hz of 0.35Vrms (0.5Vop) AC
signal to each current and voltage input. The phase difference between voltage and
current of the signal on each channel should be ‘180’ degree. This means that the power
factor of each channel should be ‘-1.0’. Under the condition, the number of output pulses at
TPO pin is counted and should be adjusted until the number equals to 1000 for every one
second by modifying the value of TP rated active power threshold value register at ADD.
‘02h’ and ‘03h’.
(10)
When calibrating receiving reactive power, apply 50Hz or 60Hz of 0.35Vrms (0.5Vop)
AC signal to each current and voltage input. The phase difference between voltage and
current of the signal on each channel should be ‘90’ degree. This means that the power
factor of each channel should be 0. The amplitude of the signal should be 0.35Vrms when
the PGA is set ×1. If the value of PGA is set other value rather than ×1 , the amplitude of
the signal should be changed accordingly. For instance, if the PGA set ×2, the amplitude of
the signal should be the half of 0.35Vrms. Under the condition, the number of output
pulses at QPO pin is counted and should be adjusted until the number is equal to 1000 for
one second by modifying the value of RQ rated reactive power threshold value register at
ADD.’04h’ and ‘05h’.
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When calibrating tranmitting active power, apply 50Hz or 60Hz of 0.35Vrms(0.5Vop)
(11)
AC signal to each current and voltage input. The phase difference between voltage and
current of the signal on each channel should be ‘270’ degree. This means that the power
factor of each channel should be ‘0’. Under the condition, the number of output pulses at
TQO pin is counted and should be adjusted until the number is equal to 1000 for one
second by modifying the value of TQ rated active power threshold value register at ADD.
‘06h’ and ‘07h’.
(12)
It is possible to use pulse count values at ADD.’48h’ and ‘49h’ as the mothod of
measuring the number of output pulses instead of counting the number of output pulses
from pulse output pins (RPO, TPO, RQO, TQO). In this case, the inside timer in the
AK5602A is used for one second timer and the value of the timer will be changed according
to the frequency of using crystal. AK5602A defines that one second timer is attained when
12.9024MHz crystal is used.
(13)
In IEC setting mode, the pulse frequency per second, F is expressed as follows.
F (the number of pulses) = 3225600 / W (rated power threshold value)
Pulse frequency,F is varied according to the value of rated power threshold in the
following.
0.048065186263Hz ≤ F ≤ 8400Hz -------------------------------(a)
5.9.4 Initial value of Rated power threshold value (IEC specification)
The initial value of Rated power threshold value is set in Japanese specification so that 1000
power pulses for one second would be output when a half of full-scale of 50 to 60 Hz of AC
signal is applied to each current input and each voltage input. When AK5602A is used in IEC
mode, related registers and Rated power threshold value should be modified. The initial value
in IEC standard is calculated as follows.
Power value per channel is
XP1=1/2 × Vin × Iin
,where Vin = maximum voltage input (±1.0Vpp)
Iin = maximum current input (±1.0Vpp)
Initial value of Rated power threshold value is defined when half of maximum input voltage
and maximum input current is applied. Input voltage and current per channel is
Vin = 1/2 × (2^15) = 16384
Iin = 1/2 × (2^17) = 65536
And the bit width of Vin × Iin is 34 bit wide, which is 16bit + 18bit but it is needed to be
shrinked to 20bit wide by taking upper 20 bit and the result should be devided by 2^13.
So, power value per channel is XP1 = (1/2) × 16384 × 65536 × (1/(2^13)) = 65536
In a case that the same signal is applied to all 3ch, total power is expressed as follows.
XP = 65536 × 3=196608
The light load value is added to the XP, so the relsult is shifted left by 2 bit.
In a case of calculating receiving active power, using light load power value is RPL.
XP = XP + RPL = XP × 4 = 786432
And in IEC mode, pulse frequency,F is
F = 4200 × P / (W × 1024)
,where P = Total power, W = rated power threshold value
When half of maximum input voltage and maximum input current is applied to each channel ,
F = 4200 × 786432 / W × 1024 = 3225600 / W -------------------------------------(b)
In other expression, W = 3225600 / F
Maximum value of W(rated power threshold) is 3FFFFFh (67108863) and pulse frequency at
the value, FMIN is expressed as follows.
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FMIN = 3225600 / 67108863 = 0.048065186Hz
When the pulse frequency,F is 1000, W = 3225600 / 1000 = 3225.6 = C99h
In IEC mode, the value of pulse frequency should be set from around 0.1Hz to 2 or 3Hz.
The value of rated power threshold can be set according to the equation (a) and (b).
Explained setting rated power thereshold method is applied to transmitting active power
threshold value, receiving reactive power threshold value and transmitting reactive power
threshold value as well.
5.9.5 Calibration measure between input voltage and input current on each channel
(1) Please apply the rated input voltage and rated input current on each channel of the system.
In order to calibrate the phase error at only the 1st channel, the incoming signal at 2nd
channel and 3rd channel should be shortened by using shorting bits ’ZV2’, ’ZV3’, ’ZI2’, ’ZI3’
at Function setting register ‘20h’ lest should powers other than 1st channel be
accumulated.
(2) The number of receiving power pulses when voltage input and current input at power
factor being ‘1’ is defined as ‘A’. The number of receiving power pulses when voltage input
and current input at power factor being ‘0.5’ is defined as ‘B’. The phase error,α is expresed
as follows.
α = ( B - A /2 ) / (A/2)
Therefore the phase difference, β(degree) is
β = -SIN-1(α / √3)
To set value at Power factor adjustment value setting register(ADD. 0Dh, 0Eh, 0Fh) so that
α is equal to zero. When input signal frequency is 50Hz and using crystal frequency is
12.9024 MHz in AK5602A, the phase adjustment range, γ is expressed as followed.
-613.84us ( -11.05°) ≤ γ ≤ +613.84us (+11.05°)
It is possible to adjust the phase error with the resolution of 1.25us (0.0225°) per step.
(3) The phase error of 2nd channel and 3rd channel is also adjusted in the same manner as the
1st channel. Adjustment range and resolution are affected by using crystal frequency.
For example, the resolution of calibration range at 12.8MHz crystal is 1.25us (0.0225°).
5.9.6 Full scale vaue adjustment
This function is to adjust the variations produced by PGA and / or VREF from ideal value so
that the result of ADC has an ideal ADC code when a half of full-scale DC voltage, 0.5 V is
applied to each voltage and current channel. When using this function, the gain of all voltage
channels should be the same value as well as the gain of all current channels. The gain
between current and voltage can be changed. It is noted that after the adjustment, every
calculation including an instantaneous value, RMS value and active & reactive power is
affected. This is the only way to adjust RMS voltage value and RMS current value.
The adjustment of gain on voltage side is performed by setting ‘1’ to ‘bit0’, FULLV of Function
setting register at address ‘20h’.
And the adjustment of gain on current side is performed by setting ‘1’ to ‘bit1’, FULLI of
Function setting register at address ‘20h’.
After the execution of this command, the adjustment values can be read from ADD.‘16h’, ’17h’,
‘18h’. It is also possible to set the values as well by writing the values directly into these
registers.
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6. Recom m ended circuit diagram around AK5602A
+
Example of Voltage inputs(Registors)
0.1uF
10uF
N
AVDD
VREFI
VREFO
2
3
sam e as
V3
V1P
sam e
as V3
V2P
4.7
V3P
33nF
DVDD
VCOM
0.1uF
VS
+
1
4.7uF 0.1uF 0.1uF 0.1uF
500
2.7V to 5.25V
+ 10uF
500
33nF
VIN
Power line (3phase 4line)
N
1
Example of current inputs (CTs)
2 3
I1P
sam e as
I3P
sam e as
I3N
sam e as
I3P
sam e as
I3N
Input circuits
VIN
DVSS
AVSS
XIN
XOUT
12.8M Hz
15pF
500
500
15pF
1M
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I1P
I1N
I2P
I2N
33nF
I3P
I3N
33nF
(1) Input circuits to power lines above are only exam ples. It is
recomm ended that capacitors and resistors should be selected so
that the frequency of anti-aliasing filters is higher to prevent
from producing the phase error.
(2) It can not be guranteed that the value of resistors and capacitors
around the crystal oscillator is the best constants. It is recomm ended
to confirm the technical data of manufactures of crystal oscillators.
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7.0 Package conditions
1) Shape: LQFP
2) Pin count: 48PIN
3) Marking: Marking of the package is specified as follows.
a. No1 pin indication: There is a round mark and cutting edge.
b. AKM’s logo and product name
c. Date code XXXXXXX ( 7 digits)
AKM
AK5602A
XXXXXXX
7.1 Package outline
48pin LQFP (Unit: mm)
1.70Max
9.0 ± 0.2
0.10 ± 0.07
7.0
36
1.4
25
37
24
48
9.0 ± 0.2
7.0
12
13
1
12
0.09 ∼ 0.22
0.5
0.22 ± 0.08
0.10 M
0° ∼ 10°
0.10
0.3 ∼ 0.75
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Revision History
Date
01/02/03
Revision
00
Reason
First edition
Page
Contents
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi
Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products.
You are fully responsible for the incorporation of these external circuits, application circuits, software and
other related information in the design of your equipments. AKM assumes no responsibility for any losses
incurred by you or third parties arising from the use of these information herein. AKM assumes no liability for
infringement of any patent, intellectual property, or other rights in the application or use of such information
contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other
official approval under the law and regulations of the country of export pertaining to customs and tariffs,
currency exchange, or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life
support, or other hazard related device or systemNote2), and AKM assumes no responsibility for such use,
except for the use approved with the express written consent by Representative Director of AKM. As used
here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system
containing it, and which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to
function or perform may reasonably be expected to result in loss of life or in significant injury or damage
to person or property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise
places the product with a third party, to notify such third party in advance of the above content and conditions,
and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM
harmless from any and all claims arising from the use of said product in the absence of such notification.
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