ETC NX25F011B-3S

PRELIMINARY
DECEMBER 2001
NX25F011B, NX25F021B, NX25F041B
1M-BIT, 2M-BIT, AND 4M-BIT
SERIAL FLASH MEMORIES WITH 4-PIN SPI INTERFACE
This document contains PRELIMINARY INFORMATION. NexFlash reserves the right to make changes to its product at any time without notice in order to improve design and supply the best possible
product. We assume no responsibility for any errors which may appear in this publication.  Copyright 2001, NexFlash Technologies, Inc.
NexFlash Technologies, Inc.
PRELIMINARY NXSF016F-1201
12/12/01 ©
1
NX25F011B
NX25F021B
NX25F041B
Table of Contents
1M-BIT, 2M-BIT, AND 4M-BIT ......................................................................................................................................... 1
SERIAL FLASH MEMORIES WITH 4-PIN SPI INTERFACE .......................................................................................... 1
FEATURES ..................................................................................................................................................................... 4
DESCRIPTION ............................................................................................................................................................... 4
FUNCTIONAL OVERVIEW ............................................................................................................................................. 5
Pin Descriptions ....................................................................................................................................................... 5
Package ............................................................................................................................................................... 5
Serial Data Input (SI) ............................................................................................................................................ 6
Serial Data Output (SO) ....................................................................................................................................... 6
Serial Clock (SCK) ............................................................................................................................................... 6
Chip Select (CS) .................................................................................................................................................. 6
Write Protect (WP) ............................................................................................................................................... 6
Hold or Ready/Busy (HOLD or R/B) ...................................................................................................................... 6
Power Supply Pins (Vcc and Gnd) ........................................................................................................................ 6
Serial Flash Memory Array ....................................................................................................................................... 7
Serial SRAM ............................................................................................................................................................. 8
Using the SRAM Independent of Flash Memory ................................................................................................... 9
Write Protection ........................................................................................................................................................ 9
Configuration Register .............................................................................................................................................. 9
Write Protect Range and Direction, WR[3:0], WD ................................................................................................ 10
Read Clock Edge, RCE ...................................................................................................................................... 10
Table 2A. Write Protect Range Sector Selection (Hex) ........................................................................................ 11
Table 2B. Write Protect Range Sector Selection (Hex) ........................................................................................ 11
Table 2C. Write Protect Range Sector Selection (Hex) ........................................................................................ 11
HOLD-R/B, HR[1:0] ............................................................................................................................................ 11
Status Register Bit Descriptions ............................................................................................................................. 12
Compare Not Equal, CNE ................................................................................................................................... 12
Power Detect, PD ............................................................................................................................................... 12
Write Enable/Disable, WE................................................................................................................................... 12
Command Set ........................................................................................................................................................ 13
Command Set for the NX25F011B, NX25F021B and NX25F041B Serial Flash Memory ..................................... 15
SERIAL FLASH SECTOR COMMANDS ....................................................................................................................... 16
Read From Sector (52H) ......................................................................................................................................... 16
Read From Sector with Auto Increment (50H) ......................................................................................................... 16
Read From Sector Low Frequency (51H) and .......................................................................................................... 16
Read From Sector Low Frequency with Auto Increment (5BH) ................................................................................ 16
Write Enable (06H) .................................................................................................................................................. 16
Write Disable (04H) ................................................................................................................................................. 16
Write to Sector Through SRAM (F3H) ..................................................................................................................... 18
SERIAL SRAM COMMANDS ....................................................................................................................................... 19
Write to SRAM Command (72H) ............................................................................................................................. 19
Read from SRAM (71H) .......................................................................................................................................... 19
Transfer All of SRAM to Sector (F3H) ..................................................................................................................... 20
Transfer All of Sector to SRAM (53H) ..................................................................................................................... 20
Compare Sector to SRAM (8DH) ............................................................................................................................ 21
CONFIGURATION AND STATUS COMMANDS ............................................................................................................ 21
Read Configuration Register (8CH) ......................................................................................................................... 21
Write Non-Volatile Configuration
Register (8AH) ........................................................................................................................................................ 22
2
NexFlash Technologies, Inc.
PRELIMINARY NXSF016F-1201
12/12/01 ©
NX25F011B
NX25F021B
NX25F041B
Table of Contents (cont’d)
Read Status Register (84H) .................................................................................................................................... 22
Clear Compare Status (89H) ................................................................................................................................... 23
Set Power Detection Bit (03H) ................................................................................................................................ 23
Reset Power Detection Bit (09H) ............................................................................................................................. 23
Read Device Information Sector (15H) .................................................................................................................... 24
SPECIAL SECTOR COMMANDS ................................................................................................................................. 24
Erase Sector (F1H) ................................................................................................................................................. 24
Erase Block (F4H) .................................................................................................................................................. 25
Write-only to Sector (F2H) ...................................................................................................................................... 25
COMPATIBILITY COMMANDS FOR 25xxxA SERIES DEVICES ................................................................................. 26
Read from SRAM (81H) .......................................................................................................................................... 26
Read Configuration Register (8BH) ......................................................................................................................... 27
Read Status Register (83H) .................................................................................................................................... 27
Transfer Sector to SRAM Clocked (54H) ................................................................................................................. 28
Compare Sector to SRAM Clocked (86H) ............................................................................................................... 28
Sector Format ........................................................................................................................................................ 29
High Data Integrity Applications .............................................................................................................................. 29
Write/Verify Flow .................................................................................................................................................... 29
Grouping Static and Frequently
Updated Data .......................................................................................................................................................... 29
ABOSOLUTE MINIMUM RATINGS .............................................................................................................................. 30
OPERATING RANGES ................................................................................................................................................. 30
1
2
3
4
5
6
DC ELECTRICAL CHARACTERISTICS (Preliminary) ................................................................................................. 30
AC ELECTRICAL CHARACTERISTICS (Preliminary) ................................................................................................. 31
SERIAL OUTPUT TIMING ............................................................................................................................................ 32
7
SERIAL INPUT TIMING ................................................................................................................................................ 32
HOLD TIMING .............................................................................................................................................................. 32
PACKAGING INFORMATION ........................................................................................................................................ 33
200-mil Plastic SOIC Package Code: (S) ............................................................................................................ 33
PACKAGING INFORMATION ........................................................................................................................................ 34
330 mil Plastic SOIC Package Code: (J) ............................................................................................................ 34
8
9
PACKAGING INFORMATION ........................................................................................................................................ 35
Plastic TSOP - 28-pins Package Code: Type I (V) ............................................................................................... 35
PRELIMINARY DESIGNATION .................................................................................................................................... 36
10
IMPORTANT NOTICE ................................................................................................................................................... 36
ORDERING INFORMATION ......................................................................................................................................... 36
LIFE SUPPORT POLICY ............................................................................................................................................. 36
11
Trademarks: ................................................................................................................................................................. 36
12
NexFlash Technologies, Inc.
PRELIMINARY NXSF016F-1201
12/12/01 ©
3
NX25F011B
NX25F021B
NX25F041B
FEATURES
DESCRIPTION
• Flash Storage for Resource-Limited Systems
– Ideal for portable/mobile and microcontroller-based
applications that store voice, text, and data
The NX25F011B, NX25F021B, and NX25F041B Serial
Flash memories provide a storage solution for systems
limited in power, pins, space, hardware, and firmware
resources. They are ideal for applications that store voice,
text, and data in a portable or mobile environment. Using
NexFlash's patented single transistor EEPROM cell, the
devices offer a high-density, low-voltage, low-power, and
cost-effective non-volatile memory solution. The devices
operate on a single 5V or 3V (2.7V-3.6V) supply for Read
and Erase/Write with typical current consumption as low as
2.5 mA active and less than 1 µA standby. Sector
erase/write speeds as fast as 7.5 ms increase system
performance, minimize power-on time, and maximize
battery life.
• 0.35µ NexFlash Memory Technology
– 1M/2M/4M-bit with 512/1024/2048 sectors
– Small 264-byte sectors
– Erase/Write time of 7.5 ms/sector (typical)
– Optional 8KB (32 sector) block erase for faster
programming
• Ultra-low Power for Battery-Operation
– Single 5V or 3V supply for read and erase/write
– 1 mA standby current, 2.5 mA active @ 3V (typical)
– Low frequency read command for lower power
• 4-pin SPI Serial Interface
– Easily interfaces to popular microcontrollers
– Clock operation as fast as 20 MHz
• On-chip Serial SRAM
– Single 264-byte Read/Write SRAM buffer
– Use in conjunction with or independent of Flash
– Off-loads RAM-limited microcontrollers
• Special Features for Media-Storage Applications
– Byte-level addressing for reads and SRAM writes
– Transfer or compare sector to SRAM
– Versatile hardware and software write-protection
– In-system electronic part number option
– Removable Serial Flash Module package option
– Serial Flash Development Kit
4
The NX25F011B, NX25F021B, and NX25F041B provide
1M-bit, 2M-bit, and 4M-bit of flash memory organized as 512,
1024, or 2048 sectors of 264 bytes each. Each sector is
individually addressable through basic serial-clocked commands. The 4-pin SPI serial interface works directly with
popular microcontrollers. Special features include: on-chip
serial SRAM, byte-level addressing, double-buffered sector
writes, transfer/compare sector to SRAM, hardware and
software write protection, alternate oscillator frequency, electronic part number, and removable Serial Flash Module
package option. Development is supported with the
PC-based SFK-SPI Serial Flash Development Kit.
NexFlash Technologies, Inc.
PRELIMINARY NXSF016F-1201
12/12/01 ©
NX25F011B
NX25F021B
NX25F041B
FUNCTIONAL OVERVIEW
Pin Descriptions
An architectural block diagram of the NX25F011B,
NX25F021B, and NX25F041B is shown in Figure 2. Key
elements of the architecture include:
Package
The NX25F011B, NX25F021B, and NX25F041B are
available in a 28-pin TSOP (Type I) surface mount package.
The NX25F011B and NX25F021B are available in either an
8-pin SOIC and a 14-pin TSOP package (contact NexFlash
for information on the 14-pin TSOP package). The
NX25F041B is also available in a 28-pin SOIC package.
See Figure 3A, 3B and Table 1 for pin assignments. All
interface and supply pins are on one side of the TSOP
package. The “No Connect” (NC) pins are not connected to
the device, allowing the pads and the area around them to
be used for routing PCB system traces. The devices are
also available in a cost-effective and space-efficient
removable Serial Flash Module package.
•
SPI Interface and Command Set Logic
•
Serial Flash Memory Array
•
Serial SRAM and Program Buffer
•
Write Protection Logic
•
Configuration and Status Registers
•
Device Information Sector
HOLD
OR R/B
WRITE CONTROL
LOGIC
16
HOLD OR
READ/BUSY
LOGIC
ROW DECODE (512, 1024 AND 2048 SECTORS)
WP
WRITE PROTECT LOGIC
DEVICE INFORMATION SECTOR (DIS)
(READ ONLY)
1
2
3
4
5
NexFlash
6
1, 2 AND 4 M-BIT
SERIAL FLASH MEMORY ARRAY
7
512, 1024 AND 2048
BYTE-ADDRESSABLE
SECTORS OF 264 BYTES EACH
ORGANIZED IN 16, 32, AND 64
BLOCKS OF 32 SECTORS PER BLOCK
8
CONFIGURATION
REGISTER
9
2112
STATUS
REGISTER
SRAM (264 BYTES)
SCK
CS
SI
SO
SPI
COMMAND
AND
CONTROL
LOGIC
SECTOR-ADDRESS
LATCH
9/10/11
HIGH-VOLTAGE
GENERATORS
8
8
8
11
COLUMN DECODE, SENSE AMP LATCH
AND DATA COMPARE LOGIC
DATA
BYTE-ADDRESS
LATCH/COUNTER
10
12
9
Figure 2. NX25F011B, NX25F021B, and NX25F041B Architectural Block Diagram
NexFlash Technologies, Inc.
PRELIMINARY NXSF016F-1201
12/12/01 ©
5
NX25F011B
NX25F021B
NX25F041B
Serial Data Input (SI)
The SPI bus Serial Data Input (SI) provides a means for data
to be written to (shifted into) the device.
Serial Data Output (SO)
The SPI bus Serial Data Output (SO) provides a means for
data to be read from (shifted out of) the device during a read
operation. When the device is deselected (CS=1 or HOLD=0)
the SO pin is in a high-impedance state.
Serial Clock (SCK)
All commands and data written to the Serial Input (SI) are
clocked relative to the rising edge of the Serial Clock (SCK).
All data read from the Serial Data Output (SO) is clocked
relative to the falling or rising edge of SCK as specified in
the non-volatile configuration register. The data output
clock edge is factory-programmed to the default condition
of the falling edge, allowing compatibility with standard SPI
systems. Clock rates of up to 20 MHz are supported.
CS
Chip Select (CS
CS)
The NX25F011B, NX25F021B, and NX25F041B are
selected for operation when the Chip Select input (CS) is
asserted low. SCK must be low when (CS) is asserted to a
low state. Upon power-up, an initial low-to-high transition of
CS is required before any command sequence will be
acknowledged. The device can be deselected to a
non-active state when CS is brought high. Once deselected,
SI
1
8
SO
SCK
2
7
GND
Hold R/B
3
6
VCC
CS
4
5
WP
the SO pin will enter a high-impedance state and power
consumption will decrease to standby levels unless programming is in process, in which case standby will resume
when programming is complete.
WP
Write Protect (WP
WP)
The Write Protect input (WP) works in conjunction with the
write protect range set in the configuration register bits.
When WP is asserted (active low) the entire Flash memory
array is write protected. When high, any Flash memory
sector can be written to unless its address is within the write
protect range that is set in the configuration register.
HOLD or R/B
B)
Hold or Ready/Busy (HOLD
This multifunction pin can serve either as a Hold input
(HOLD) or as a Ready-Busy output (R/B). The pin function
is user-programmable through the non-volatile configuration
register. Factory-programmed as a no-connect, the pin can
be reconfigured as a Ready-Busy output or as a Hold input
by setting the configuration register. See the configuration
register section of this data sheet for further details.
Power Supply Pins (Vcc and GND)
The NX25F011B, NX25F021B, and NX25F041B support
single power supply Read and Erase/Write operations in 5V
and 3V versions. Typical active power is as low as 2.5 mA
for the 3V version with standby current less than 1 µA.
GND
NC
NC
CS
SCK
SI
SO
NC
NC
NC
NC
NC
NC
NC
Figure 3A. NX25F011B and NX25F021B
Pin Assignments, 8-Pin SOIC
HOLD-R/B
NC
WP
NC
NC
VCC
GND
NC
NC
NC
CS
SCK
SI
SO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Figure 3B. NX25F011B, NX25F021B, and NX25F041B
Pin Assignments, 28-Pin TSOP (Type I)
6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
NC
NC
WP
NC
HOLD-R/B
NC
NC
NC
NC
NC
NC
NC
NC
Figure 3C. NX25F041B
Pin Assignments, 28-Pin SOIC
Table 1. Pin Descriptions
SI
SO
SCK
CS
Serial Data Input
Serial Data Output
Serial Clock Input
Chip Select Input
WP
Hold, R/B
Vcc
Write Protect Input
Hold Input or Read Busy Output
Power Supply
NexFlash Technologies, Inc.
PRELIMINARY NXSF016F-1201
12/12/01 ©
NX25F011B
NX25F021B
NX25F041B
Serial Flash Memory Array
mand. No pre-erase is needed. Instead, the device
incorporates an auto-erase-before-write feature that
automatically erases the addressed sector at the beginning
of the write operation. After a sector has been written, the
memory array will become busy while it is programming the
specified non-volatile memory cells of that sector. This
busy time will not exceed tWP during which time the Flash
array is unavailable for read or write access. The device
can be tested to determine the array’s availability using
the Ready/Busy status that is available during most read
commands, through the status register, or on the
Ready/Busy pin.
The NX25F011B, NX25F021B, and NX25F041B Serial
Flash memory arrays are organized as 512, 1024, and 2048
sectors of 264-bytes (2,112 bits) each, as shown in
Figure 4. The block size of the device is 32 sectors, yielding
16, 32 and 64 blocks for the NX25F011B, NX25F021B, and
NX25F041B.
The Serial Flash memory of the NX25F011B, NX25F021B,
and NX25F041B is byte-addressable for read operations.
This allows a single byte, or specified sequence of bytes,
to be read without having to clock an entire 264-byte sector
out of the device. Data can be read directly from a sector
in the Flash memory array by using a Read from Sector
command.
After sector programming is complete and the device is
ready, it is recommended to verify the data in the sector
with the data in the SRAM using the compare command,
(see Write/ Verify Flow towards the end of this data sheet).
Data can be written to the Flash memory array one sector
(264-bytes) at a time through the Serial SRAM using a Write
to Sector command or a Transfer SRAM to Sector com-
1
2
3
4
5
6
Sector Address:
25F011
S[8:0]
25F021
S[9:0]
25F041
S[10:0]
Block 16
Sector 511
1FFH
Block 32
Sector 1023
3FFH
Block 64
Sector 2047
7FFH
Byte 0
000H
Byte1
001H
Byte 2-261
002H-105H
Byte 262
106H
Byte 263
107H
Sector 480
1E0H
Sector 992
3E0H
Sector 2016
7E0H
Byte 0
000H
Byte1
001H
Byte 2-261
002H-105H
Byte 262
106H
Byte 263
107H
7
Byte Address: B[8:0]
8
1M-bit, 2M-bit, or 4M-bit Serial Flash Memory Array
512, 1024, and 2048 Byte-Addressable Sectors
of 264-Bytes each.
9
Organized in 16, 32 and 64
blocks of 32 sectors per block.
10
Block 0
Sector 31
1FH
Block 0
Sector 31
1FH
Block 0
Sector 31
1FH
Byte 0
000H
Byte 1
001H
Byte 2-261
002H-105H
Byte 262
106H
Byte 263
107H
Sector 0
000H
Sector 0
000H
Sector 0
000H
Byte 0
000H
Byte 1
001H
Byte 2-261
002H-105H
Byte 262
106H
Byte 263
107H
11
12
Figure 4. NX25F011B, NX25F021B, and NX25F041B Serial Flash Memory Array
NexFlash Technologies, Inc.
PRELIMINARY NXSF016F-1201
12/12/01 ©
7
NX25F011B
NX25F021B
NX25F041B
Serial SRAM
One of the most powerful features of the NX25F011B,
NX25F021B, and NX25F041B is the integrated Serial
SRAM. The main purpose of the Serial SRAM is to serve
as the primary buffer for sector data to be written into the
Serial Flash memory array. Using the Write to Sector
command, data is first shifted into the SRAM from the SPI
bus. When the command sequence has been completed, the
entire 264-bytes is written to the selected sector. See
Erase/Write cycle timing (tWP).
The SRAM is fully byte-addressable. Thus, the entire
264-bytes, a single byte, or a sequence of bytes can be read
from, or written to the SRAM. This allows the SRAM to be
used as a temporary work area for read-modify-write
operations prior to a sector write.
The Transfer Sector to SRAM command allows the contents of a specified sector of Flash memory to be moved to
the SRAM. This can be useful when only a portion of a sector
needs to be altered. In this case the sector is first transferred
to the SRAM, where modifications are made using the Write
to SRAM command. Once complete, a Transfer SRAM to
Sector command is used to update the sector.
The Compare Sector command allows the contents of the
SRAM to be compared with the specified sector in memory.
The result of the compare is set in the status register. This
command is useful for performing a fast verify of the last
sector write operation (see Write/ Verify Flow towards the
end of this data sheet). This command can be useful when
re-writing multi-sector files that have only minor changes
from the previous write. If the new data in the SRAM is the
same as the previously written data, the sector write can
be skipped. Used in this way, the command saves time
that would have been used for re-programming. It also
extends the endurance of the Flash memory cells.
DEVICE INFORMATION SECTOR
READ FROM
DEVICE INFORMATION
SECTOR
READ FROM
SECTOR
SERIAL FLASH MEMORY ARRAY
CONFIGURATION
REGISTER
512, 1024 AND 2048 BYTE-ADDRESSABLE
SECTORS OF 264-BYTES EACH
TRANSFER
SECTOR TO
SRAM
STATUS
REGISTER
SCK
CS
SI
SPI
COMMAND
AND
CONTROL
LOGIC
SO
COMPARE SECTOR
TO SRAM
READ FROM
OR WRITE TO
SRAM
WRITE TO SECTOR
(VIA SRAM)
SERIAL SRAM
Note:
1. A single byte, several bytes, or all bytes of a Flash sector, the SRAM, or Program Buffer may be addressed.
2. All double lines represent implied connections or actions.
Figure 5. Command Relationships of the SPI Interface, Serial Flash Memory Array and SRAM
8
NexFlash Technologies, Inc.
PRELIMINARY NXSF016F-1201
12/12/01 ©
NX25F011B
NX25F021B
NX25F041B
Using the SRAM Independent of Flash Memory
The SRAM can be used independently of Flash memory
operations for lookup tables, variable storage, or scratch
pad purposes. If the Flash memory needs to be written to
while SRAM is being used for a different purpose, the
contents can be temporarily stored to a sector and then
transferred back again when needed. The SRAM can be
especially useful for RAM-limited microcontroller-based
systems, eliminating the need for external SRAM and
freeing pins for other purposes. It can also make it possible
to use small pin-count microcontrollers, since only a few
pins are needed for the interface instead of the 20-40 pins
required for parallel bus-oriented Flash devices.
1
System Power-up
2
Read Device Information Sector,
Verify Device Density and Type
3
Read Configuration Register
Verify bits are Set as Needed
Write Protection
The NX25F011B, NX25F021B, and NX25F041B provide advanced software and hardware write protection
features. Software-controlled write protection of the entire
array is handled using the Write Enable and Write Disable
commands. Hardware write protection is possible using the
Write Protect pin (WP). Write-protecting a portion of Flash
memory is accommodated by programming a write protect
range in the configuration register. For applications
needing a portion of the memory to be permanently
write-protected or a fixed configuration register value, a
onetime programmable write protection feature is supported.
Contact NexFlash for further information.
4
Configuration
Setting is Correct?
Yes
5
No
Write Configuration Register
to Correct Setting
6
7
Configuration Register
The Configuration Register stores the current configuration
of the HOLD-R/B pin, read clock edge and write protect
range (Figure 7). The configuration register is accessed
using the Write and Read Configuration Register
commands. The non-volatile configuration register will
maintain its setting even when power is removed.
8
Application Routines
Figure 6. Flow Chart for Checking the Configuration
Register upon Power-up
To avoid unnecessary programming of the configuration
register, and to save time during power-up, the configuration
register should be read upon power-up and compared to the
intended setting before sending a Write Configuration
Register command (Figure 6).
9
10
11
12
NexFlash Technologies, Inc.
PRELIMINARY NXSF016F-1201
12/12/01 ©
9
NX25F011B
NX25F021B
NX25F041B
The factory default setting for the configuration register is
CF8-CF0 is: 0 0000 1001 B (write protect range = none, read
uses falling edge of the clock, and pin 1 = no connect). Bits
CF15-CF9 are reserved. When writing to the configuration
register CF15-CF9 should be 0. When reading, the settings
of CF15-CF9 should be ignored.
Write Protect Range and Direction, WR[3:0], WD
The write protect range and direction bits WR[3:0] and WD
are located at configuration bits CF[7:4] and CF[3] respectively. The write protect range and direction bits select how
the array is protected. They work in conjunction with the
WP input pin, valid only if WP is inactive (high). WR[3:0]
can select write protection of all sectors, none of the
sectors, or specific sectors grouped in blocks of 32
(~8 KB). The WD bit specifies whether the protected block
range starts from the first sector, address 0 (000H), or from
the last sector (1FFH for the NX25F011B, 3FFH for the
NX25F021B, and 7FF for the NX25F041B). Table 2A, 2B
and 2C lists the write protect sector range for the devices.
Once protected, all further writes to sectors within the
range will be ignored. The factory default setting is with no
write protected sectors, WR=[0,0,0,0] and WD=1.
Read Clock Edge, RCE
The Read Clock Edge bit (RCE) is located at configuration
bit location CF[2]. It selects which edge of the clock (SCK)
is used while reading data out of the device. Although the
SPI protocol specifies that data is written during the rising
edge and read on the falling edge of the clock, if required,
the output can be driven on the rising edge of the clock by
setting the configuration registers RCE bit to a 1. Using the
rising edge of clock for data reads may be beneficial to the
timing of some high-speed systems. The factory default
setting is the falling edge of SCK for standard SPI.
RCE=0 Read data is output on the falling edge of SCK
(Standard SPI).
RCE=1 Read data is output on the rising edge of SCK
(Fast SPI).
CF15:8
CF7
CF6
CF5
CF4
CF3
CF2
CF1
CF0
(RESERVED)
WR3
WR2
WR1
WR0
WD
RCE
HR1
HR0
WRITE PROTECT
RANGE
WRITE PROTECT
DIRECTION
READ DATA
CLOCK EDGE
HOLD-READY/BUSY
PIN FUNCTION
Figure 7. Configuration Register Bit Locations
10
NexFlash Technologies, Inc.
PRELIMINARY NXSF016F-1201
12/12/01 ©
NX25F011B
NX25F021B
NX25F041B
Table 2A. Write Protect Range Sector Selection (Hex)
Write Protect
Range Config. Bits
WR3 WR2 WR1 WR0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
(NX25F011B)
Write Protected Sectors
WD=0
None
000 - 01FH
000 - 03FH
000 - 05FH
000 - 07FH
000 - 09FH
000 - 0BFH
000 - 0DFH
000 - 0FFH
000 - 11FH
000 - 13FH
000 - 15FH
000 - 17FH
000 - 19FH
000 - 1BFH
ALL
WD=1
None
1 E0 - 1FF
1 C0 - 1FF
1 A0 - 1FF
1 80 - 1FF
1 60 - 1FF
1 40 - 1FF
1 20 - 1FF
1 00 - 1FF
0 E0 - 1FF
0 C0 - 1FF
0 A0 - 1FF
0 80 - 1FF
0 60 - 1FF
0 40 - 1FF
ALL
Table 2B. Write Protect Range Sector Selection (Hex)
Write Protect
Range Config. Bits
WR3 WR2 WR1 WR0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
(NX25F021B)
Write Protected Sectors
WD=0
None
000 - 01FH
000 - 03FH
000 - 05FH
000 - 07FH
000 - 09FH
000 - 0BFH
000 - 0DFH
000 - 0FFH
000 - 11FH
000 - 13FH
000 - 15FH
000 - 17FH
000 - 19FH
000 - 1BFH
ALL
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PRELIMINARY NXSF016F-1201
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Table 2C. Write Protect Range Sector Selection (Hex)
WD=1
None
3 E0 - 3FF
3 C0 - 3FF
3 A0 - 3FF
3 80 - 3FF
3 60 - 3FF
3 40 - 3FF
3 20 - 3FF
3 00 - 3FF
2 E0 - 3FF
2 C0 - 3FF
2 A0 - 3FF
2 80 - 3FF
2 60 - 3FF
2 40 - 3FF
ALL
Write Protect
Range Config. Bits
WR3 WR2 WR1 WR0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
(NX25F041B)
Write Protected Sectors
WD=0
None
000 - 01FH
000 - 03FH
000 - 05FH
000 - 07FH
000 - 09FH
000 - 0BFH
000 - 0DFH
000 - 0FFH
000 - 11FH
000 - 13FH
000 - 15FH
000 - 17FH
000 - 19FH
000 - 1BFH
ALL
1
WD=1
None
7 E0 - 7FFH
7 C0 - 7FFH
7 A0 - 7FFH
7 80 - 7FFH
7 60 - 7FFH
7 40 - 7FFH
7 20 - 7FFH
7 00 - 7FFH
6 E0 - 7FFH
6 C0 - 7FFH
6 A0 - 7FFH
6 80 - 7FFH
6 60 - 7FFH
6 40 - 7FFH
ALL
HOLD
B , HR[1:0]
HOLD-R/B
The Hold-Ready/Busy (HOLD-R/B) bits HR1 and HR0 are
located at bits CF[1:0] of the configuration register. These
two bits select one of four possible functions: No Connect,
HOLD input, R/B Output, or R/B Output with open drain. The
factory setting for the pin is “No Connect”.
HR1
HR0
Pin Configuration
0
0
1
1
0
1
0
1
HOLD input
No Connect
R/B Output (Open Drain)
R/B Output
2
3
4
5
6
7
8
9
Configured as a R/B output, the pin can serve as a system
interrupt. When R/B is high, the array is ready to be
programmed. When R/B is low, it is busy programming. If
configured with an open-drain, an external pull-up resistor
should be used.
As a HOLD input, the pin can be used in conjunction with
the CS and SCK pin to suspend a serial command
sequence without resetting the command. This can be
useful if a command is in process and a higher priority
task on the same SPI bus needs to be attended to. To
11
10
11
12
NX25F011B
NX25F021B
NX25F041B
suspend a command, HOLD must be brought low while
CS and SCK are low. With HOLD low, further data on the
SI pin is ignored (even while SCK is clocked) and the SO
pin goes to a high-impedance state. To resume the
command sequence, HOLD must be brought high when
CS and SCK are low. See timing diagrams.
Status Register Bit Descriptions
The status register provides status of the Flash array’s
Ready/Busy condition (R/B), transfers between the SRAM
and program buffer (TX), Write-Enable/Disable (WE), and
Compare Not Equal (CNE). The register can be read using
the Read Status Register command (Figure 8).
Ready/Busy Status, BUSY
The BUSY status bit is located at bit ST[7] of the status
register. Testing the BUSY bit is one of several ways to
check Ready/Busy status of the array. At power-up the
BUSY bit is reset to 0.
SRAM Transfer All or Compare All, TR
The TR status bit is located at bit ST[6] of the status
register. The bit provides status primarily for use during
the Transfer All Sector to SRAM command and Compare
All Sector to SRAM command. An active state 1 indicates a transfer is in process and the SRAM Array is not
available for use. The device will indicate a BUSY state
while the TR bit is active. Upon power up the TR bit resets
to 0.
TR=1 Transfer or Compare All in Process.
TR=0 Transfer or Compare All not in Process.
Write Enable/Disable, WE
The WE status bit is located at bit ST[4] of the status
register. The bit provides write protect status of global Write
Enable and Write Disable commands. Upon power- up the
WE bit resets to 0.
WE=1 Write Enabled, array can be written to.
WE=0 Write Disabled, array can not be written to.
BUSY=1 The device is busy programming.
BUSY=0 The deivce is ready for further use.
x =RESERVED
ST7
ST6
ST5
ST4
ST3
ST2
ST1
ST0
Busy
TR
X
WE
CNE
X
X
PD
READ/BUSY
POWER DETECT
SRAM TRANSFER OR COMPARE
SECTOR-SRAM COMPARE NOT EQUAL
FLASH ARRAY WRITE ENABLE/DISABLE
Figure 8. Status Register Bit Locations
Compare Not Equal, CNE
The CNE status bit is located at bit ST[3] of the status
register. The bit provides a cumulative comparison result
during a Compare Sector with SRAM command. The CNE
bit is reset to a 0 upon power-up or after a Clear Compare Bit
command is executed.
Power Detect, PD
The Power Detect bit works in conjunction with the Set
Power Detection and Reset Power Detection Commands
and is primarily used for removable media applications. The
Set Power Detect Command must be issued before the PD
bit can be used for power detection.
CNE=1 Sector and SRAM contents are not equal.
CNE=0 Sector and SRAM are equal or CNE bit reset.
PD=0 Power has been removed
PD=1 Power has not been removed
12
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NX25F011B
NX25F021B
NX25F041B
Command Set
The NX25F011B, NX25F021B, and NX25F041B have a
powerful command set that is fully controlled through the
SPI bus. Command relations are shown in Figure 5 and a
list of commands and their associated address, status,
clock, and data bytes are shown in Table 3. Detailed clock
timing of the Read Sector and Write Sector command
sequences are shown in Figures 9 and 10.
1
2
After power up, a device enters an idle state that will
maintain until CS pin is asserted low. All commands are
entered from the SPI serial data input (SI) pin on the rising
edge of SCK while CS is asserted low. All command,
address, and configuration bits are shifted into the device
with most-significant-bit-first. Data bits read from the
device are shifted out with least significant byte first
(i.e., byte-00H, byte-01H,...). The bit order within each
byte is most-significant-bit first (i.e.,D7,...D0). All commands are completed by asserting the CS pin high.
3
4
5
Note that the entire 264-byte contents of a Flash sector or
the SRAM does not have to be accessed all at once. Read,
Write, Transfer Clocked, and Compare Clocked commands allow for byte addressing. Thus a single byte, or
clocked sequence of bytes, can be accessed at any
starting location within the 264-byte boundary as specified
by the byte-address field.
6
7
8
9
10
11
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NX25F011B
NX25F021B
NX25F041B
CS
C[7:0] Command
Idle
S[15:0] Sector Address
SCK
C7 C6 C5 C4 C3 C2 C1 C0 0
SI
0
0
0
0 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
SO Output is Driven
16 Clocks
B[15:0] Byte Address
SCK
SI
0
0
0
0
0
0
0
B8 B7 B6 B5 B4 B3 B2 B1 B0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SO
High-Z
RB[15:0] Ready/Busy Status (9999H=Ready)
1st Byte of Data
2nd Byte of Data
SCK
SO
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D4 D5 D3 D2 D1 D0
Last Byte of Data
n-Bytes of Data
CS
Idle
SCK
SO
D7 D6 D5 D4 D3 D2 D1 D0
High-Z
Figure 9. Read from Sector Command Sequence
CS
C[7:0] Command
Idle
S[15:0] Sector Address
SCK
C7 C6 C5 C4 C3 C2 C1 C0 0
SI
0
0
0
B[15:0] Byte Address
0 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
1st Byte of Data
2nd Byte of Data
SCK
SI
CS
0
0
0
0
0
0
n-Bytes of Data
0
B8 B7 B6 B5 B4 B3 B2 B1 B0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Last Byte of Data
8 Clocks
tWP Program Time
SCK
SI
D7 D6 D5 D4 D3 D2 D1 D0 0
0
0
0
0
0
0
0
Figure 10. Write to Sector Command Sequence
14
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NX25F011B
NX25F021B
NX25F041B
Command Set for the NX25F011B, NX25F021B and NX25F041B Serial Flash Memory
Command Name
Byte 0 Byte 1-2
Sector Commands
Read From Sector
52H Sector address
Read From Sector w/AutoInc (3)
50H Sector address
Read From Sector Low Freq.
51H Sector address
Read From Sector
5BH Sector address
w/AutoInc Low Freq (3)
Write Enable (1)
06H 00H
Write Disable (1)
04H 00H
(2)
Write to Sector (through SRAM)
F3H Sector address
Serial SRAM Commands
Write to SRAM (2), (3)
72H Byte address
Read from SRAM (1),(3)
71H Byte address
Transfer all of SRAM to Sector
F3H Sector address
(3)
Transfer all of Sector to SRAM
53H Sector address
(3)
Compare Sector to SRAM
8DH Sector address
Configuration and Status Commands
Read Configuration (1), (3)
8CH Configuration
Write Non-Volatile
8AH Configuration
Configuration Register (1)
Read Status Register (1), (3)
84H Status (8 bits)
Clear Compare Status (1)
89H
(1), (3)
Set Power Detection Bit
03H
(1), (3)
Reset Power Detection Bit
09H
Read Device Information Sector
15H 0000H
(3),(4)
Special Sector Commands
Erase Sector
F1H Sector address
Erase Block
F4H Block address
Write-Only to Sector through SRAM
F2H Sector address
Compatibility Commands for 25xxxA Series Devices
Read from SRAM
81H 0000H
Write to SRAM
82H 0000H
Read Configuration Register
8BH 0000H
Read Status Register
83H 0000H
Transfer Sector to SRAM Clocked
54H Sector address
Compare Sector to SRAM Clocked
86H Sector address
Byte 3-4
Byte address
0000H
Byte address
0000H
n- bytes
(Italics indicate device output)
0000H
0000H
0000H
0000H
Ready/Busy
Ready/Busy
Ready/Busy
Ready/Busy
1
Read Data
Read Data
Read Data
Read Data
2
3
Byte address
Write Data 00H
Write data
00H
0000H
0000H
Byte address
00H
Read Data
4
5
0000H
0000H
6
0000H
7
Ready/Busy
Byte address
0000H
0000H
0000H
Byte address
Write Data 00H
Byte address
Byte address
0000H
0000H
Byte address
Byte address
0000H
Write data
0000H
0000H
N*00H
0000H
8
DIS Data
9
Read/Busy
Read Data
00H
Ready/Busy
Configuration
Ready/Busy
Status
00H
Ready/Busy Bit compare of data
Notes:
1. Command may be used when device is busy
2. Command may not be used when device is busy and TR bit=0
3. New “B” series command
4. Warning: Read description of these commands before using to ensure reliable operation.
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10
11
12
15
NX25F011B
NX25F021B
NX25F041B
SERIAL FLASH SECTOR COMMANDS
Read From Sector (52H)
Reading from a sector is accomplished by first bringing
CS low then shifting in the Read from Sector command
(52H) followed by its 16-bit “sector-address” field.
Although the sector-address field is 16-bits, only bits
S[8:0] for the NX25F011B (0-1FFH), S[9:0] for the
NX25F021B (0-3FFH), S[10:0] for the NX25F041B
(0-7FFH) are used. The uppermost sector address bits
are not used but must be clocked using 0 for data. Next
a 16-bit “byte-address” field is clocked into the device to
designate the starting location within the 264-byte
sector. Only B[8:0] of the byte-address field are used;
the uppermost bits are not used but must be clocked in
(use 0 for data). Only byte-addresses of 0 to 107H
(264 bytes) are valid. Following the byte-address field,
16 control clocks are required with data=0.
The Serial Data Output (SO) will change from a
high-impedance state and begin to drive the output with
Ready/Busy status RB[15:0]. If SO uses the rising edge
of clock (configuration register RCE=1), the output will
be driven after the last control clock. If SO uses the
falling edge of clock (RCE=0), the output will be driven
on the next falling edge of clock. If the array is not busy,
the output status will be 9999H, followed by the sector
data on the SO pin. If the array is busy, the status will be
6666H, and the command should be terminated and
restarted after a ready state occurs. The data field is
shifted out with the least significant byte first (i.e.,
byte-00H, byte-01H, ...). The bit order within each byte
is the most significant bit first (i.e.,D7,...D0). The
SI
SO
byte-address is internally incremented to the next higher
byte address as the clock continues. When the highest
byte-address (107H) is reached, the address counter
rolls over to byte-0H and continues to increment. Asserting the CS pin high completes (or terminates) the
command. Detailed timing for the Read from Sector
command is shown in Figure 10.
Read From Sector with Auto Increment (50H)
The Read from sector with Auto Increment command
operates similar to the standard Read from Sector command except that after the last bit of the current sector is
clocked the next sequentially addressed sector will be
automatically selected for reading without requiring the nine
byte command sequence to be issued. This allows the
entire device or a large number of sectors to be read out with
a single command.
Read From Sector Low Frequency (51H) and
Read From Sector Low Frequency with Auto
Increment (5BH)
The Read From Sector at Low Frequency command (51H)
and Read From Sector Low Frequency with Auto Increment
command (5BH) can reduce power consumption during read
operations by 25%-40% when the system clock frequency
is 1 MHz or lower. The command sequences are identical to
the standard commands.
Read from
Sector
Command
Sector
Address*
Byte
Address**
16 Clocks
52H, 50H, 51H, 53H
S[15:0]
B[15:0]
0000H
RB[15:0]
Read/Busy
Status
First Byte - Last Byte
Read Sector Data
*The sector address only uses bits [8:0], [9:0] or [10:0] Depending on the density
**The byte address only uses bits [8:0]. Byte address must be 0000h for Auto Increment commands
16
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NX25F011B
NX25F021B
NX25F041B
Write Enable (06H)
Upon power-up, the Flash memory array is write- protected
until the Write Enable command (06H) has been issued. The
WP pin must be inactive while writing the command for the
write enable to be accepted. The status of the device’s write
protect state can be read in the status register. The Write
Enable command sequence is completed by asserting CS
high after eight additional clocks.
SI
Write Enable
Command
8 Clocks
06H
00H
1
2
SO
3
4
Write Disable (04H)
The Write Disable command (04H) protects the Flash
memory array from being programmed. Once issued, further Write to Sector or Transfer SRAM to Sector commands
will be ignored. The status of the write protect state can be
read in the status register. The Write Disable command
sequence is completed by asserting CS high after eight
additional clocks.
SI
Write Disable
Command
8 Clocks
04H
00H
5
6
SO
7
8
9
10
11
12
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NX25F011B
NX25F021B
NX25F041B
Write to Sector Through SRAM (F3H)
Before writing to a sector in the Flash memory array, all
hardware and software write protection must be in an
enabled state. This means that the WP pin must be in a
high state, a Write Enable command must have previously been issued, and the sector location that is to be
written to must be outside the write protect range set in
the configuration register. Additionally, the Ready/Busy
status should be checked to confirm that the memory
array is available to be written to.
Writing to a sector is accomplished by first bringing CS
low and shifting in the Write to Sector command (F3H)
followed by a 16-bit “sector-address” field. Although the
sector-address field is 16-bits, only bits S[8:0] for the
NX25F011B (0-1FFH), S[9:0] for the NX25F021B
(0-3FFH), or S[10:0] for the NX25F041B (0-7FFH) are
used. The uppermost sector address bits are not used
but must be clocked in (use 0 data). Following the sector
address, a 16-bit “byte-address” field is clocked into the
device to designate the starting location within the 264-byte
sector. Only bits B[8:0] of the byte-address field are used
and only values of 0-107H (264 bytes) are valid.
SI
After the byte-address has been loaded, data is shifted
into the 264-byte SRAM, which serves as a temporary
storage buffer. Existing data in the SRAM will be written
over. The byte order of the data shifted into the SRAM is
least significant byte first (i.e., byte-00H, byte-01H,...).
The bit order within each byte is most significant bit first
(i.e., D7,...D0). The byte-address is automatically incremented to the next higher byte address as the clock
continues. When the last byte address to be written is
reached, the command can be completed with an
additional eight control clocks (with data=0) followed by
asserting CS high. If the clock continues to increment
past the highest byte-address (107H), the address counter
will roll over to byte 0H.
After the CS pin is brought high, the data in the SRAM is
transferred to the specified sector in memory array. See
tWP timing specifications. During this time the array and
SRAM will be “busy” and will ignore further array-related
commands until complete. All Ready/Busy status indicators will indicate a busy status. Detailed clock timing
for the Write to Sector command is shown in Figure 11.
Write to
Sector
Command
Sector
Address*
Byte
Address**
Write Sector Data
F3H
S[15:0]
B[15:0]
First Byte - Last Byte
8 Clocks
00H
Program
Time
(tWP)
SO
*The sector address only uses bits [8:0], [9:0] or [10:0]
**The byte address only uses bits [8:0]
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NX25F011B
NX25F021B
NX25F041B
SERIAL SRAM COMMANDS
Write to SRAM Command (72H)
The Write to SRAM command (72H) provides access to
the 264-Byte SRAM independently of any Flash memory
array operation. When CS is asserted high to complete
the command, the contents of the SRAM will be maintained until overwritten through another command or the
power is removed. Using the Write to SRAM command,
Write to
SRAM
Command
72H
SI
data can be loaded in preparation of writing to a sector in
memory and then transferred to a selected sector using
the Transfer SRAM to Sector command. The TR bit in the
status register should be checked first if Transfer Sector to
SRAM or Compare Sector to SRAM commands are used.
1
2
3
Byte
Address*
B[15:0]
Write Sector Data
8 Clocks
First Byte - Last Byte
00H
4
SO
5
*The byte address only uses bits [8:0]
6
7
Read from SRAM (71H)
The Read from SRAM command (71H) provides access to
the 264-Byte SRAM independent of any Flash memory
array operations. The TR bit in the status register should be
checked first if Transfer Sector to SRAM or Compare Sector
to SRAM commands are used.
Read from
SRAM
Command
Byte
Address*
8 Clocks
71H
B[15:0]
00H
SI
SO
8
9
10
11
First Byte-Last Byte
Read SRAM Data
*The byte address only uses bits [8:0]
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NX25F011B
NX25F021B
NX25F041B
Transfer All of SRAM to Sector (F3H)
The Transfer SRAM to Sector command (F3H) will
write the existing contents of the SRAM to the specified sector in memory. The command sequence is
identical to that of the Write to Sector command
except that immediately after the sector address field
S[15:0] and 16 control clocks, the CS pin is asserted
high. This automatically transfers the 264-bytes of
SRAM data to the specified sector in the memory array.
During this time, the array will be busy. Since the entire
264-bytes are transferred, the byte-address field B[15:0]
is not used.
Transfer SRAM
Sector
to Sector
Address*
Command
SI
F3H
S[15:0]
16 Clocks
Program Time
0000H
(tWP)
SO
*The sector address only uses bits [8:0], [9:0] or [10:0]
Depending on device density
Transfer All of Sector to SRAM (53H)
The Transfer Sector to SRAM command (53H) allows the
contents of a sector to be transferred directly to the SRAM
without having to clock or read the sector out of the device
and rewrite it into the SRAM. During the transfer, the SO
output is in a high-impedance state and the TR bit in the
status register will be set to a "1" state. When the last byte
address is transferred the TR bit in the status register will be
cleared. Note that the Transfer Sector to SRAM Clocked
command (54H) can also be used if partial transfers are
required.
20
Transfer Sector
Sector
to SRAM
Address*
Command
SI
53H
S[15:0]
32
Clocks
Transfer Time
0000 0000H
(tXS)
SO
*The sector address only uses bits [8:0], [9:0] or [10:0]
Depending on device density
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NX25F011B
NX25F021B
NX25F041B
Compare Sector to SRAM (8DH)
The Compare Sector to SRAM command (8DH) does a
bit-by-bit comparison of the data stored in the addressed
sector against data in the SRAM. The TR bit will be 1 during
the transfer compare operation. If any of the compared bits
are not equal, then the Compare Not Equal (CNE) bit in the
Status Register is set to a 1. This bit will stay set until a Clear
Compare Sector
Sector
with SRAM
Address*
Command
SI
8DH
S[15:0]
Compare Status command has been issued. Note that the
Compare Sector to SRAM Clocked command can be used
if partial compares are required. This command is very
useful for performing a fast verify of the Last Sector write
operation. This verify provides for the highest data integrity.
Sector
Address*
16 Clocks
Compare Time
B[15:0]
0000H
(tXS)
1
2
3
SO
4
*The sector address only uses bits [8:0], [9:0] or [10:0]
Depending on device density
5
6
7
CONFIGURATION AND STATUS
COMMANDS
8
Read Configuration Register (8CH)
The Read Configuration Register command provides
access to the configuration register, which stores the
current configuration of the HOLD-R/B pin, read clock
edge, write protect range, and alternate oscillator
frequency (Figure 7). A 16-bit Configuration Data field
CF[15:0] provides the contents of the Configuration
Register. Although the field is 16-bits long, only bits
CF[7:0] are used. All other upper bits are reserved for
future features.
Read Configuration
Register
Command
SI
SO
9
8CH
10
CF{15:0}*
Read Configuration Bits
11
*The CF Register only uses bits [7:0]
12
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PRELIMINARY NXSF016F-1201
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21
NX25F011B
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NX25F041B
Write Non-Volatile Configuration
Register (8AH)
The Write Configuration Register command provides access to the configuration register which stores the current
configuration of the HOLD-R/B pin, read-data clock edge,
write protect range, and alternate oscillator frequency. The
configuration register is non-volatile. Once set using the
Write Configuration Register command, the contents will
maintain even when power is removed. Because the
register’s state is stored in non-volatile memory, there is
a finite endurance limit to the number of times it can be
written to. To limit the number of writes, it is recommended
that before writing to the configuration register it should
first be read from using the Read Configuration Register
command. If no change is required, the Write Configuration
Register command can be skipped. This process will help
extend the endurance of the configuration register bits and
eliminate additional programming “busy” time.
The Write Configuration Register command sequence
starts with the command byte (8AH) followed by a 16-bit
field that specifies configuration register bit settings.
Although the field is 16-bits long, only bits CF[7:0] are
used. All other upper bits are reserved and must be
clocked using 0 for data. After an additional 16 control
clocks using 0 for data, the command can be completed
by asserting CS high. The device will become busy for a
short time (tWP) while the non-volatile memory cells of the
configuration register are programmed.
Write
Configuration
Configuration
Register
Bits*
Command
16 Clocks
SI
8AH
CF[15:0]
Program Time
(tWP)
0000H
SO
*The CF Register only uses bits [7:0]
Read Status Register (84H)
The Read Status Register command provides access to
the status register and its status flags for Ready/Busy
(R/B), SRAM and program buffer transfer operations (TX),
Write Enable/Disable (WE), and Compare Not Equal (CNE)
(Figure 8). An 8-bit Status field ST[7:0] provides the
contents of the Status Register.
Read Status
Register
Command
SI
SO
84H
ST[7:0]
Read Status Register Bits
22
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Clear Compare Status (89H)
The Clear Compare Status command (89H) works in conjunction with the Compare Sector to SRAM command and
the Status Register. If any of the compared bits are not
equal, then the Compare Not Equal (CNE) bit in the Status
Register is set to a 1. The Clear Compare Status command
must be executed to reset the CNE bit to a 0.
Clear Compare
Status
Command
8 Clocks
SI
89H
1
00H
2
SO
3
4
Set Power Detection Bit (03H)
The Set Power Detection Bit command (03H) can be used
to detect if power has been removed from the device. The
command works in conjunction with the Power Detect (PD)
status bit. Upon power up the PD bit is cleared to 0. The PD
bit can be set to a 1 using the Set Power Detection Bit
command. Once set, if a power down condition occurs
(Vcc voltage < 2V) the PD bit will reset to 0. This function
is especially useful for applications using NexFlash Serial
Flash Modules or other removable media.
SI
5
Set Power
Detection
Bit
8 Clocks
03H
00H
6
SO
7
8
9
10
Reset Power Detection Bit (09H)
The Reset Power Detection Bit command (09H) can be used
to force the Power Detect Status bit in the status register to
a 0 state. (see Set Power Detection Bit command (03H).
SI
Reset Power
Detection
Bit
8 Clocks
09H
00H
11
SO
NexFlash Technologies, Inc.
PRELIMINARY NXSF016F-1201
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12
23
NX25F011B
NX25F021B
NX25F041B
Read Device Information Sector (15H)
The Read Device Information command provides access
to a read-only sector that can be used to electronically
identify the NexFlash Serial Flash device being interfaced to. Information available includes: part number,
density, voltage, temperature range, package type, and
any special options. This can be extremely useful for
systems that need to accommodate optional densities
SI
Read Device
Info. Sector
Command
16 Clocks
Byte
Address*
16 Clocks
15H
0000H
B[15:0]
0000H
SO
*The byte address only uses bits [8:0]
(e.g., both 1M-bit or 2M-bit). In this case the firmware can
interrogate the Device Information Sector and
determine the density. The Device Information Sector
also includes a list of any restricted sectors that might
exist in the device. Contact NexFlash for more detailed
information on the Device Information Sector format.
RB[15:0]
Read/Busy
Status
First Byte - Last Byte
Read Sector Data
SPECIAL SECTOR COMMANDS
Erase Sector (F1H)
The Erase Sector command (F1H) will erase a sector to an
“all 1s” state, during this time the array will be "busy." This
command can be used in conjunction with the Write only to
Sector through SRAM command (F2H) to achieve faster
program performance in applications that can accommodate pre-erase. (see T EO in AC Characteristics for
erase timing).
SI
Erase
Sector
Command
Sector
Address*
16
Clocks
Transfer Time
F1H
S[15:0]
0000H
(tEO)
SO
*The sector address only uses bits [8:0], [9:0] or [10:0]
Depending on device density
24
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Erase Block (F4H)
The Erase Block command (F4H) will erase a block of 32
sectors to an “all 1s” state, during this time the array will be
"busy." This command can be used in conjunction with the
Write only to Sector through SRAM command (F2H) to
achieve faster program performance in applications that
can accommodate pre-erase. (see TEO in AC Characteristics for erase and write timing).
SI
Erase
Block
Block
Address*
16
Clocks
Transfer Time
F4H
BLK[15:0]
0000H
(tEO)
1
2
SO
*The Block address only uses bits [8:5], [9:5] or [10:5]
Depending on device density. Lowest four bit [4:0] must be 0h
3
4
5
6
Write-only to Sector (F2H)
The Write-Only to Sector through SRAM command (F2H)
will write a pre-erased sector in about half the time of the
standard Write to Sector through SRAM command (F3H),
during this time the array will be "busy." This command
can be used in conjunction with the Erase Sector command (F1H) or Erase Block command (F4H) to achieve
SI
faster program performance in applications that can
accommodate pre-erase. (see TWO inAC Characteristics
for erase and write timing). Warning: to ensure data integrity this command should only be issued after an erase
command.
Write only
to Sector
Command
Sector
Address*
Byte
Address**
Write Sector Data
F2H
S[15:0]
B[15:0]
First Byte - Last Byte
8 Clocks
00H
7
8
9
Program
Time
(tWP)
10
SO
*The sector address only uses bits [8:0], [9:0] or [10:0] Depending on device density
**The byte address only uses bits [8:0]
11
12
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NX25F011B
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COMPATIBILITY COMMANDS FOR 25xxxA
SERIES DEVICES
Read from SRAM (81H)
The Read from SRAM command (81H) provides access to
the 264-Byte SRAM independent of any Flash memory
array operations. The command is similar to the Read from
SI
Read from
SRAM
Command
16 Clocks
Byte
Address*
16 Clocks
81H
0000H
B[15:0]
0000H
SO
Sector command except for the sector address field
S[15:0] which is replaced with all 0 bits.
RB[15:0]
Read/Busy
Status
*The byte address only uses bits [8:0]
First Byte - Last Byte
Read SRAM Data
Write to SRAM (82H)
The Write to SRAM command (82H) provides access to
the 264-Byte SRAM independently of any Flash memory
array operation. The command is similar to the Write to
Sector command sequence except that the sector
address field S[15:0] is replaced by all 0 bits. When CS
is asserted high to complete the command, the contents
SI
of the SRAM will be maintained until overwritten through
another command or the power is removed. Using the
Write to SRAM command, data can be loaded in preparation of writing to a sector in memory and then transferred
to a selected sector using the Transfer SRAM to Sector
command.
Write to
SRAM
Command
16 Clocks
Byte
Address*
Write Sector Data
8 Clocks
82H
0000H
B[15:0]
First Byte - Last Byte
00H
SO
*The byte address only uses bits [8:0]
26
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Read Configuration Register (8BH)
The Read Configuration Register command provides
access to the configuration register, which stores the
current configuration of the HOLD-R/B pin, read clock
edge, write protect range, and alternate oscillator
frequency (Figure 7). The command sequence is similar
to the Read from Sector command except that the sector
address field S[15:0] and the byte-address field B[15:0]
Read Configuration
Register
16 Clocks
Command
SI
8BH
0000H
are replaced with all 0 bits. After 16 control clocks and
after the Ready/Busy status field has been clocked
through, a 16-bit Configuration Data field CF[15:0]
provides the contents of the Configuration Register.
Although the field is 16-bits long, only bits CF[7:0] are
used. All other upper bits are reserved for future
features.
1
2
3
16 Clocks
16 Clocks
0000H
0000H
SO
*The CF Register only uses bits [7:0]
4
RB[15:0]
CF{15:0}*
Read/Busy
Status
Read Configuration Bits
5
6
7
Read Status Register (83H)
The Read Status Register command provides access to
the status register and its status flags for Ready/Busy
(R/B), SRAM and program buffer transfer operations (TX),
Write Enable/Disable (WE), and Compare Not Equal (CNE)
(Figure 8). The command sequence is similar to the Read
SI
From Sector command except that the sector address
field S[15:0] and the byte-address field B[15:0] are replaced
by all 0 bits. After 16 clocks and the Ready/Busy status field
RB[15:0] has been read, an 8-bit Status field ST[7:0]
provides the contents of the Status Register.
16 Clocks
16 Clocks
16 Clocks
83H
0000H
0000H
0000H
SO
11
RB[15:0]
ST[7:0]
Read/Busy Read Status
Register Bits
Status
NexFlash Technologies, Inc.
12/12/01 ©
9
10
Read Status
Register
Command
PRELIMINARY NXSF016F-1201
8
12
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NX25F011B
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Transfer Sector to SRAM Clocked (54H)
The Transfer Sector to SRAM Clocked command (54H)
allows the contents of a sector to be transferred directly to
the SRAM without having to read the sector out of the device
and rewrite it into the SRAM. The command is similar to the
Write to Sector command except that instead of inputting
data from the SI pin, the data is taken from the specified
sector and is transferred to the SRAM. Every eight clocks
on SCK, a byte from the specified sector to the SRAM will
be transferred. Although data on SI is ignored, it is recomTransfer Sector
Sector
to SRAM
Address*
Command
SI
Byte
Address**
8 Clocks per Byte Trasnfered
from First Byte to Last Byte
8 Clocks
B[15:0]
SI=00H During Byte Ttansfers
00H
S[15:0]
54H
mended to write data bytes of 00H in order to support the
clocking requirements. During the transfer, the SO output is
in a high-impedance state. When the last byte address is
transferred, the command can be completed by issuing
eight more control clocks and asserting CS high. If the clock
continues to increment past the highest byte-address
(107H), the address counter will roll over to byte-0H. This
command can also be used to load partial sectors into
SRAM
SO
*The sector address only uses bits [8:0], [9:0] or [10:0] Depending on device density
**The byte address only uses bits [8:0]
Compare Sector to SRAM Clocked (86H)
The Compare Sector to SRAM command does a bit-by-bit
comparison of the data stored in the addressed sector
against data in the SRAM. The command is similar to the
Read from Sector command except that data is not read out
of the Serial Output pin (SO). Instead, the SO pin provides
a bit-by-bit compare of each sector and SRAM bit. A high (1)
per bit will be output if the bit compare is equal. A low (0) per
bit will be output if the bit compare is not equal. The compare
can start from any location in the 264-byte range as
Compare Sector
Sector
with SRAM
Address*
Command
SI
SO
86H
S[15:0]
Byte
Address**
16 Clocks
B[15:0]
0000H
specified by the byte-address field B[15:0]. The
byte-address counter is automatically incremented and will
wrap around to the first address (0H) if it passes the last
address (107H). If any of the compared bits are not equal,
then the Compare Not Equal (CNE) bit in the Status Register
is set to a 1. This bit will stay set until a Clear Compare
Status command has been issued. This command can also
be used to load partial sectors into SRAM
RB[15:0]
Read/Busy
Status
First Byte - Last Byte
Bit Compare of Sector
and SRAM
*The sector address only uses bits [8:0], [9:0] or [10:0] Depending on device density
**The byte address only uses bits [8:0]
28
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Sector Format
The memory array of standard Serial Flash devices are
factory programmed to a full erase state with all bits set to
“1” (FFH). NexFlash also offers restricted sector devices
(with “-R” suffix) which may provide a more cost effective
alternative to standard devices that have 100% valid
sectors. Restricted sector devices have a limited number
of sectors that do not meet manufacturing programming
criteria over the specified operating range. The first bye of
each good sector in a “-R” device is pre-programmed during
manufacturing with a tag/sync value of C9H. Although this
byte location of the sector can be changed, it is recommended that it be maintained and incorporated into the
application’s sector formatting. The tag/sync values serve
two purposes. First, they provide a sync-detect that can
help verify if the command sequence was clocked into the
device properly. Secondly, they serve as a tag to identify
a fully functional (valid) sector. For defective sectors, the
first byte is tagged with a pattern other than C9H. In addition
to individual sector tagging, all restricted sectors for a given
device are listed in the Device Information Sector. For more
information see the latest version of Device Information
Sector Application Note SFAN-02.
High Data Integrity Applications
Data storage applications that use Flash memory or other
non-volatile media must take into consideration the possibility of noise or other adverse system conditions that may
affect data integrity. For those applications that require
higher levels of data integrity it is a recommended practice
to use Error Correcting Code (ECC) techniques. The
NexFlash Serial Flash Development Kit provides a software
routine for a 32-bit ECC that can detect up to two bit errors
and correct one. The ECC not only minimizes problems
caused by system noise but can also extend Flash memory
endurance.
Grouping Static and Frequently
Updated Data
In the NX25F011B/021B/041B a data block is every 32
sectors starting from sector 0; that is, block 0 is sector
0 - 31, block 1 is sector 32 - 63 and so on. Refer to figure
4. For the highest data integrity, it is important to separate
static data (configuration settings, tables) and frequently
updated data (streaming voice/image or data acquisition)
into separate blocks. Following this convention optimizes
the environment for the data stored in the flash cells within
each block.
PRELIMINARY NXSF016F-1201
12/12/01 ©
3
4
Write to SRAM Command
5
Transfer SRAM to Sector Command
6
7
Ready?
Programming
Done?
NO
8
YES
Compare Sector with SRAM Command
Equivalent
NexFlash Technologies, Inc.
2
Write Verify
Write/Verify Flow
For those systems without the processing power to handle
ECC algorithms, a simple “verification after write” is recommended. The write verify can be done quickly (less than tXS)
using the Compare Sector command. The compare result
can be checked in the Status Register. If compare is not
equal (CNE=1) then a sector rewrite should be done using
the Transfer to Sector command (Figure 12). A single retry
is adequate for most applications. However, if an application requires extended endurance additional retrys can be
added. The Serial Flash Development Kit software includes
a simple Write/Verify routine that will compare data written
to a given sector and rewrite the sector if the compare is
not correct.
1
YES
9
NO
10
Retry
Counter
Retry
11
No More
Retries
Return
Error
12
Figure 12. Write/Verify Flow
29
NX25F011B
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ABOSOLUTE MINIMUM RATINGS (1)
Symbol
Vcc
VIN, VOUT
TSTG
TLEAD
Parameters
Supply Voltage
Voltage Applied to Any Pin
Storage Temperature
Lead Temperature
Conditions
Range
0 to 7.0
–0.5 to Vcc + 0.5
–65 to +150
+300
Relative to Ground
Soldering 10 Seconds
Unit
V
V
°C
°C
Note:
1. This device has been designed and tested for the specified operation ranges. Proper operation outside of these levels is not
guaranteed. Exposure beyond absolute maximum ratings (listed above) may cause permanent damage.
OPERATING RANGES
Symbol
Vcc
Parameter
Supply Voltage (1)
TA
Ambient Temperature, Operating
TRVCC
Power Ramp Time
Conditions
5.0V programing
3.0V or 3.3 V programing
Commercial
Extended
Industrial
Min
4.5
2.7
0
–20
–40
Max
5.5
3.6
+70
+70
+85
Unit
V
V
°C
°C
°C
—
10
ms
Note:
1. Vcc voltage during Read can operate across the min and max range but should not exceed ±10% of the programming
(erase/write) voltage.
DC ELECTRICAL CHARACTERISTICS
Symbol
VI L
VI H
VO L
VOH
VOLC
VOHC
IIL
IOL
ICC
(active)
I CCLF
(low
frequency)
ICCSB
(standby)
CIN
COUT
Parameter
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage CMOS
Output High Voltage CMOS
Input Leakage
I/O Leakage
Active Power Supply Current
Active Current Low
Frequency. Read
(Preliminary)
(2)
Conditions
IOL = 2 mA
VCC = 4.5V
IOH = –400 µA
VCC = 4.5V
VCC = Min, IOL = 10 µA
VCC = Min, IOH = –10 µA
0 < VIN < Vcc
0 < VIN < Vcc
fCLK @ 8 MHz (1/tCP) VCC = 5V
VCC = 3V
fCLK @1 MHz (1/tCP) VCC = 5V
VCC = 3V
Standby Vcc Supply Current CS = VCC,
Vcc = 5V
VIN = Vcc or 0
Vcc = 3V
Input Capacitance (1)
TA = 25°C, VCC = 5V or 3V
Frequency = 1 MHz
(1)
Output Capacitance
TA = 25°C, VCC = 5V or 3V
Frequency = 1 MHz
Min
–0.4
Vccx0.6
—
2.4
—
VCC–0.3
–10
–10
5
2
2
1
Typ
—
—
—
—
—
—
—
—
6
2.5
4
1.5
Max
Vccx0.2
Vcc+0.5
0.45
—
0.15
—
+10
+10
8
4
5
2
Unit
V
V
V
V
V
V
µA
µA
mA
mA
mA
mA
—
—
—
5
1
—
10
5
10
µA
µA
pF
—
—
10
pF
Notes:
1. Tested on a sample basis or specified through design or characterization data.
2. See Preliminary Designation page 31
30
NexFlash Technologies, Inc.
PRELIMINARY NXSF016F-1201
12/12/01 ©
NX25F011B
NX25F021B
NX25F041B
AC ELECTRICAL CHARACTERISTICS
(Preliminary)
Symbol
Description
FREQ
Clock Frequency
tCYC
SCK Serial Clock Period (1)
tWH
tWL
tRI
tFI
tSU
tIH
tOH
tV
Data Input Hold Time from SCLK
Data Output Hold Time from SCLK
Data Output Valid after SCLK (1,3)
tCSS
tCSH
tWP
CS Setup Time to Command
CS Hold Time after Command
Erase/Write Program Time
(see Write to Sector Command)
Erase Only Time
(see Erase Sector/Block Commands)
Write Only Time
(see Write Only to Sector Command)
Transfer or Compare Sector
(see Transfer/Compare All Command)
SCK Setup Time to HOLD
SCK Hold Time from HOLD
CS Deselect Time
READY / BUSY Valid Time
Data Output Disable Time
Data Disable/Enable from HOLD
tEO
tWO
tXS
tHD
tCD
tCS
tRB
tDIS
tHZ
(4)
Fast SPI
(RCE =1)
Min Typ Max
=
=
=
=
5V
3V
5V
3V
Unit
1
SCK Serial Clock High or Low Time
0
0
50
50
24
—
—
—
—
—
20
20
—
—
—
0
0
80
100
24
—
—
—
—
—
12
10
—
—
—
MHz
MHz
ns
ns
ns
SCK Serial Clock Rise or Fall Time (2)
—
—
5
—
—
5
ns
14 —
25 —
0
—
0
—
— —
— —
100 —
100 —
— 7.5
—
—
—
—
35
45
—
—
20
14
25
0
0
—
—
100
100
—
—
—
—
—
—
—
—
—
7.5
—
—
—
—
35
45
—
—
20
ns
ns
ns
ns
ns
ns
ns
ns
ms
2
4
ms
16
ms
— 100 150
µs
Data Input Setup Time to SCLK
Vcc
Vcc
Vcc
Vcc
Standard SPI
(RCE = 0)
Min Typ Max
Vcc = 5V
Vcc = 3V
Vcc = 5V
Vcc = 3V
—
2
4
—
—
5.5
16
— 5.5
—
100 150
10
30
160
160
—
—
—
—
—
—
—
—
—
—
—
—
60
60
10
30
160
160
—
—
—
—
—
—
—
—
—
—
—
—
60
60
2
3
4
5
6
7
8
ns
ns
ns
ns
ns
ns
9
10
Notes:
1. To achieve maximum clock performance, the read clock edge will need to be set for rising edge operation in the configuration
register (RCE=1).
2. Test points are 10% and 90% points for rise/fall times. All others timings are measured at 50% point.
3. With 30 pF (16 MHz) load SO to GND.
4. See Preliminary Designation page 31
11
12
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12/12/01 ©
31
NX25F011B
NX25F021B
NX25F041B
SERIAL OUTPUT TIMING
CS
tCYC
tWH
tCSH
SCK
tV
SO
MSB
tWL
tOH
MSB-1
tDIS
LSB+1
LSB
SI
SERIAL INPUT TIMING
tCS
CS
tCSS
SCK
tSU
SI
tRI
tFI
tCSH
tIH
MSB
LSB+1
MSB-1
LSB
tRB
(High Impedance)
SO
tXS
tWP
R/B
HOLD TIMING
CS
tCD
tHD
tHD
tCD
SCK
tHZ
tHZ
SO
SI
HOLD
32
NexFlash Technologies, Inc.
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12/12/01 ©
NX25F011B
NX25F021B
NX25F041B
PACKAGING INFORMATION
200-mil Plastic SOIC
Package Code: (S)
1
N
2
E
3
H
4
1
SEATING PLANE
D
A
B
e
5
A1
L
a
6
C
7
8
200 mil Plastic SOIC (S)
Symbol
No. Leads
A
A1
B
C
D
E
e
H
L
α
Millimeters
Min
Max
8
1.780
2.030
0.102
0.330
0.305
0.508
0.178
0.254
5.160
5.380
5.210
5.410
1.27BSC
7.62
8.38
0.508
0.889
o
0
8o
NexFlash Technologies, Inc.
PRELIMINARY NXSF016F-1201
12/12/01 ©
Inches
Min
Max
0.070
0.080
0.004
0.013
0.012
0.020
0.007
0.010
0.203
0.212
0.205
0.213
0.050 BSC
0.300
0.330
0.020
0.035
o
0
8o
9
10
Notes:
1. Controlling dimensions: inches, unless otherwise
specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold flash
protrusions and should be measured from the
bottom of the package.
4. Formed leads shall be planar with respect to one
another within .0004 inches at the seating plane.
11
12
33
NX25F011B
NX25F021B
NX25F041B
PACKAGING INFORMATION
330 mil Plastic SOIC
Package Code: (J)
N
H
E
1
D
SEATING PLANE
A
B
e
L
A1
α
C
330 Mil Plastic SOIC (J)
Symbol
Ref. Std.
No. Leads
A
A1
B
C
D
E
H
e
L
a
34
Millimeters
Min
Max
Inches
Min
Max
28
2.388 2.794
0.051 0.508
0.051 0.356
0.203 0.305
7.983 8.288
8.585 8.788
11.68 12.19
1.27 BSC
0.762 1.270
0°
8°
0.094 0.110
0.002 0.020
0.002 0.014
0.008 0.0012
0.709 0.720
0.338 0.346
0.460 0.480
0.050 BSC
0.030 0.050
0°
8°
Notes:
1. Controlling dimension: inches, unless
otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E do not include mold
flash protrusions and should be measured
from the bottom of the package.
4. Formed leads shall be planar with respect
to one another within 0.004 inches at the
seating plane.
NexFlash Technologies, Inc.
PRELIMINARY NXSF016F-1201
12/12/01 ©
NX25F011B
NX25F021B
NX25F041B
PACKAGING INFORMATION
Plastic TSOP - 28-pins
Package Code: Type I (V)
1
1
2
3
E
H
4
5
N
D
6
SEATING PLANE
A
7
e
B
L
A1
α
C
8
Plastic TSOP Type I (V)
Millimeters
Inches
Symbol Min Max
Min Max
No. Leads
28
A
1.00 1.20
0.039 0.047
A1
0.05 0.20
0.002 0.008
B
0.15 0.25
0.006 0.010
C
0.10 0.20
0.004 0.008
D
7.90 8.10
0.311 0.319
E
11.60 11.80
0.457 0.465
H
13.30 13.50
0.524 0.531
e
0.55 BSC
0.022 BSC
L
0.50 0.70
0.020 0.028
α
0°
5°
0°
5°
NexFlash Technologies, Inc.
PRELIMINARY NXSF016F-1201
12/12/01 ©
9
10
Notes:
1. Controlling dimension: millimeters, unless
otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E do not include mold flash
protrusions and should be measured from the
bottom of the package.
4. Formed leads shall be planar with respect to one
another within 0.004 inches at the seating plane.
11
12
35
NX25F011B
NX25F021B
NX25F041B
PRELIMINARY DESIGNATION
LIFE SUPPORT POLICY
The “Preliminary” designation on an NexFlash data sheet
indicates that the product is not fully characterized. The
specifications are subject to change and are not guaranteed. NexFlash or an authorized sales representative
should be consulted for current information before using this
product.
NexFlash does not recommend the use of any of it's
products in life support applications where the failure or
malfunction of the product can reasonably be expected to
cause failure in the life support system or to significantly
affect its safety or effectiveness. Products are not
authorized for use in such applications unless NexFlash
receives written assurances, to it’s satisfaction, that:
IMPORTANT NOTICE
NexFlash reserves the right to make changes to the
products contained in this publication in order to improve
design, performance or reliability. NexFlash assumes no
responsibility for the use of any circuits described herein,
conveys no license under any patent or other right, and
makes no representation that the circuits are free of patent
infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary
depending upon a user’s specific application. While the
information in this publication has been carefully checked,
NexFlash shall not be liable for any damages arising as a
result of any error or omission.
(a)
the risk of injury or damage has been minimized;
(b)
the user assumes all such risks; and
(c)
potential liability of NexFlash is adequately protected under the circumstances.
Trademarks:
NexFlash is a trademark of NexFlash Technologies, Inc. All
other marks are the property of their respective owner.
ORDERING INFORMATION
Size
Order Part No.
Package
1M-bit
NX25F011B-3V*
SPI, 28-pin, TSOP (Type I)3V
1M-bit
NX25F011B-3S*
SPI, 8-pin, SOIC 3V
1M-bit
NX25F011B-5V*
SPI, 28-pin, TSOP (Type I) 5V
1M-bit
NX25F011B-5S*
SPI, 8-pin, SOIC 5V
2M-bit
NX25F021B-3V*
SPI, 28-pin, TSOP (Type I) 3V
2M-bit
NX25F021B-3S*
SPI, 8-pin, SOIC 3V
2M-bit
NX25F021B-5V*
SPI, 28-pin, TSOP (Type I) 5V
2M-bit
NX25F021B-5S*
SPI, 8-pin, SOIC 5V
4M-bit
NX25F041B-3V*
SPI, 28-pin, TSOP (Type I) 3V
4M-bit
NX25F041B-3J
SPI, 28-pin, SOIC 3V
4M-bit
NX25F041B-5V*
SPI, 28-pin, TSOP (Type I) 5V
4M-bit
NX25F041B-5J
SPI, 28-pin, SOIC 5V
*Note:
Add -R for Restricted Sector Device (See Serial Flash Application Note SFAN-2 for more information on
restricted sector devices).
36
NexFlash Technologies, Inc.
PRELIMINARY NXSF016F-1201
12/12/01 ©
NX25F011B
NX25F021B
NX25F041B
1
2
3
4
5
6
7
8
9
10
11
12
NexFlash Technologies, Inc.
PRELIMINARY NXSF016F-1201
12/12/01 ©
37